EP1889434A1 - Differentielle detektionseinheit für den zigbee 802.15.4 standard - Google Patents
Differentielle detektionseinheit für den zigbee 802.15.4 standardInfo
- Publication number
- EP1889434A1 EP1889434A1 EP06754002A EP06754002A EP1889434A1 EP 1889434 A1 EP1889434 A1 EP 1889434A1 EP 06754002 A EP06754002 A EP 06754002A EP 06754002 A EP06754002 A EP 06754002A EP 1889434 A1 EP1889434 A1 EP 1889434A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- sequence
- unit
- derived
- chip
- group
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/233—Demodulator circuits; Receiver circuits using non-coherent demodulation
- H04L27/2331—Demodulator circuits; Receiver circuits using non-coherent demodulation wherein the received signal is demodulated using one or more delayed versions of itself
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/70735—Code identification
Definitions
- the present invention relates to a detection unit for detecting data symbols contained in a differentially demodulated signal.
- the invention further relates to a transmitting / receiving device and an integrated circuit with such a detection unit.
- the invention is in the field of data transmission, although applicable in principle to any digital communication systems, the present invention and its underlying problem will be explained below with reference to a "ZigBee" communication system according to IEEE 802.15.4.
- WP ANs Wireless Personal Area Networks
- WLANs Wireless Local Area Networks
- the IEEE 802.15.4 standard specifies low-speed WPANs that can be programmed with raw data rates up to max. 250 kbit / s and fixed or mobile devices are suitable for applications in industrial monitoring and control, in sensor networks, in automation, as well as in the field of computer peripherals and for interactive games.
- extremely low energy consumption of the devices is of crucial importance for such applications. For example, battery life of several months to several years is the goal of this standard.
- PN pseudo-noise
- the sequence set of 16 "quasi-orthogonal" PN sequences specified in the standard comprises a first group of eight first PN sequences, which differ from each other only by a cyclical shift of their chip values, and a second group of eight second PN sequences. Sequences which also differ only by a cyclical shift of their chip values from each other and by one of the first PN sequences only by an inversion of every other chip value (see IEEE Std 802.15.4-2003, chapter 6.5.2.3).
- the PN sequences assigned to the consecutive symbols are concatenated and then offset QPSK (quaternary phase shift keying) modulated by the half-sine pulse shaping PN (0, 2, 4, ...) PN chips the inphase (I) carrier and those odd-index PN chips (1, 3, 5, ...) are modulated onto the quadrature-phase (Q) carrier, the quadrature-phase chips become one to form an offset Chipping diode TC delayed compared to the in-phase chips (see IEEE Std 802.15.4-2003, chapter 6.5.2.4).
- both coherent and incoherent approaches are known per se for the detection of data symbols contained in a received signal.
- the present invention is based on an incoherent receiver, wherein the received signal at least not in-phase converted into the complex envelope and the resulting baseband signal is differentially demodulated.
- the invention is based on the object, to provide a detection unit for detecting data symbols contained in a differentially demodulated signal, which enables energy-saving and simple implementations of transmit receive devices, eg according to IEEE 802.15.4, and nevertheless has a high performance of the detection, ie a low error rate (symbol, bit)
- a detection unit for detecting data symbols contained in a differentially demodulated signal
- transmit receive devices eg according to IEEE 802.15.4
- a high performance of the detection ie a low error rate (symbol, bit
- ⁇ br/> ⁇ br/> ⁇ br/> According to the invention, this object is achieved by a detection unit, a transmitting receiving device and an integrated circuit with the Features of the claims 1, 22 and 23, respectively.
- a detection unit for detecting data symbols contained in a differentially demodulated signal, to each of which a PN sequence from a sequence store can be assigned, a first group of first PN sequences and a second group of second PN sequences wherein the first and second PIM sequences within their respective group differ from one another only by a cyclical shift of their chip values, and wherein the second group has for each first PN sequence a corresponding second PN sequence which differs from the first PN sequence.
- Distinguishing sequence only by an inversion of every other chip value comprising a) a sequence providing unit configured to provide a third group of derived sequences, the third group having for each first PN sequence a derived sequence comprising said first PN sequence.
- a correlation unit connected to the sequence providing unit, which calculates correlation results by correlating the differentially demodulated Si - A - gnals is formed with each of the derived sequences of the third group, and c) an evaluation unit connected to the correlation unit, which is designed to derive the values of the data symbols by evaluating the correlation results.
- the inventive transmitting / receiving device and the integrated circuit according to the invention each have such a detection unit.
- the essence of the invention is to provide a third group of derivative sequences adapted for differential demodulation and to correlate the differentially demodulated signal to each derived sequence of the third group.
- the derived sequences of the third group are not identical to the PN-sequences which can be used on the transmitting side, but are derived from these and differ in contrast to the PIM sequences which can be used on the transmitting side only by a cyclic shifting of their chip values from one another. This allows a differentially demodulated signal to be transmitted at the transmitting end e.g. according to IEEE 802.15.4, to correctly detect (decide).
- the particular properties of the derived sequences enable extremely simple and energy-saving implementations of the detection unit and thus of the transceiver devices.
- the sequence providing unit has exactly one storage means which is designed to store exactly one (ie only one) of the derived sequences.
- a storage medium whose size is so can be advantageously implemented very simple and energy-saving operation.
- the storage means is preferably designed as a feedback shift register.
- the very simple structure of a shift register made up of register cells connected in series enables a very efficient and simple realization of the sequence providing unit with very low energy requirement. For example, neither a calculation of memory addresses nor a complex control logic for the shift register is required.
- the sequence providing unit provides the derived sequences of the third group at outputs of respective (plural) register cells of the shift register.
- means for clocking the feedback shift register are provided in the chip clock. In this way, it is very easy to provide all the derived sequences of the third group with or without temporal offset among each other.
- the sequence providing unit has a counting unit and multiplexers connected to it, wherein fixed values can be applied to the inputs of the multiplexers and the sequence providing unit is designed to provide the derived sequences of the third group at outputs of the multiplexers.
- Such a structure of logic elements also allows a very efficient and simple implementation of the sequence providing unit with very low energy consumption.
- the number n of the at least two derived sequences of the third group corresponds to the number of first PN sequences in the first group, and this in turn corresponds to the number of second PN sequences in the second group.
- the number of derived sequences of the third group is only half as high as the number of total PN-sequences that can be used on the transmitting side. This advantageously enables a simpler implementation, in particular of the correlation unit, but also of the sequence providing unit and of the evaluation unit.
- the correlation unit includes n multiplier units and n downstream integration units, wherein the respective multiplier units associated with the sequence providing unit and the differential demodulator (or equalizer) calculate n product signals by (individually delayed or undelayed and in-chip) signal values of the demodulated (and possibly equalized) signal are multiplied by (possibly also higher-level [more than two-level] chip values of one of the derived sequences of the third group, and subsequently each integration unit provides a correlation result per symbol period by a number of signal values of the corresponding product signal
- the correlation unit is very simple, requires very little operating energy and enables a high performance in the detection error rate, and if the derived sequences of the third group have two-stage chip values (eg +/- 1), the multiplier units can be advantageous
- a chip value of each derived sequence remains unconsidered in the correlation calculation, so that in spite of the differential demodulation, two consecutive data symbols may advantageously remain unaffected depending on each other.
- the evaluation unit evaluates the n correlation results per symbol period in parallel by transmitting them substantially simultaneously, i. in a chip period or in a few chip periods of each symbol period. In this way, the results of the evaluation of the correlation results are fully available as early as possible, so that advantageously decisions can be made as soon as possible on the most likely transmitted data symbol values.
- the evaluation unit includes a parallel maximum value determination unit and a downstream allocation unit, the parallel maximum value determination unit connected to the integration units of the correlation unit comparing the n correlation results per symbol period substantially simultaneously, ie in one chip period or in a few chip periods of each symbol period, and as a result the signed one value Nisses and a sequence index with values between 0 and n-1 determines the amount of maximum Korrelationsergeb- indicating which is allocated to this signed value of the derived sequences of the third group, and wherein the assignment unit of the sequence index and the sign of the signed value of the maximum magnitude correlation result determines a value of one of the data symbols.
- an evaluation unit can make decisions about provide the data symbol values as early as possible, be implemented easily and energy efficiently.
- the correlation unit has delay elements arranged such that, per symbol period, two first of the n correlation results in the same chip period and n-2 second correlation results in subsequent chip periods to be provided.
- the evaluation unit serially evaluates the n correlation results per symbol period by evaluating the first correlation results in a first chip period and each of the second correlation results in the subsequent chip periods.
- the delay elements are in this case arranged in the signal path in front of the multiplier units, since in this way the delay of the correlation results with the least possible (hardware) is achieved on wall.
- the evaluation unit includes a serial maximum value determination unit and a downstream allocation unit.
- the serial maximum value determination unit in the first chip period compares the first correlation results with each other in absolute value and determines as the result the signed value of the first correlation result having the largest amount and a sequence index indicating which of the derived sequences of the third group associate with this signed value is.
- the serial maximum value determination unit compares one of the second correlation results in absolute terms with the result determined in the respective preceding chip period and, as a result, determines the signed value having the greater amount and a sequence index which indicates which of the derived sequences attributable to this signed value. This step is carried out until all second correlation results have been taken into account, and thus the signed value of the maximum correlation result and a sequence index (with values between 0 and n-1) indicating which of the n derived sequences is to be assigned to this signed value.
- the allocation unit finally determines a value of one of the data symbols from the sequence index and the sign of the signed value of the magnitude-maximum correlation result.
- This evaluation unit is advantageously very simple in construction, requires extremely little energy during operation and is characterized by a high performance in the detection error rate.
- the serial maximum value determining unit includes a first multiplexer, a second multiplexer and a logical unit.
- the first multiplexer in this case has a first input which is connected to a first integration unit of the correlation unit, and a second input which is connected to the first output of the logic unit.
- the second multiplexer has n-1 inputs connected to the n-1 remaining (“second") integrators
- the logic unit has two inputs connected to the two outputs of the two multiplexers and two outputs
- the first multiplexer is driven in such a way that in the first chip period it passes the first correlation result applied to its first input and in the subsequent chip periods the value applied to its second input to its output, while the second multiplexer is driven in such a way the first chip period passes the first correlation result applied to one of its inputs and, in the subsequent chip periods, one of the second correlation results applied to its other inputs to its output, the logical unit compares the two values passed by the two multiplexers by a given value and determines the latter signed value of the greater value and the sequence index of the derived sequence to be assigned to this signed value.
- This serial maximum value determination unit is advantageously constructed very simply.
- the operating energy is consumed more evenly over time or lower peak currents occur compared to the parallel implementation. This is advantageous both in terms of the interference radiation and in terms of the battery life.
- the allocation unit preferably determines that value of one of the data symbols to which the first pi1 sequence of the first group is assigned. the derived sequence is associated with this sequence index (value) if the signed-value of the magnitude-maximum correlation result is positive, and otherwise the value of one of the data symbols to which the second PN sequence of the second group is assigned, that to the derived sequence associated with this sequence index (value) inverse sequence.
- Such an allocation unit is advantageously very simple and requires extremely little energy during operation.
- the derived chips (ie the chips of a derived sequence) having a first positive index (ie all chips except the first one) each have a value which consists of an XOR combination of the PN chip (ie the chip the first PN sequence to which the derived sequence is assigned) with this first positive index with the index-wise (and therefore temporally) respective preceding PN chip can be derived.
- the index-wise (and time-wise) first derived chip has a value derivable from an XOR of the index-wise first PN (zero-zero) PN chip with the index-wise last PN chip.
- FIG. 1 shows a "wireless personal area network” (WPAN) according to the IEEE 802.15.4 standard with transmission receiving devices (TRX) according to the invention
- WPAN wireless personal area network
- TRX transmission receiving devices
- FIG. 3 shows a first embodiment of a detection unit according to the invention
- FIG. 4 shows a preferred second embodiment of a detection unit according to the invention.
- WPAN Wireless Personal Area Network
- TRX transceivers
- the transmitting receiving device 11 is a so-called full-function device which performs the function of the WPAN coordinator, while the transmitting receiving devices 12, 13 are so-called sub-function devices which are assigned to the full-function device 11 and only with In addition to the star-shaped network topology shown in FIG.
- the transmitting receiving devices 11-13 each comprise an antenna 14, a transmitting unit (transmitte TX) 15 connected to the antenna, a receiving unit (receiver, RX) 16 connected to the antenna and a control unit (control unit) connected to the transmitting and receiving units.
- CTRL control unit
- the transceiver devices 11-13 each include a not shown in Figure 1 power supply unit in the form of a battery, etc. for powering the units 15-17, and possibly other components such as sensors, interfaces etc .. in the following it is assumed that the data transmission in the ISM band (industrial, scientific, medical) is done by 2.4 CHz.
- the successive Pl1 sequences are then QPSK modulated (quaternary phase shift keying) with half sine pulse shaping.
- the receiving unit 16 of each transmitting receiving device converts a radio signal received from its antenna 14 (and generated by the transmitting unit of another transmitting / receiving device according to the IEEE standard 802.15.4) into the transmitted data as error-free as possible by transmitting the radio signal among other things demodulated and the data subsequently detected (decided).
- the transmitting unit 15 and the receiving unit 16 of a transmitting / receiving device are in this case part of an integrated circuit (IC) (not shown in FIG. 1), e.g. an ASIC (application specific integrated circuit), while the control unit 17 is implemented by a (also not shown) microcontroller.
- IC integrated circuit
- the transmitting receiving device may also comprise only one IC (embodied, for example, as ASIC), which performs the functions of the transmitting unit 15, the receiving unit 16 and the control unit 17.
- FIG. 2 shows a block diagram of an incoherent receiving unit (RX) 16 which comprises the following series-connected functional blocks: an inner receiver (iREC) 21, a differential demodulator (DEMOD) 22 and a detection unit 28 according to the invention, comprising a correlation unit (COR) 23 and a downstream evaluation unit (EVAL) 24 and one with the correlation unit 23rd connected sequence providing unit (SEQ) 25 has.
- the receiving unit 16 optionally has an equalizer (EQ) 26 between the demodulator 22 and the detection unit 28.
- EQ equalizer
- Each complex sample comprises a real part (in-phase component I) and an imaginary part (quadrature component Q).
- Complex-valued signals such as the baseband signal b are shown in the figures by arrows with double lines.
- the inner receiver 21 further includes a synchronization unit (SYNC) 27 which performs symbol and chip clock synchronization.
- SYNC synchronization unit
- the baseband signal b is then converted by the differential demodulator 22 into a demodulated signal having real-valued signal values in the chip clock fc.
- the differential demodulator 22 generates a demodulated signal whose signal values have so-called soft information values (higher-level, e.g., 4-bit wide signal values) instead of so-called hard bits (i.e., two-level binary values).
- the demodulated signal is then optionally equalized.
- the equalizer 26 may comprise a filter, e.g. have a high-pass filter.
- the differentially demodulated (and possibly equalized) signal is denoted by s.
- the data symbols d ⁇ , d1, d2,... Contained in the differentially demodulated (and optionally equalized) signal s are detected by the detection unit 28 according to the invention, ie decided.
- the signal s present in the chip clock fC (with, for example, four bit wide signal values) is first correlated in the correlation unit (COR) 23 with so-called derived sequences FO, F1,..., F7 provided by the sequence providing unit 25.
- the SendeVEmpfangsvoriquesen 11-13 of Figure 1 characterized by a very simple feasibility, a very low energy consumption and high performance from (bit error rate, etc. depending on interference such as noise and / or channel distortions).
- the following describes how the derived sequences FO, F1, .... F7 provided by the sequence providing unit 25 are arranged.
- the following table shows both the PN sequences P0, P1,... To be used according to IEEE 802.15.4 and the derived sequences FO, F1,... Associated with the PN sequences according to the invention.
- each PN sequence here comprises 32 so-called chips, each of which can assume a value of logical zero (0) or one (1).
- the first ten chips of the PN sequence P5 assume the values 001 1 01 0 1 00.
- the parameters P5c ⁇ (first chip (c ⁇ ) of P5), P5d (second chip (CD), .... P5c30, P5C31 (last chip (c3D) are introduced to simplify the description.
- the former are referred to as PN chips, dividing the total of 16 PN sequences PO, P1 , ..., P15 of the sequence supply into a first group PC1 of the eight "first" PN sequences PO, P1, ' ..., P7 and a second group PG2 of the eight "second" PN sequences P8, P9,. ., P15, it can also be seen from the table that the first PN sequences PO, P1,..., P7 only differ from each other by a cyclic shift of their chip values differ.
- the bit pattern ⁇ 1 1 0 1 1 0 ⁇ occurring at the beginning of the PN sequence PO is in the PN sequence P1 from the PN chip P1C4, in the PN
- each PN sequence is assigned a non-identical derivative sequence adapted to the differential demodulation, the PN sequence PO, for example, the derived sequence FO listed in the table below PO, the PN sequence P1, the derived sequence F1, etc
- the chips of the derived sequences can assume the anti-podal values +1 and -1, whereby in the table only the sign of these values is entered for reasons of clarity.
- the values of the derived chips are as follows from the values of the PN chips.
- F0c2 which according to the table is + 1
- the value of the PN chip P0c2 0
- the logical XOR operation in this case yields a value of logic 1 to which the antipodal value +1 entered in the table for F0c2 is assigned.
- the derived sequences FO, F1,..., F7 of the third group FG1 differ from each other only by a cyclical shift of their chip values, such as that occurring at the beginning of the derived sequence FO Bit pattern ⁇ + + + - - - ⁇ in the derived sequence F1 from the derived chip F1C4, in the derived sequence F2 from F2c8, in F3 from F3C12, in F4 from F4d6, ..., and finally in F7 from F7c28 - cyclical expansion - to recognize. Also, the derived sequences F8, F9, ..., F15 of the fourth group FG2 differ only by a cyclic shift of their chip values from each other.
- each derived sequence of the third group FG1 there exists a derivative sequence of the fourth group FG2 which differs only by an inversion of all its chip values. For example, if one compares the derived sequence FO from FG1 with F8 from FG2 in the table, one finds that all chip values are inverted. As for the sequence pairs F1 / F9, F2 / F10 etc., it should be noted that all the derived sequences of the third group FC1 are contained in inverted form in the fourth group FG2:
- the corresponding pairs F0 / F8, F1 / F9, etc. differ from derived sequences by inversion of all their chip values.
- FIG. 3 shows a block diagram of a first exemplary embodiment of the detection unit according to the invention, in which the correlation results are provided and evaluated in parallel, ie substantially simultaneously.
- the detection unit 30 has a correlation unit (COR) 31 connected to the differential demodulator 22 or the equalizer 26 from FIG. 2 and a downstream evaluation unit (EVAL) 32 as well as a sequence providing unit (SEQ) 33 connected to the correlation unit 31.
- the sequence providing unit 33 has a storage means 34 connected to the correlation unit 31, the size of which is so dimensioned that exactly one of the derived sequences can be stored, in the case of the derived sequences FO, F1, F2, .., explained with reference to the table above.
- the storage means 34 is suitable for storing 32 chip values.
- the storage means is designed as a feedback shift register 34 with a total of 32 register cells 34-0, 34-1,..., 34-31 for storing one chip value each of a derived sequence.
- the storage means is designed as a feedback shift register 34 with a total of 32 register cells 34-0, 34-1,..., 34-31 for storing one chip value each of a derived sequence.
- a state of the shift register 34 is shown by way of example, in which the register cells 34-0, 34-1,..., 34-31, from left to right, display the chip values "+ + + - - - -
- the other derived sequences F1, F2, ..., F7 of the third group FC1 differ from the derived sequence FO only by a cyclic shift.
- the derived sequences F1, F2,..., F7 can therefore either also be at the output of the first register cell 34-0 (but later starting later than FO) or else at outputs of other register cells (with or without time offset with respect to FO). be tapped.
- FIG. 3 shows at which register cells the other derived sequences F1, F2,..., F7 of the third group FG1 are tapped if they are used simultaneously, i. in the same time interval as the derived sequence FO should be provided. According to the table explained above, e.g.
- the feedback shift register 34 of Figure 3 provides the derived sequences FO and F7 at the same time when F7 at the output of the fifth register cell 34-4 and FO is tapped at the output of the first register cell 34-0 as previously discussed.
- Analogous considerations show that the further derived sequences F1, F2,..., F6 of the third group FG1 at the outputs of the register cells 34-28, 34-24, 34-20, 34-16, 34-12 and 34- 8 are provided at the same time, as shown in Figure 3.
- the correlation unit 31 has eight multiplier units 35-0, 35-1,..., 35-7, each with two inputs, and also eight integration units 36-0, 36-1,..., 36-7 connected downstream of a respective multiplication unit ,
- the second inputs of the multiplier units 35-0, 35-1, ..., 35-7 are connected to the outputs of the register cells 34-0, 34-28, 34-24, 34-20, 34-16, 34-12, 34-8 and 34-4 of the feedback shift register 34 are connected so that they simultaneously (parallel) the derived sequences FO, F1, ... or F7 of the third group FG1 are supplied.
- the downstream integration unit 36-i adds, per Svmbolperiode 31 of these 32 signal values of the corresponding product signal ti, thus providing a correlation result rsFi per symbol period.
- the respective first signal value of ti - and thus the first chip value Fico of the corresponding derived sequence Fi - is not taken into account in each symbol period.
- the integration unit 36-i is reset, so that the subsequent integration with the value zero starts.
- the signal processing takes place in the individual branches of the correlation unit 31 without a time offset: all the jth chips of the derived sequences are multiplied in the same chip period by a signal value of s. After integration, therefore, the correlation results are also simultaneous, i. parallel, ready.
- the deduced sequences may assume antipodal values (+ 1 and -1).
- the multiplication of the (possibly equalized) demodulated signal s with the antipodal chip values of the derived sequences thus causes a sign reversal of the values of the demodulated signal s in this case. Therefore, the multiplying units 35-0, 35-1, ..., 35-7 are advantageously realized as sign reversers.
- the evaluation unit 32 has a parallel maximum value determination unit (MAX) 37 connected to the integration units 36-0, 36-1,..., 36-7 and a downstream allocation unit (MAP) 38.
- MAX parallel maximum value determination unit
- MAP downstream allocation unit
- the parallel maximum value determination unit 37 compares eight correlation results rsFO, rsFi,..., RsF7 per symbol period in parallel (ie essentially at the same time, eg in the same chip period) and determines the (signed) value of the magnitude-maximum correlation result rsFmax and a sequence index k with integer values between 0 and 7, which indicates which of the derived sequences FO, F1, ..., F7 of the third group FC1 is to be assigned to this signed value.
- the correlation result rsF5 is the maximum amount among all the eight correlation results
- the allocation unit 38 takes into account the fact that in the correlation unit only with the eight derived sequences FO, F1, ..., F7 of the third group FC1, but not with the eight derived sequences F8, F9, ..., F15 the fourth group FG2 was correlated. Due to the above-described property of the derived sequences according to which for each derived sequence FO, F1, ..., F7 of the third group FG1 there exists a derived sequence F8, F9,..., F15 of the fourth group FG2, which can only be understood by an inversion of all of their chip distinguishes the correlation result, eg for F13, only in sign from that for F5. For this reason, the allocation unit 38 evaluates the sign of rsFmax.
- the embodiment of a detection unit according to the invention described with reference to FIG. 3 requires only a minimum memory of 32 bits, only eight instead of 16 multiplication units, which are advantageously designed as sign reversers, only 8 instead of 16 integration units, a parallel maximum value determination unit and a simple allocation unit.
- the detection unit is therefore easy to implement and is characterized by a very low energy consumption. A further simplification will be described below with reference to FIG.
- FIG. 4 shows a block diagram of a preferred second exemplary embodiment of the detection unit according to the invention, in which almost all correlation results are provided and evaluated serially, ie in chronological succession.
- the detection unit 40 has a correlation unit (COR) 41 and connected to the differential demodulator 22 or the equalizer 26 from FIG. 2 a downstream evaluation unit (EVAL) 42 as well as a sequence providing unit (SEQ) 43 connected to the correlation unit 41.
- COR correlation unit
- EVAL downstream evaluation unit
- SEQ sequence providing unit
- the correlation unit 41 provides, per symbol period, the correlation results rsFO, rsFi of the first two branches in the same chip period, while the remaining correlation results rsF2, ..., rsF7 are respectively provided in one of the subsequent chip periods. In this way, an evaluation of rsFmax with lower costs is possible in the evaluation unit 42.
- the sequence providing unit 43 essentially corresponds to the sequence providing unit 33 described with reference to FIG. 3, in this respect reference is made to the above description. However, the sequence providing unit 43 provides the deduced sequence F2 starting a chip period later than the derived sequences FO and F1 by substituting F2 at the output of the register cell 34-23 (FIG. 4) instead of 34-24 (FIG. a chip period later, is tapped.
- the derived sequence F3 is provided with a chip period after F2 or two chip periods after FO / F1, for which reason it is tapped at the output of the register cell 34-18 (FIG. 4) instead of 34-20 (FIG. 3).
- the outputs of the register cells 34-13, 34-8, 34-3 and 34-30 result analogously for the further derived sequences F4,..., F7.
- eight outputs of the delivery unit 43 are provided, which are connected to the outputs of the register cells 34-0, 34-28, 34-23, 34-18, 34-13, 34-8, 34-3 and 34, respectively -30 are connected to provide the derived sequences FO and F1 at the same time and the derived sequences F2, F3, ..., F7 each offset by one chip period.
- sequence providing unit 43 is just as easy and energy-saving to implement as the sequence providing unit 33 described with reference to FIG. 3. In this respect, reference is made to the above description.
- the correlation unit 41 also essentially corresponds to the correlation unit 31 described with reference to FIG. 3. In this respect, reference is made to the above description. However, the correlation unit 41 additionally has six delay elements 44-2, 44-3,..., 44-7. In this case, the delay elements are arranged in series as a so-called "tapped delay line", to which the (possibly equalized) demodulated signal s is supplied. Each delay element in this case provides the signal values of the signal present at its input delayed by one chip period TC at its output such that at the output of the first delay element 44-2, the demodulated signal delayed by one chip period TC s2, at the output of the second delay element 44-3, the demodulated by two chip periods demodulated signal s3, ...
- the sixth delay element 44-7 is delayed by six Chipperioden demodulated signal s7.
- 35-7 are respectively connected to the output of the identically indexed delay element 44-2, 44-3, ..., 44-7 and so on with one, two, ..., and six, respectively
- the second inputs of the multiplier units 35-0, 35-1, ..., 35-7 are connected to the outputs of the register cells 34-0, 34 -28, 34-23, 34-18, 34-13, 34-8, 34-3, and 34-30, respectively, of the feedback shift register 34, so that the derived sequences FO and F1 coincide with them, and the derived sequences F2 , F3, ..., F7 relative to F0 / F1 by one, two, ... or six Chipperioden delayed supplied.
- time delays have an analogous effect on the outputs of the corresponding multiplier and integrator units, so that the correlation results rsFO and rsF1 are provided in the same chip period per svmblope period, while the correlation results rsF2, rsF3,..., RsF7 are provided with a time delay of one, two, ..., or six Chipperioden be provided.
- delay elements 44-2, 44-3,..., 44-7 shown in FIG. 4 delay elements can also be arranged between the multiplier units and the integration units or else (in the signal flow direction) downstream of the integration units. However, in these cases in the branch with index 2 a delay by one chip period, in the second by index 3 a delay by two chip periods, etc. is required. If the delay elements are arranged after the integration units, then signal values greater than the bit width are to be delayed have demodulated signal s.
- the multiplier units shown in FIG. 4 are also advantageously implemented as sign reversers.
- the integration units shown in FIG. 4 also advantageously add 31 of the 32 signal values of the respective product signal ti per symbol period.
- the evaluation unit 42 has a serial maximum value determination unit 49 connected to the integration units 36-0, 36-1,..., 36-7 and a downstream allocation unit (MAP) 48.
- MAP downstream allocation unit
- the serial maximum value determination unit 49 compares eight correlation results rsFO, rsFi,..., RsF7 per symbol period serially (ie in successive chip periods) and determines the (signed) value of the magnitude-maximum correlation result rsFmax and a sequence index k with integer values between 0 and 7, indicating which of the derived sequences FO, F1, ..., F7 of the third group Fd is to be assigned to this signed value.
- the serial maximum value determination unit 49 has a first multiplexer (MUX) 45 whose first input is connected to the integration unit 36-0, a second multiplexer (MUX) 46 connected on the input side to the integration units 36-1,..., 36-7, and a on the input side to the outputs of the two multiplexers 45, 46 connected logic unit (LOG) 47 with two outputs, wherein the first output of the logic unit 47 is connected to the second input of the first multiplexer 45.
- MUX first multiplexer
- MUX second multiplexer
- LOG logic unit
- the logic unit 47 is designed such that it compares the magnitude of the input values provided by the two multiplexers 45, 46 and determines the signed value of the larger input value and provides it at the first output, as well as the sequence index k of the derived sequence to be assigned to this signed value determined and provided at the second output, advantageously, the logical unit 47 is formed as a state machine (state machine).
- the first multiplexer 45 is controlled, for example, by a control unit in such a way that in each symbol period in a certain ("first") chip period the correlation result rsFO applied to its first input and in the subsequent chip periods the value applied to its second input, that of the first output
- the second multiplexer 46 is also controlled, for example, by the said control unit in such a way that in the said "first" chip period it has the correlation result rsFi applied to its first input and in the subsequent chip period that at its second input present correlation result rsF2 etc. at its output.
- the allocation unit 48 corresponds to the allocation unit 38 described with reference to FIG. 3. In this respect, reference is made to the above description.
- the embodiment of a detection unit according to the invention described with reference to FIG. 4 requires only a minimum memory of 32 bits, only 8 instead of 16 multiplication units, which are advantageously designed as sign reversers, only 8 instead of 16 integration units, a very easy to implement serial maximum value determination unit and also very simple allocation unit.
- the detection unit is therefore very easy to implement and is characterized by an extremely low energy requirement.
- FIG. 5 shows an alternative embodiment of the sequence providing unit.
- the sequence providing unit 53 has a total of eight multiplexers (MUX) 52-0, 52-1,..., 52-7, the control input of which is respectively connected to the counting unit (CNO 51), while at the outputs of the multiplexers the decoupling unit is connected.
- MUX multiplexers
- the 32 inputs per multiplexer are at fixed values (such as the supply voltage and ground) representing the respective derived sequence.
- Analogous to the "current" content of the register cells 34-0, ..., 34-31 of the shift register 34 of FIGS. 3 and 4, the input values of the multiplexers 52-0, 52-1,..., 52-7 in FIG 5 is represented by plus and minus symbols, where the sequence "+ +" shown at the inputs of the multiplexer 52-0 in FIG.
- the counting unit 51 is designed to count from zero to 31 in the chip clock fC and then to start again from 0. It therefore provides a running chip index (0 ... 31) at its output per symbol period.
- the multiplexers In the first chip period (with index zero), therefore, the multiplexers each pass the value applied to their first (uppermost) input to their output, so that in the first chip period the first chip values of the derived sequences are provided at the same time (FOcO, FIcO,. .., F7c ⁇ ).
- the multiplexers in each case synchronously switch the values applied to their second, third, etc. inputs until all the derived sequences are provided in parallel after a total of 32 chip periods.
- the sequence providing unit 53 from FIG. 5 can be used directly instead of the sequence providing unit 33 in FIG.
- the sequence providing unit 53 of FIG. 5 can also be used instead of the sequence providing unit 43 in FIG.
- the input values of the multiplexers 52-2, 52-3,..., 52-7 are to be cyclically shifted, ie the inputs of the mentioned multiplexers are to be shifted cyclically shifted.
- the input values of the multiplexer 52-2 are cyclically shifted in FIG. 5 by an input position, those of multiplexer 52-3 down two input positions, etc. and those of multiplexer 52-7 down six input positions.
- the derived sequences are provided serially, analogously to the sequence providing unit 43 of FIG. 4, ie the derived sequences FO and F1 in the same chip period, F2 starting a chip period later, F3 starting a further chip period later, etc.
- input values of the multiplexers 52-2, 52-3, ..., 52-7 may also be delayed correspondingly to the output values of the counting unit 51 fed to these multiplexers.
- the detection unit according to the invention described above with reference to FIGS. 2 to 5 and therefore also transmission receiving apparatuses which have such a detection unit are characterized by a very simple realizability, an extremely low energy requirement as well as a high performance (bit error rate or the like as a function of disturbing influences such as Noise and / or channel distortion).
- the digital parts of the receiving units require - without synchronization unit - a hardware cost on the order of a few thousand Catteräquivalenten (N AN D-gate with two inputs), in the data transmission mode, these digital parts of the receiving units have a power requirement of the order of a few milliwatts (mW).
- P5c ⁇ , P5d, ... chips of the PN sequence P5 PC1 first group of first PN sequences PO,..., P7
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Abstract
Description
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Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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DE102005026093A DE102005026093B4 (de) | 2005-06-07 | 2005-06-07 | Detektionseinheit |
PCT/EP2006/005174 WO2006131243A1 (de) | 2005-06-07 | 2006-05-31 | Differentielle detektionseinheit für den zigbee 802.15.4 standard |
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EP1889434A1 true EP1889434A1 (de) | 2008-02-20 |
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EP06754002A Withdrawn EP1889434A1 (de) | 2005-06-07 | 2006-05-31 | Differentielle detektionseinheit für den zigbee 802.15.4 standard |
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EP (1) | EP1889434A1 (de) |
CN (1) | CN101243665B (de) |
DE (1) | DE102005026093B4 (de) |
WO (1) | WO2006131243A1 (de) |
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US7983235B2 (en) * | 2007-11-05 | 2011-07-19 | Freescale Semiconductor, Inc. | High speed overlay mode for burst data and real time streaming (audio) applications |
US8605568B2 (en) | 2009-04-14 | 2013-12-10 | Texas Instruments Incorporated | PHY layer options for body area network (BAN) devices |
WO2011025418A1 (en) * | 2009-08-25 | 2011-03-03 | Telefonaktiebolaget Lm Ericsson (Publ). | Admission control in a wireless communication system |
DE102010050118B4 (de) | 2010-11-03 | 2018-03-22 | Atmel Corp. | Sende-Empfangs-Vorrichtung und Verfahren zur Übertragung von Daten zwischen Knoten eines Funknetzes |
EP2781031B1 (de) * | 2011-11-16 | 2019-05-15 | NXP USA, Inc. | Direktsequenzvorrichtung und verfahren zum empfangen eines spreitzspektrumsignals |
DE102012221798A1 (de) * | 2012-11-28 | 2014-05-28 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Vorrichtung und Verfahren zur Sequenzerkennung für Frequenzumtastung |
CN106341158B (zh) * | 2016-10-13 | 2019-03-26 | 惠州Tcl移动通信有限公司 | 一种移动终端根据扩频和解频安全接收信号的方法及系统 |
CN111224649B (zh) * | 2020-01-17 | 2021-06-18 | 深圳市紫光同创电子有限公司 | 高速接口的固定延时电路 |
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US7020111B2 (en) * | 1996-06-27 | 2006-03-28 | Interdigital Technology Corporation | System for using rapid acquisition spreading codes for spread-spectrum communications |
JP3105786B2 (ja) * | 1996-06-13 | 2000-11-06 | 松下電器産業株式会社 | 移動体通信受信機 |
US7545854B1 (en) * | 1998-09-01 | 2009-06-09 | Sirf Technology, Inc. | Doppler corrected spread spectrum matched filter |
FI112831B (fi) * | 1999-04-28 | 2004-01-15 | Nokia Corp | Menetelmä kanavaestimaatin muodostamiseksi ja vastaanotin |
US6850557B1 (en) * | 2000-04-18 | 2005-02-01 | Sirf Technology, Inc. | Signal detector and method employing a coherent accumulation system to correlate non-uniform and disjoint sample segments |
US7366227B2 (en) * | 2003-11-13 | 2008-04-29 | Hyperband Communications, Inc. | Chip-to-symbol receiver despreader architectures and methods for despreading spread spectrum signals |
US7424047B2 (en) * | 2003-11-13 | 2008-09-09 | Uniband Electronic Corp. | Receiver based method for de-spreading of spread spectrum signal |
JP3806425B2 (ja) * | 2003-12-01 | 2006-08-09 | マゼランシステムズジャパン株式会社 | 衛星測位方法及び衛星測位システム |
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2005
- 2005-06-07 DE DE102005026093A patent/DE102005026093B4/de active Active
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2006
- 2006-05-31 CN CN2006800293646A patent/CN101243665B/zh active Active
- 2006-05-31 EP EP06754002A patent/EP1889434A1/de not_active Withdrawn
- 2006-05-31 US US11/917,150 patent/US8107513B2/en active Active
- 2006-05-31 WO PCT/EP2006/005174 patent/WO2006131243A1/de active Application Filing
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2011
- 2011-12-08 US US13/314,999 patent/US8477829B2/en active Active
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CN101243665A (zh) | 2008-08-13 |
US8477829B2 (en) | 2013-07-02 |
DE102005026093A1 (de) | 2006-12-21 |
US20120087307A1 (en) | 2012-04-12 |
CN101243665B (zh) | 2011-06-22 |
US20100254304A1 (en) | 2010-10-07 |
WO2006131243A8 (de) | 2008-04-03 |
DE102005026093B4 (de) | 2007-07-05 |
US8107513B2 (en) | 2012-01-31 |
WO2006131243A1 (de) | 2006-12-14 |
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