EP1590832B1 - Cellule de memoire, systeme de cellules de memoire et procede de fabrication d'une cellule de memoire - Google Patents

Cellule de memoire, systeme de cellules de memoire et procede de fabrication d'une cellule de memoire Download PDF

Info

Publication number
EP1590832B1
EP1590832B1 EP04707864A EP04707864A EP1590832B1 EP 1590832 B1 EP1590832 B1 EP 1590832B1 EP 04707864 A EP04707864 A EP 04707864A EP 04707864 A EP04707864 A EP 04707864A EP 1590832 B1 EP1590832 B1 EP 1590832B1
Authority
EP
European Patent Office
Prior art keywords
region
substrate
trench
storage cell
charge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
EP04707864A
Other languages
German (de)
English (en)
Other versions
EP1590832A2 (fr
Inventor
Franz Schuler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1590832A2 publication Critical patent/EP1590832A2/fr
Application granted granted Critical
Publication of EP1590832B1 publication Critical patent/EP1590832B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7885—Hot carrier injection from the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the invention relates to a memory cell, a memory cell arrangement and a method for producing a memory cell.
  • CHE Choannel Hot Electron
  • CHE Choannel Hot Electron
  • FIG.1 A floating gate memory cell 100 known in the art is described.
  • the floating gate memory cell 100 is integrated in a p-doped silicon substrate 101.
  • an n-type well 102 is formed in the p-type silicon substrate 101.
  • a p-doped well 103 is formed in the n-doped well 102.
  • a first source / drain region 104 is formed as an n + -doped region.
  • a second source / drain region 105 is formed in a second surface region of the p-doped well 103 as an n + -doped region.
  • a channel region 106 is formed in the surface area of the p-type well 103 between the source / drain regions 104, 105.
  • a floating gate region 108 arranged above the channel region 106 is electrically insulated from the channel region 106, and a control gate 109, which is arranged above the floating gate region 108, is separated from the floating gate. Section 108 electrically isolated.
  • the floating gate memory cell 100 of adjacent memory cells (not shown in FIG Fig.1 ) is electrically decoupled from a memory cell array.
  • a predeterminable electrical potential can be applied to the source / drain regions 104, 105 and to the control gate 109 by means of contacting elements 111.
  • a pn junction 112 is formed.
  • the in Fig.1 shown floating gate memory cell 100 has the disadvantage that the entire pn junction 112 must be biased over a large lateral width. This leads to a high energy consumption during programming, erasing and reading of the memory cell 100, which is disadvantageous in particular for low-power applications.
  • test arrangement 200 which is known for investigations of the reliability of components.
  • the test arrangement 200 serves to improve the quality or reliability of a gate-insulating Check layer in a previously formed field effect transistor.
  • the test arrangement 200 is integrated on and in a p-doped silicon substrate 201.
  • a field-effect transistor 202 is integrated in the test arrangement 200.
  • This includes a first source / drain region 203 formed in a first surface region of the p-doped silicon substrate 201 and a second source / drain region 204 formed in a second surface region of the p-doped silicon substrate 201.
  • Both source / Drain regions 203, 204 are n + doped regions. Between the two source / drain regions 203, 204, a channel region 208 is formed.
  • a gate region 206 is formed, which is electrically separated from the channel region 208 by means of a gate-insulating layer, which is part of an electrically insulating region 205. Furthermore, contacting elements 207 are provided for applying defined electrical potentials to the source / drain regions 203, 204 or to the gate region 206. On the side of the field-effect transistor 202, an additional n + -doped region 209 is provided in another surface region of the silicon substrate 201, which region can be electrically driven by means of another contacting element 210.
  • Fig.2 can be indicated schematically by means of applying 0V or a positive electrical potential to the source / drain regions 203, 204 and a positive electric potential to the gate region 206 which is stronger in comparison with this positive potential and a negative electrical potential to the n + -doped region 209 electrical charge carriers, namely electrons, from the n + -doped region 209 via the p-doped silicon substrate 201 and the channel region 208 through the gate insulating layer until possibly injected into the gate region 206.
  • the invention is based in particular on the problem of providing a memory cell and a memory cell arrangement in which programming with reduced energy requirement is made possible.
  • the memory cell according to the invention contains a substrate which contains charge carriers of a first conductivity type. Furthermore, the memory cell includes a first source / drain region in a first surface region of the substrate and a second source / drain region in a second surface region of the substrate. A channel region is formed in a surface region of the substrate between the first and second source / drain regions. Further, a charge storage region is formed over the channel region and a control gate is formed over the charge storage region, which control gate is electrically isolated from the charge storage region.
  • a trench structure is formed, comprising charge carrier material having carriers of a second conductivity type and an isolation region between the substrate and at least a portion of the charge generating material.
  • the first conductivity type is different from the second conductivity type, so that between the substrate and the charge-carrying material of the trench structure, a diode junction, when using a semiconductor material as a charge-carrier material depending on the doping a pn junction or np junction, when used For example, a metal such as tungsten, a Schottky diode is formed.
  • the memory cell is set up in such a way that, by applying predeterminable electrical potentials to the memory cell, electrical charge carriers from the charge carrier-supplying material of the trench structure can be introduced into the charge storage region.
  • the memory cell arrangement according to the invention contains a plurality of memory cells integrated in the substrate with the features mentioned above.
  • a first source / drain region is formed in a first surface region of a substrate containing charge carriers of a first conductivity type and a second source / drain region in a second surface region of the substrate. Further, a channel region is formed in the surface region of the substrate between the first and second source / drain regions. A charge storage area is formed over the channel area. A control gate is formed over the charge storage region, which is electrically isolated from the charge storage region.
  • a trench structure arranged in the substrate is formed, which has charge-generating material with charge carriers of a second conductivity type and an isolation region between the substrate and at least part of the charge-generating material.
  • the first conductivity type is set differently from the second conductivity type, so that a diode junction is formed between the substrate and the charge carrier-supplying material of the trench structure.
  • the memory cell is furthermore set up in such a way that, by applying predeterminable electrical potentials to the memory cell, electrical charge carriers from the charge carrier-supplying material of the trench structure can be introduced into the charge storage area.
  • a basic idea of the invention is to be seen in that in an integrated memory cell, a trench with increased charge carrier concentration as a supplier of charge carriers for injecting into a charge storage region of the memory cell.
  • the injection can be done by applying presettable electrical potentials to the terminals of the memory cell, in particular to the trench structure and / or the substrate layer and the control gate.
  • the memory cell according to the invention can be implemented in a very space-saving manner since the shallow STI isolation for decoupling adjacent memory cells of a memory cell arrangement can be eroded and can be eroded with an electrically conductive material (for example in n + -doped) Polysilicon) can be filled.
  • the trench structure formed thereby can be used, on the one hand, as insulation for adjacent components in the substrate and, on the other hand, as a charge carrier emitter sufficiently deep in a substrate, without increasing the space requirement.
  • the small space requirement of the memory cell according to the invention represents an important advantage.
  • the memory cell according to the invention is designed for injecting hot electrical charge carriers (electrons or holes) from the trench structure via a substrate into the charged-material storage layer.
  • the emitter for emitting electrical charge carriers is embedded in a trench with at least partial sidewall insulation.
  • the memory cell according to the invention can be realized as an n-channel memory cell or as a p-channel memory cell.
  • the type of conduction (in the case of a p-type or n-type semiconductor material) of charge carriers (dopant atoms in the case of a semiconductor material) is different in the substrate on the one hand and in the trench structure of the trench structure on the other hand. complementary to one another (for example, p-type substrate and n-type or metallic carrier material of the trench structure or n-type substrate and p-type carrier of the trench structure).
  • a diode junction pn-junction or Schottky junction
  • the memory cell according to the invention has the advantage that a uniform charge carrier injection into a charge storage layer is made possible, which leads to a lower degradation of the charge storage layer.
  • a local injection is made possible directly in a neighboring area of a memory cell, since the current paths of the charge carriers in the substrate can be predetermined by applying suitable potentials to the terminals of the memory cell.
  • the local injection of charge carriers in a memory cell leads to a low energy requirement and the ability to address individual cells.
  • the emitter of the electrical charge carriers is embedded in a trench, resulting in a small footprint.
  • the trench structure preferably extends deeper into the substrate than the first and second source / drain regions. This ensures that electrical charge carriers can be introduced very homogeneously into the charge storage layer. As a result, the service life of the memory cell, in particular the charge storage layer, is increased.
  • the vertical depth of the trench structure must not exceed the depth of the well region in the substrate.
  • the trench structure preferably extends in a substantially vertical direction to the surface of the substrate.
  • the trench structure may be formed laterally of at least one of the source / drain regions and outside the channel region.
  • the memory cell according to the invention may comprise two (or more) trench structures in the substrate, one of which is arranged laterally of the first source / drain region and outside the channel region and the other laterally of the second source / drain region and outside Channel area is arranged.
  • This configuration is symmetrical, giving a particularly homogeneous. Injecting of electric charge carriers in the charge storage layer is made possible.
  • the memory cell can be electrically decoupled from both sides of possibly arranged in adjacent areas of the substrate components to avoid unwanted electrical interaction between such components and the memory cell.
  • other integrations are also conceivable (e.g., NAND architectures)
  • the trench structure can have an electrically insulating jacket region on at least part of the side wall of the trench and an electrically conductive core region filled in the trench such that electrical charge carriers can emerge from the trench structure only from those regions into which the core region of a jacket is free with the cladding region, or of such regions in which the cladding region has a sufficiently small thickness to allow a tunneling current of charge carriers from the charge carrier material through the cladding region into the substrate.
  • the trench structure may be fabricated by first forming a trench in the substrate. Thereafter, e.g. formed in a deposition method or by thermal oxidation, an insulating layer on the side wall of the trench and the bottom thereof. Thereafter, for example, with a unisotropic etching step (e.g., by reactive ion etching (RIE)), the insulating layer is at least partially removed from the bottom of the trench and / or its sidewall at the bottom. Subsequently, the trench is filled with the carrier-emitting material, whereby a diode junction is formed in the contact region. Then, starting from the bottom region of the trench, charge carriers can be introduced from the trench structure into the substrate. For example, in-situ doped polysilicon material or a metal is filled into the cavity introduced in the trench, thereby forming the trench structure.
  • RIE reactive ion etching
  • a partial region of the charge carrier-supplying material of the trench structure directly adjoins material of the substrate.
  • insulation material typically less than 2 nm to remain or be formed or introduced between the substrate and the charge-supplying material of the trench structure. In this case, upon application of suitable electrical potentials to the trench structure and the control gate, electrical charge carriers can tunnel through the thin electrically insulating layer.
  • the charge storage region may be a floating gate.
  • a trained as a floating gate Charge storage region polysilicon have.
  • a gate insulating layer for electrically insulating the channel region from the floating gate is provided between the substrate and the floating gate.
  • the charge storage region may be an electrically insulating charge storage region.
  • a silicon oxide-silicon nitride-silicon oxide layer sequence O layer sequence
  • the silicon nitride layer may be replaced by another material such as alumina (Al 2 O 3 ), yttria (Y 2 O 3 ), lanthana (LaO 2 ), hafnia (HfO 2 ), and / or zirconia (ZrO 2 ).
  • Such an electrically insulating charge storage region is also referred to as a charge trapping layer.
  • electrical charge carriers are injected into the silicon nitride layer of the ONO layer sequence, where they are permanently stored, in particular, in imperfections.
  • the substrate may have a well region that has the charge carriers, in particular doping atoms, of the first conductivity type, and may have a charge carrier, in particular dopant atoms, of the region having the second conductivity type, wherein the components of the storage cell are formed in the well region.
  • the substrate of the memory cell of the present invention it is not necessary to use a homogeneous substrate become. It is possible, for example, to form an n-doped well region in a p-doped substrate and to form the memory cell according to the invention therein. Also, a multiple well structure of vividly interleaved well regions of different conductivity types is possible (eg, an n-well in a p-substrate and a p-well in the n-well).
  • the memory cell can have a plurality of spatially separated control gates which can be controlled separately, such that by applying predeterminable electrical potentials to at least one selected one of the control gates, electrical charge carriers can be introduced from the trench structure into an area of the charge storage area adjacent to the at least one selected control gate.
  • control gates which can be controlled separately, such that by applying predeterminable electrical potentials to at least one selected one of the control gates, electrical charge carriers can be introduced from the trench structure into an area of the charge storage area adjacent to the at least one selected control gate.
  • a plurality of field-effect transistors in the memory cell according to the invention can illustratively be formed next to one another in the substrate.
  • Each of the transistors is assigned its own control gate.
  • a common charge storage layer can be provided for all the field-effect transistors; alternatively, each transistor can have its own charge storage layer.
  • a memory cell of the invention may comprise only one field effect transistor, in the charge storage area in each of two spatially separated sections charge carriers can be introduced, each of the sections may be associated with a separately controllable control gate.
  • information of one bit may be stored in each of the sections, so that a plurality of bits can be stored in a field effect transistor.
  • the memory cell according to the invention can be set up such that several bits of information can be stored in the memory cell.
  • n bit information can be stored in the charge storage layer using n control gates.
  • Such a multi-bit memory cell may be programmed, for example, as follows. First of all, by means of the inventive injection of hot charge carriers, all information can be deleted from the charge storage layer or the charge storage layers of the at least one field-effect transistor, which clearly corresponds to resetting the memory contents. This can be done, for example, by the fact that hot electrons can be introduced into the entire charge storage layer. Subsequently, each portion of the charge storage layer associated with a respective control gate may be fowled, for example, by Fowler-Nordheim tunneling, i. with particularly good spatial resolution and thus limited to a specific selected area of the charge storage layer, be programmed separately. Thus, the memory cell of the invention is set up as a high-density storage medium.
  • the charge carriers of the first conductivity type and / or the charge carriers of the second conductivity type can be doping atoms.
  • This refinement relates in particular to realizations of the memory cell using a semiconductor material for the substrate and / or the charge-supplying material.
  • the memory cell arrangement may be designed such that different memory cells are electrically decoupled from one another by means of the electrically insulating jacket regions.
  • This refinement corresponds to the realization of the trench structure using a clearly hollowed-out STI structure which, apart from its isolation function, additionally fulfills the function of a charge carrier feed structure for injecting electrical charge carriers into the substrate.
  • the trench structure may be formed by forming at least one trench in the substrate, forming an electrically insulating cladding region at least on at least a part of the surface of the at least one trench, and forming an electrically conductive core region in the at least one trench.
  • first a trench in the substrate are introduced and subsequently formed an electrically insulating jacket area. This can be done, for example, by generating an electrically insulating layer by means of thermal oxidation of the side wall of the trench.
  • charge carrier-supplying material for example doped polysilicon, can be introduced into the obtained arrangement, whereby the trench structure is formed.
  • the trench may be filled with electrically insulating material and partially removed from the trench using a lithography and an etching process.
  • the trench structure can thus be formed by forming at least one trench in the substrate and filling the trench with electrically insulating material. A part of the electrically insulating material is removed from the trench, whereby the electrically insulating cladding region is formed. An electrically conductive core region is formed in the at least one trench.
  • FIG. 3 a memory cell 300 according to a first embodiment of the invention described.
  • the memory cell 300 is formed on and in a p-doped silicon substrate 301.
  • a first source / drain region 302 is formed as an n + -doped region.
  • a second source / drain region 303 is formed as an n + -doped region.
  • a channel region 304 of the floating gate arrangement 300 is formed in the surface region between the first and second source / drain regions 302, 303.
  • a first trench structure 305 is formed, which comprises a first n + -doped polysilicon core 307 and a first silicon oxide partially formed around it. Sheath 308 contains.
  • a second trench structure 306 is formed in the substrate 301, laterally of the second source / drain region 303 and outside of the channel region 304. This includes a second n + -doped polysilicon core 309 and second silicon oxide cladding 310 surrounding the core 309.
  • an electrical insulation region 311 made of silicon oxide material the channel region 304 is electrically separated from a floating gate 312 made of polysilicon material.
  • the control gate 313 formed over the floating gate 312 is electrically isolated from the floating gate 312.
  • Contacting elements 314 are realized as vias and make it possible to provide the trench structures 305, 306 with a predeterminable electrical potential.
  • a first pn junction 315 that is, a first diode junction is provided.
  • a second pn junction 316 is realized between the second n + -doped polysilicon core 309 and the p-doped silicon substrate 301.
  • the trench structures 305, 306 have due to the Siliziumoxid-coats 308, 310, an electrical insulation of in Figure 3 shown memory cell of possibly formed in adjacent portions of the substrate 301 other components, such as other memory cells on.
  • a p-substrate a p-substrate
  • n-substrate reverse doping for substrate, wells, trench filling, source / drain
  • a metallic filling for example of tungsten material, can also be used ,
  • Figure 9 describes how electrical charge carriers can be introduced into the n + -type floating gate 312 made of polysilicon as a charge storage region, that is, how information can be programmed into the storage cell 300.
  • the first and second n + -doped polysilicon cores 307, 309 brought to a negative electrical potential (eg of -2 volts).
  • the source / drain regions 302, 303 are held at the potential of the substrate.
  • To the control gate 313 (which may or may not be doped n +, for example) a positive electrical potential of eg + 8 volts is applied.
  • the doping of the gate regions is of no particular importance, so that no definition of a specific doping type is given.
  • the p-doped silicon substrate 301 can be held at the electrical ground potential.
  • first electrons 902 are injected into the silicon substrate 201 due to the forward biased diodes 315, 316, as indicated by first current paths 900. Due to the strong positive bias of the control gate 313, the injected negatively charged first electron 902 accelerates toward the channel region 304 of the p-doped substrate 301, which is illustrated by means of second current paths 901. The accelerated, "hot" second electrons 903 can then pass through the gate insulating layer of the electrical isolation region 311, that is to say between the channel region 304 and the floating gate 312, and be injected into the floating gate 312 and remain there permanently.
  • the floating gate memory cell 300 In a first operating state, in which the floating gate 312 is ideally free of electrical charge carriers, the floating gate memory cell 300 has a different threshold voltage than in a scenario in which electrical charge carriers are injected in the floating gate 312.
  • electrons contained within the floating gate 312 act similarly to an external electrical voltage applied to the control gate 313, so that the amount of current flow between the source / drain regions 302, 303 is dependent upon a fixed voltage applied therebetween. whether electric charge carriers are injected in the floating gate 312 or not.
  • the magnitude of such a read current includes information having a logical value "1" (e.g., floating gate electrodes 312) or a logic "0" (e.g., floating gate 312 electrons).
  • the memory cell 400 differs from the memory cell 300 essentially in that the conductivity types of the doped regions are designed differently in the memory cell 400 than in the memory cell 300.
  • the memory cell 400 also has a p-doped silicon substrate 301. However, in the p-doped silicon substrate 301, an n-doped well region 401 is formed, which may also be referred to as a high-voltage n-well region. As the first and second source / drain regions 402, 403, p + -doped regions are formed in the first and second surface regions of the n-well region 401.
  • first and second trench structures 404, 405 are provided which extend from the first and second trench structures 305, 306 Figure 3 in that first and second p + doped polysilicon cores 406, 407 of the trench structures 404, 405 are made of p + doped polysilicon, rather than of nu doped polysilicon as in FIG Figure 3 , are made.
  • This in Figure 4 provided n + -doped control gate can alternatively be realized as a p + -doped control gate.
  • the junction between the first p + -doped polysilicon core 406 and the n-well region 401 forms a first diode 315
  • the junction between the second n + -doped polysilicon core 407 and the n-well region 401 forms a second diode 316.
  • Figure 10 the functionality of memory cell 400 is described.
  • Figure 10 2 shows what potentials are to be applied to the terminals of the memory cell 400 in order to inject hot holes (designated h + in the figures) into the floating gate 312.
  • the first and second p + -doped polysilicon cores 406, 407 are brought to a potential of, for example, + 2 volts.
  • the source / drain terminals 402, 403 are held at the potential of the n-well 401.
  • the terminals of the p-doped substrate 301 and the n-well region 401 are preferably maintained at the electrical ground potential.
  • the control gate 408, however, is brought to a negative potential of, for example, -8 volts. It should be noted that the n-well can be set to a positive potential.
  • the diodes 315, 316 are according to Figure 10 operated in the forward direction. Due to the forward-biased diodes 315, 316, first holes 1002 h + are injected into the n-well region 401, as illustrated by first current paths 1000. Due to the high negative potential at the control gate 408, the positively charged first 1002 holes are accelerated toward the channel region 304, thereby converting the first holes 1002 into "hot" second holes 1003. The second holes 1003, due to their sufficiently high kinetic energy, can reach the floating gate region 312 into which they are injected.
  • a read current at a high voltage at a constant voltage between the source / drain regions 402, 403 may be assigned to information of logical value "1" and "0", respectively.
  • FIG. 5 a memory cell 500 according to a third embodiment of the invention described.
  • memory cell 500 differs from that in Figure 3 shown memory cell 300 substantially in that the memory cell is not formed directly in the p-doped substrate 301, but in a p-doped small well region 502, which in turn is formed within an n-doped large well region 501.
  • the memory cell according to the invention directly in a.
  • Substrate is integrated, but it can also be formed in an introduced into the substrate well area.
  • a negative potential can be applied to the (inner) p-well. This means that the voltages applied to other areas must always be seen in relation to this negative well potential.
  • memory cell 600 differs from that in Figure 3 shown memory cell 300 substantially in that instead of the floating gate 312 as a charge storage region, a silicon nitride layer (Si 3 N 4 ) 601 sandwiched between two silica partial layers of the electrical insulation region 311, whereby between the channel region 304 and the control gate 313, an ONO layer sequence (silicon oxide-silicon nitride-silicon oxide) is formed.
  • the silicon nitride layer 601 of the ONO layer sequence is used as a charge trapping layer, that is, as an electrically insulating charge storage region.
  • the injection of electrons into the silicon nitride layer 601 is similar to the injection of electrons into the floating gate 312 in the memory cell 300, due to the electrical insulating property of silicon nitride material, the charge carriers placed in the silicon nitride layer 601 remain at the respective injection site within the silicon nitride layer 601 and are not distributed freely in the charge storage region.
  • FIG. 7 a memory cell 700 according to a fifth embodiment of the invention described.
  • the memory cell 700 differs from that in FIG Figure 4 1, that the floating gate 312 from Figure 4 is replaced by the silicon nitride layer 601.
  • FIG. 8 a memory cell 800 according to a sixth embodiment of the invention described.
  • the memory cell 800 differs from the one in FIG Figure 5 shown memory cell 500 in that the floating gate 312 is replaced by the silicon nitride layer 601.
  • FIG. 11 a memory cell 1100 according to a seventh embodiment of the invention described.
  • the memory cell 1100 differs from that in Figure 6 shown memory cell 600 substantially by, 1 that instead of only one memory field effect transistor in Figure 6 according to fig.11 a first memory field effect transistor 1101 and at least one second memory field effect transistor 1102 are formed.
  • the Control gates 313 of the first and second memory field effect transistors 1101, 1102 can be controlled separately.
  • the control gates 313 of the two memory field-effect transistors 1101, 1102 are spatially separated from one another and can be driven separately electrically.
  • the memory cell 1100 has an ONO layer sequence 1103, which is formed from a first silicon oxide layer 1104, a silicon nitride layer 1105 as a "charge trapping layer" and a second silicon oxide layer 1106.
  • a negative electrical potential of, for example, -2 volts is applied to the n + -doped polysilicon cores 307, 309 of the trench structures 305, 306.
  • a positive electrical potential of, for example, + 8 volts is applied to the control gates 313 of the first and the second memory field effect transistor 1101, 1102, in each case a positive electrical potential of, for example, + 8 volts is applied. Due to the potential relationships, the electrons emerging from the diodes 315, 316 are accelerated towards the channel regions 304 of the memory field effect transistors 1101, 1102 and injected in a first charge storage region 1107 and in a second charge storage region 1108 of the ONO layer sequence 1103. This process step may be referred to as resetting the memory contents of the field effect transistors 1101, 1102.
  • Fowler-Nordheim tunneling selectively removes the electrons introduced into the respective charge storage region 1107 or 1108 by injecting hot electrons.
  • the very good spatial resolution of Fowler-Nordheim programming can be used to advantage in the introduction / removal of charge carriers.
  • the memory cell 1100 can separately describe different memory field effect transistors of the memory cell.
  • the memory cell of the invention can be used as a multi-bit memory cell such as a 2-bit memory cell as in FIG fig.11 , be realized.
  • different areas of the ONO layer sequence 1103 can be operated as a charge storage layer for the separate introduction / removal of electrical charge carriers and thus as separate information bit storage areas.
  • An advantageous mode of operation of such a memory cell 1100 is that first all memory cells are reset by injecting charge carriers (for example by means of hot carrier tunnels) into the entire charge storage layer 1103. The programming of information is then performed using location-specific removal of charge carriers from a selected region of the charge storage layer, e.g. using Fowler-Nordheim tunnels.
  • hot carrier injection may be selective by applying the one control gate as described puts a positive potential, leaves the other control gate to substrate or well potential. As a result, the charge carriers are selectively accelerated only to a gate, whereby a selective programming is achieved.
  • Figure 12 a schematic layout view (top view) of a memory cell array 1200 according to an embodiment of the invention described.
  • the memory cell array 1200 includes a plurality of memory cells, such as those shown in FIG Figure 3 are shown. For clarity are in Figure 12 Reference number from Figure 3 inserted.
  • the memory cell array 1200 is realized SNOR architecture.
  • the control gate 313 is in Figure 12 for a row of memory cells running together and is thus realized similar to a conductor track.
  • a substrate contacting (not in Fig. 12 drawn)
  • a defined electrical potential can be provided to the substrate 301.
  • printed conductors 1202 and printed circuit vias 1203 or contact holes 1201 are shown, by means of which the source / drain regions can be contacted.
  • FIG. 13 a memory cell 1300 according to an eighth embodiment of the invention described.
  • the memory cell 1300 differs from the memory cell 1100 essentially in that of FIG fig.11 right, ie the second source / drain region 303 of the first memory field effect transistor 1101 with the according to fig.11 left, ie second source / drain region 302 of the second memory field effect transistor 1102 is designed as a common source / drain region 1301.
  • the common source / drain region 1301 thus represents a coherent implantation region.
  • Such a combination of two source / drain regions of two adjacent memory cells can also be realized for a memory cell arrangement having a multiplicity of memory cells. If you put the source / drain regions 303/302 together, you will clearly get a kind of NAND structure.
  • Figure 14 a schematic layout view (top view) of a memory cell array 1400 according to another embodiment of the invention described, wherein in the memory cell array tracks 1401 are provided.
  • FIG. 12 illustrates a schematic layout from which it can be seen how memory cells according to the invention can be integrated into a NAND structure. Integration into other arrangements (eg NOR, ...) is also possible. Therefore, the examples shown are for illustrative purposes only, without being limited to any particular memory arrangement.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Claims (20)

  1. Cellule de mémoire
    - comprenant un substrat (301) qui comporte des porteurs de charge d'un premier type de conductivité;
    - comprenant une zone (302) de source/drain dans une première partie de surface du substrat et comprenant une deuxième zone (303) de source/drain dans une deuxième partie de surface du substrat ;
    - comprenant une zone (304) de canal dans une partie de surface du substrat entre la première et la deuxième zone de source/drain ;
    - comprenant une zone (312) d'accumulation de charges au-dessus de la zone de canal ;
    - comprenant une grille (313) de commande au-dessus de la zone d'accumulation de charges et isolée électriquement de la zone d'accumulation de charges ;
    - comprenant une structure (305, 306) de sillons formée dans le substrat et ayant du matériau (307, 309) fournissant des porteurs de charge et ayant des porteurs de charge d'un deuxième type de conductivité et une zone (308) isolante entre le substrat et au moins une partie du matériau fournissant des porteurs de charge, dans laquelle la structure de sillons dont est munie au moins en partie d'un isolant de paroi shallow-trench ;
    - dans laquelle le premier type de conductivité est différent du deuxième type de conductivité de manière à former une jonction (315, 316) de diode entre le substrat et le matériau de la structure de sillons fournissant des porteurs de charge ;
    - dans laquelle la cellule de mémoire est telle, qu'en appliquant des potentiels électriques pouvant être prescrits à la cellule de mémoire, des porteurs de charge électrique peuvent être introduits du matériau de la structure de sillons fournissant des porteurs de charge dans la zone d'accumulation de charges.
  2. Cellule de mémoire suivant la revendication 1,
    dans laquelle la structure de sillons pénètre plus profondément dans le substrat que la première zone et la deuxième zone de source/drain.
  3. Cellule de mémoire suivant la revendication 2,
    dans laquelle la structure de sillons pénètre au moins plus profondément dans le substrat d'un facteur de trois que la première et la deuxième zones de source/drain.
  4. Cellule de mémoire suivant l'une des revendications 1 à 3,
    dans laquelle la structure de sillons s'étend dans la direction sensiblement verticale par rapport à la surface du substrat.
  5. Cellule de mémoire suivant l'une des revendications 1 à 4, dans laquelle la structure de sillons est formée latéralement à au moins l'une des zones de source/drain et en dehors de la zone de canal.
  6. Cellule de mémoire suivant des revendications 1 à 5, comprenant deux structures de sillons, dont l'une est disposée latéralement à la première zone de source/drain et en dehors de la zone de canal et dont l'autre est disposée latéralement à la deuxième zone de source/drain et à l'extérieur de la zone de canal.
  7. Cellule de mémoire suivant l'une des revendications 1 à 6, dans laquelle la structure de sillons a une zone de surface latérale isolante électriquement sur au moins une partie de la paroi latérale des sillons et une zone de coeur conductrice de l'électricité garnie dans les sillons de façon à ce que des porteurs de charge électrique puissent sortir de la structure de sillons seulement des parties du substrat dans lesquelles la zone de coeur n'est pas entourée de la partie de surface latérale où dans des parties dans lesquelles la partie de surface latérale a une épaisseur suffisamment petite pour permettre un courant de tunnel.
  8. Cellule de mémoire suivant l'une des revendications 1 à 7, dans laquelle la zone d'accumulation de charges est, une grille flottante.
  9. Cellule de mémoire suivant la revendication 8,
    dans laquelle la grille flottante comporte du polysilicium.
  10. Cellule de mémoire suivant les revendications 8 et 9, dans laquelle une couche isolante de grille est déposée entre le substrat et la grille flottante.
  11. Cellule de mémoire suivant l'une des revendications 1 à 7, dans laquelle la zone d'accumulation de charges est une zone d'accumulation de charges isolante du point de vue électrique.
  12. Cellule de mémoire suivant la revendication 11,
    dans laquelle la zone d'accumulation de charges isolante du point de vue électrique a :
    • une succession de couches oxyde de silicium-nitrure de silicium-oxyde de silicium
    • du nitrure de silicium ;
    • de l'oxyde d'aluminium ;
    • de l'oxyde d'yttrium ;
    • de l'oxyde de lanthane ;
    • de l'oxyde d'hafnium ;
    • de l'oxyde de zirconium ;
    • une succession de couches oxyde de silicium-oxyde d'aluminium-oxyde de silicium ;
    • une succession de couches oxyde de silicium-oxyde d'yttriumoxyde de silicium ;
    • une succession de couches oxyde de silicium-oxyde de lanthane-oxyde de silicium ;
    • une succession de couches oxyde de silicium-oxyde d'hafniumoxyde de silicium ;
    • une succession de couches oxyde de silicium-oxyde de zirconium ; et/ou
    • une autre succession de couches, qui rend possible une accumulation permanente de charges
    ou en est constituée.
  13. Cellule de mémoire suivant l'une des revendications 1 à 12, dans laquelle le substrat a une partie de caisson comportant les porteurs de charge du premier type de conductivité et une partie ayant des porteurs de charge du deuxième type de conductivité, dans laquelle les composants de la cellule de mémoire sont formés dans la partie de caisson.
  14. cellule de mémoire suivant l'une des revendications 1 à 13 qui a une multiplicité de grilles de commande séparées dans l'espace et pouvant être commandées séparément du point de vue électrique de façon à ce qu'en appliquant des potentiels électriques prescrits à au moins l'une sélectionnée des grilles de commande, on puisse introduire des porteurs de charge de la structure de sillons dans une partie, voisine de la au moins une grille de commande choisie, de la zone d'accumulation de charges.
  15. Cellule de mémoire suivant l'une des revendications 1 à 14, dans laquelle les porteurs de charge du premier type de conductivité et/ou et les porteurs de charge du deuxième type de conductivité sont des atomes de dopage.
  16. Dispositif à cellules de mémoire comprenant une multiplicité de cellules de mémoire intégrées dans le substrat suivant l'une des revendications 1 à 15.
  17. Dispositif à cellules de mémoire suivant la revendication 16,
    qui est constitué de façon à ce que des cellules de mémoire différentes soient découplées électriquement les unes des autres au moyen des parties de surfaces latérales isolantes du point de vue électrique.
  18. Procédé de production d'une cellule de mémoire
    dans lequel, 1
    - On forme une première zone (302) de source/drain dans une première partie de surface d'un substrat, qui comporte des porteurs de charge d'un premier type de conductivité, et on forme une deuxième zone (303) de source/drain dans une deuxième partie de surface du substrat ;
    - on forme une zone (304) de canal dans une partie de surface du substrat entre la première et la deuxième zones de source/drain ;
    - on forme une zone (312) d'accumulation de charges au-dessus de la zone de canal ;
    on forme une grille (313) de commande au-dessus de la zone d'accumulation de charges, grille qui est isolée du point de vue électrique de la zone d'accumulation de charges ;
    - on forme une structure (305, 306) de sillons, qui est disposée dans le substrat et qui a du matériau (307, 309) fournissant des porteurs de charge et ayant des porteurs de charge d'un deuxième type de conductivité et une partie (308) isolante entre le substrat et au moins une partie du matériau fournissant des porteurs de charge, la structure de sillons étant munie au moins en partie d'un isolant de paroi latérale shallow-trench ;
    - on fait en sorte que le premier type de conductivité soit différent du deuxième type de conductivité de manière à former une jonction (315, 316) de diode entre le substrat et le matériau de la structure de sillons fournissant les porteurs de charge ;
    - on fait en sorte que la cellule de mémoire puisse, en appliquant des potentiels électriques pouvant être prescrits par la cellule de mémoire, faire passer les porteurs de charge électrique de la structure de sillons fournissant des porteurs de charge dans la zone d'accumulation de charges.
  19. Procédé suivant la revendication 18, dans lequel
    on forme la structure de sillons en
    • formant au moins un sillon dans le substrat ;
    • formant une partie de surface latérale isolante du point de vue électrique dans au moins une partie de la surface du au moins un sillon ;
    • on forme une partie de coeur conductrice de l'électricité dans le au moins un sillon.
  20. Procédé suivant la revendication 18, dans lequel
    on forme la structure de sillons en
    • formant au moins un sillon dans le substrat ;
    • remplissant le sillon de matériau isolant du point de vue électrique ;
    • éliminant une partie du matériau isolant du point de vue électrique du sillon en formant ainsi la partie de la surface latérale isolante électriquement ;
    • formant une partie de coeur conductrice de l'électricité dans le au moins un sillon.
EP04707864A 2003-02-05 2004-02-04 Cellule de memoire, systeme de cellules de memoire et procede de fabrication d'une cellule de memoire Expired - Fee Related EP1590832B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10304654A DE10304654A1 (de) 2003-02-05 2003-02-05 Speicherzelle, Speicherzellen-Anordnung und Verfahren zum Herstellen einer Speicherzelle
DE10304654 2003-02-05
PCT/DE2004/000186 WO2004070841A2 (fr) 2003-02-05 2004-02-04 Cellule de memoire, systeme de cellules de memoire et procede de fabrication d'une cellule de memoire

Publications (2)

Publication Number Publication Date
EP1590832A2 EP1590832A2 (fr) 2005-11-02
EP1590832B1 true EP1590832B1 (fr) 2009-11-18

Family

ID=32730771

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04707864A Expired - Fee Related EP1590832B1 (fr) 2003-02-05 2004-02-04 Cellule de memoire, systeme de cellules de memoire et procede de fabrication d'une cellule de memoire

Country Status (5)

Country Link
US (1) US7176519B2 (fr)
EP (1) EP1590832B1 (fr)
CN (1) CN100382324C (fr)
DE (2) DE10304654A1 (fr)
WO (1) WO2004070841A2 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005277171A (ja) * 2004-03-25 2005-10-06 Toshiba Corp 半導体装置およびその製造方法
JP2007194259A (ja) * 2006-01-17 2007-08-02 Toshiba Corp 半導体装置及びその製造方法
US7982284B2 (en) * 2006-06-28 2011-07-19 Infineon Technologies Ag Semiconductor component including an isolation structure and a contact to the substrate
US7911021B2 (en) * 2008-06-02 2011-03-22 Maxpower Semiconductor Inc. Edge termination for semiconductor devices
WO2010014283A1 (fr) * 2008-07-30 2010-02-04 Max Power Semiconductor Inc. Dispositifs latéraux contenant une charge permanente
US7960783B2 (en) * 2008-08-25 2011-06-14 Maxpower Semiconductor Inc. Devices containing permanent charge
WO2010065428A2 (fr) * 2008-12-01 2010-06-10 Maxpower Semiconductor Inc. Dispositifs de puissance à grille mos, procédés et circuits intégrés
US9000527B2 (en) 2012-05-15 2015-04-07 Apple Inc. Gate stack with electrical shunt in end portion of gate stack
US8912584B2 (en) 2012-10-23 2014-12-16 Apple Inc. PFET polysilicon layer with N-type end cap for electrical shunt

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4454646A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
US5515319A (en) * 1993-10-12 1996-05-07 Texas Instruments Incorporated Non-volatile memory cell and level shifter
DE19600307C1 (de) * 1996-01-05 1998-01-08 Siemens Ag Hochintegrierter Halbleiterspeicher und Verfahren zur Herstellung des Halbleiterspeichers
US6330190B1 (en) * 1996-05-30 2001-12-11 Hyundai Electronics America Semiconductor structure for flash memory enabling low operating potentials
JPH10173157A (ja) * 1996-12-06 1998-06-26 Toshiba Corp 半導体装置
JPH1187664A (ja) * 1997-04-28 1999-03-30 Nippon Steel Corp 半導体装置及びその製造方法
TW428287B (en) * 1998-12-21 2001-04-01 United Microelectronics Corp Manufacturing method for flash memory and the operation method for its erasure
TW484213B (en) * 2001-04-24 2002-04-21 Ememory Technology Inc Forming method and operation method of trench type separation gate nonvolatile flash memory cell structure
US6566200B2 (en) * 2001-07-03 2003-05-20 Texas Instruments Incorporated Flash memory array structure and method of forming

Also Published As

Publication number Publication date
EP1590832A2 (fr) 2005-11-02
WO2004070841A2 (fr) 2004-08-19
DE10304654A1 (de) 2004-08-19
US7176519B2 (en) 2007-02-13
US20050285182A1 (en) 2005-12-29
CN1774808A (zh) 2006-05-17
DE502004010394D1 (de) 2009-12-31
WO2004070841A3 (fr) 2004-11-04
CN100382324C (zh) 2008-04-16

Similar Documents

Publication Publication Date Title
DE69733630T2 (de) EEPROM-und NVRAM-Niederspannungstransistoren und Verfahren zur Herstellung
DE3002493C2 (fr)
DE4219854C2 (de) Elektrisch löschbare und programmierbare Halbleiterspeichereinrichtung und ein Verfahren zur Herstellung derselben
DE102006062403B4 (de) Integriertes Schaltkreisbauelement sowie Herstellungs- und Betriebsverfahren
DE3203516A1 (de) Nicht fluechtige, elektrisch umprogrammierbare floating-gate-speicheranordnung
DE60316449T2 (de) Nichtflüchtige speicherarrayarchitektur mit kontaktloser separater p-mulde mit gleichförmiger tunnelung (cusp), herstellung und betrieb
DE102004006505A1 (de) Charge-Trapping-Speicherzelle und Herstellungsverfahren
DE102007052217A1 (de) Integrierter Schaltkreis mit NAND-Speicherzellen-Strängen
WO2004059738A1 (fr) Cellule memoire a transistor a effet de champ a aileron de semi-conducteur, dispositif a cellules memoire a transistor a effet de champ a aileron de semi-conducteur, et procede pour realiser une cellule memoire a transistor a effet de champ a aileron de semi-conducteur
EP1590832B1 (fr) Cellule de memoire, systeme de cellules de memoire et procede de fabrication d'une cellule de memoire
EP1532689B1 (fr) Element semi-conducteur de memoire non volatile et procede de realisation et procede de commande correspondants
DE19807010A1 (de) Verfahren zur Herstellung einer nichtflüchtigen Speichereinrichtung
DE102004047610A1 (de) Integrierte Speicher-Schaltungsanordnung mit Ansteuerschaltung und Verwendungen
DE19949805C2 (de) In Silizium-auf-Isolator gebildetes, nichtflüchtiges Direktzugriffs-Speicherelement
EP1374308B1 (fr) Reseau de cellules de memoire comportant des cellules de memoire adressables individuellement et son procede de fabrication
DE19958144A1 (de) Programmierbare Zwischenverbindungszelle zum wahlweisen Verbinden von Schaltkreisknoten in einem integrierten Schaltkreis
EP1399973A2 (fr) Ensemble transistor, procede pour l'exploitation d'un ensemble transistor comme memoire de donnees et procede pour la production d'un ensemble transistor
EP1330845B1 (fr) Cellule de memoire a semi-conducteur et son procede de fabrication
EP1723669A1 (fr) Cellule de memoire eeprom destinee a des temperatures elevees
DE10146978A1 (de) Flash-Speicherzelle mit vergrabenem Floating-Gate und Verfahren zum Betreiben einer solchen Flash-Speicherzelle
DE19929618B4 (de) Verfahren zur Herstellung einer nichtflüchtigen Halbleiter-Speicherzelle mit separatem Tunnelfenster
DE102006024121B4 (de) Nichtflüchtige Speicherzelle einer in einem Halbleiterplättchen integrierten Schaltung, Verfahren zu deren Herstellung und Verwendung einer nichtflüchtigen Speicherzelle
EP1466370B1 (fr) Procede de formation d'une cellule de memoire non volatile a semi-conducteur a deux bits
DE19939092B4 (de) Speicherbereich eines EEPROM sowie bereichsspezifische Programmier- und Löschverfahren
DE10231202A1 (de) Vertikaltransistor-Speicherzelle, Speicherzellen-Anordnung, Verfahren zum Herstellen einer Vertikaltransistor-Speicherzelle und Verfahren zum Betreiben einer Vertikaltransistor-Speicherzelle

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20050704

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL LT LV MK

DAX Request for extension of the european patent (deleted)
RBV Designated contracting states (corrected)

Designated state(s): DE

RIN1 Information on inventor provided before grant (corrected)

Inventor name: SCHULER, FRANZ

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE

REF Corresponds to:

Ref document number: 502004010394

Country of ref document: DE

Date of ref document: 20091231

Kind code of ref document: P

RAP2 Party data changed (patent owner data changed or rights of a patent transferred)

Owner name: INFINEON TECHNOLOGIES AG

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20100819

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20170425

Year of fee payment: 14

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 502004010394

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20180901