EP1518266A1 - Procede de production d'un transistor bipolaire a heterojonction et transistor bipolaire a heterojonction - Google Patents

Procede de production d'un transistor bipolaire a heterojonction et transistor bipolaire a heterojonction

Info

Publication number
EP1518266A1
EP1518266A1 EP03732493A EP03732493A EP1518266A1 EP 1518266 A1 EP1518266 A1 EP 1518266A1 EP 03732493 A EP03732493 A EP 03732493A EP 03732493 A EP03732493 A EP 03732493A EP 1518266 A1 EP1518266 A1 EP 1518266A1
Authority
EP
European Patent Office
Prior art keywords
layer
emitter
deposited
passivation layer
ledge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03732493A
Other languages
German (de)
English (en)
Inventor
Dag Behammer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Monolithic Semiconductors GmbH
Original Assignee
United Monolithic Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Monolithic Semiconductors GmbH filed Critical United Monolithic Semiconductors GmbH
Publication of EP1518266A1 publication Critical patent/EP1518266A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors

Definitions

  • the invention relates to a method for producing a hetero-bipolar transistor and a hetero-bipolar transistor.
  • Heterobipolar transistors in particular in GaAs-based compound semiconductor materials, typically have a relief structure with an emitter shape referred to as a mesa over a base layer, the contacts for controlling the base laterally from the emitter-mesa structure are spaced.
  • passivation of the semiconductor surface of the base layer between base contacts and emitter mesa with a semiconductor material depleted of charge carriers can significantly improve the long-term stability of the component properties, in particular the current gain.
  • a passivation layer is referred to in general for HBT and also in the following as a ledge.
  • the ledge consists of emitter semiconductor material, in the case of an emitter made up of a plurality of semiconductor layers, at least the material of the emitter layer immediately following the base layer and typically has a small layer thickness.
  • a method is known in which a lithographically structured metallic emitter contact as a mask for io- serves as reactive anisotropic etching of the emitter mesa, a thin residual layer of the emitter semiconductor material InGaP with a thickness of approximately 70 nm being left on the base layer consisting of GaAs on the side of the emitter mesa.
  • the structure of the ledge is defined in this residual layer, again using ion-reactive etching processes (RIE).
  • US Pat. No. 5,668,388 describes a particularly advantageous layer structure for the emitter of an HBT on GaAs which describes the highly selective etchability between GaAs and InGaP in a layer sequence with several GaAs
  • a first emitter layer made of InGaP with a layer thickness of approximately 30 nm is deposited on the GaAs base layer, which is covered by a GaAs layer only 5 nm thick and then further InGaP and GaAs layers.
  • the mesa structure is etched up to the very thin GaAs layer using a previously structured emitter-metal contact as an etching mask, with slight undercutting of the semiconductor layers under the contact metal layer.
  • the lateral structure of the ledge is then defined in a photoresist layer applied over the entire area, and the thin GaAs layer and the InGaP emitter layer are etched away in the regions not protected by photoresist.
  • a similar layer sequence with alternating GaAs and InGaP layers is in IEEE Device Letters, Vol. 17, No. 12, pp. 555-556, in order to laterally etch back the semiconductor layers of the emitter under the metallic emitter contact with alternating use of selective etchants, whereby under the masking metallic emitter contact a ledge and an emitter mesa etched back laterally compared to it are formed.
  • GaAs also has a lateral one Forms an etch stop for an enclosed InGaP layer.
  • the ledge is aligned in a self-adjusting manner with respect to the emitter without additional lithography steps, but the setting of the lateral dimensions poses problems due to the repeatedly used wet-chemical etching steps.
  • the metallic emitter contact also serves as a mask for subsequent vapor deposition of contact metal for the base contact.
  • a self-aligning alignment of the emitter contact and the base contacts of an HBT is also known from EP 0 480 803 B1, where a defined distance between the emitter mesa and the base contacts is set by lateral spacers on an emitter mesa. A lateral indentation in the spacer layers prevents short circuits between the emitter contact and the base contact.
  • the present invention is based on the object of specifying a method for producing an HBT (or a component of comparable design) and an HBT, in particular produced by such a method, with particularly good long-term stability of the component properties.
  • the method according to the invention with the early deposition of a passivation layer leads to advantageous component properties in that the passivation layer deposited on the ledge reliably prevents damage to the ledge layer or the interface of the ledge to the base layer in the following process steps.
  • the passivation layer is structured and, with this structure, serves as a mask for a subsequent etching of the ledge.
  • This etching of the ledge can advantageously be carried out using a gentle isotropic, in particular wet-chemical, etching process. den, so that damage to the exposed base layer can be excluded. It can be seen that HBT components produced in this way reproducibly have very good long-term stability of the electrical component properties.
  • the passivation layer preferably remains permanently on the ledge, so that it is reliably protected against damage in subsequent process steps.
  • nitride in particular Si 3 N
  • a semiconductor etching stop layer for the ledge region that covers it and can be selectively etched on this ledge stop layer.
  • Nitride adheres very well to the semiconductor surface, so that there is no gap formation between the semiconductor layer and the passivation layer, which could lead to an uncontrolled and / or uneven etching of the ledge under the passivation layer.
  • the passivation layer can also, e.g. B.
  • nitride and oxide which are preferably deposited one after the other in partial layers, preferably the material adhering better to the semiconductor material, in the example nitride being deposited first, ie directly on the semiconductor surface.
  • the passivation layer is advantageously also deposited on the vertical flanks of the emitter mesa, for example in an essentially isotropic process such as a gas phase deposition CVD, so that the structure of the mesa remains uninfluenced by the crystal-gentle, in particular wet-chemical etching of the ledge layer and subsequent process steps.
  • the passivation layer can be structured using a photolithographically produced mask, which can also serve as a mask for producing metallic base contacts in a lift-off process.
  • a cover layer of the emitter mesa which also serves in particular as a first mask for structuring the emitter mesa in a preceding step, is preferably used as a second mask or as a basis for the second mask for structuring the passivation layer.
  • the use of the cover layer as a mask for structuring the passivation layer, which in turn masks the etching of the ledge, means that the semiconductor emitter mesa has a lateral indentation under the cover layer, which has essentially the lateral dimension of the ledge.
  • the use of the structured cover layer for the first and the second mask leads to a particularly symmetrical and / or uniform and precisely adjustable dimensioning of the ledge due to the self-aligned alignment using an essentially anisotropic etching process, which is particularly advantageous for long-term stable properties of the ledges produced in this way Components proves.
  • the space surrounded on several sides by the cover layer, semiconductor emitter mesa and ledge is, according to an advantageous development, permanently filled with a defined dielectric, in particular a polymer, preferably BGB (benzocyclobutene), in order to avoid the uncontrolled deposition of materials from subsequent process steps.
  • a metallic emitter contact can serve as the cover layer in a manner known per se from the prior art, in particular when it is implemented with a photolithographic second mask.
  • the cover layer is preferably not formed by the metallic emitter contact, but rather by a dielectric layer, preferably an oxide, deposited thereon, which after initial structuring is separated from the following etching steps in the remains essentially unaffected.
  • the dielectric cover layer enables the generation of a lateral indentation by under-etching with particularly high precision by selective etching of the metallic emitter contact layer and the structuring of the emitter semiconductor layers with essentially the lateral structures of the metallic contact, which is then only slightly under-etched in the semiconductor layers.
  • this minimizes electrochemical influences of the metal layers, which only offer the side flanks as contact surfaces with a wet chemical etchant.
  • the lateral structures of the emitter semiconductor layers which in this respect serve as an etching mask for the emitter semiconductor layers, which are preferably wet chemical etching, are reached, further undercutting of the lateral structure of the metallic contact in the emitter semiconductor layers can be kept very low , so that fluctuations in the lateral structure of the emitter semiconductor layers due to insufficiently controllable etching rate or in particular due to etching rate dependent on the crystal direction can be largely avoided or kept to a minimum and the lateral indentation determined by the underetching of the dielectric cover layer in the metallic contact layer and thus also the lateral extension of the ledge away from the emitter mesa can be precisely adjusted.
  • a protective layer in an intermediate step, in particular after the emitter semiconductor mesa has largely been completed, which in subsequent steps protects the already etched structure from renewed exposure to an etchant and can be removed again before the passivation layer is deposited ,
  • a protective layer can be produced without additional masking.
  • the semiconductor layers 2 to 10 on the GaAs substrate 1 form the vertical profile of an HBT, 2 the highly doped subcollector, 3 an InGaP stop layer, 4 the low-doped collector, 5 the base, 6 the InGaP emitter, 7 a very thin one GaAs stop layer, 8 an InGaP stop layer, which can also be used as a ballast resistor with increased thickness, 9 and 10 represent the GaAs / InGaAs emitter contact, which ends in 10 with a highly doped InGaAs layer (FIG. 1a).
  • the metallic contact layer 11 and the likewise metallic contact reinforcement 12 are applied (FIG. 1b).
  • Sputtered diffusion barriers such as WTiN, WSiN, TaN or WTiSiN are preferably used.
  • the double layer consisting of 11 and 12 should have a low mechanical tension, have good adhesion properties on InGaAs and can preferably be structured in a fluorine-based plasma.
  • the lacquer mask 14 (FIGS. 1c, d) produces a first mask structure 13a in this oxide layer, which then masks the etching of the metal layers 12 and 11 (FIGS. 1e, f).
  • the overhanging structure shown in FIG. 1g Due to the different lateral etching rates of the layers 11-13 depending on the etching parameters with a low la- When the oxide 13a is removed generally, the overhanging structure shown in FIG.
  • the lateral etching of the metallic layers 11 and 12 is direction-independent and easy to control, so that the degree of undercut can be set precisely.
  • the semiconductor emitter mesa in the layers 9 and 10 is preferably structured by wet chemical means (FIG. 1g).
  • the metal layers 11a, 12a remain essentially unchanged. This etching process takes place selectively to the InGaP layer 8, which is retained over the entire area.
  • the etching proceeds, in a manner known per se, preferably much faster perpendicular to the layer plane than in the layer plane.
  • a complete etching of the layers 9 and 10 in areas not covered by the metal layer 11 can be reliably achieved by specifying the time and / or optical observation of the etching progress, and at the same time it can be ensured that the semiconductor layers 9, 10 are only slight show further undercutting of the metal layer 11 and essentially follow its precisely adjustable lateral structure.
  • the photoresist mask 17 in FIG. 1 h protects the flanks of the layers 9a and 10a of the emitter mesa, which have been etched up to that point, from a lateral etching attack.
  • the InGaP layer 8 is subsequently wet-chemically, for. B. selectively etched in HCI to the GaAs layers 7 and 9a, the lateral undercut in the InGaP etching being very high and the protective layer 17 being severely underetched.
  • the lateral removal of the layer 8 automatically stops in a known manner on the GaAs layer 9a (FIG. 1 i).
  • a double layer (15, 16) consisting of SiN and SiO 2 becomes isotropic, preferably in a plasma separator - Application applied (Fig. 1j).
  • this double layer is removed with the cover layer structure 13b widened laterally by the passivation layer 15, 16 as a mask, with the overhang of 13b, there is no removal, so that the lateral structure designated 15a, 16a is formed in the double layer 15, 16 above the semiconductor layers 6, 7, the course of which depends essentially on the shape of the oxide mask 13a with the widening through the passivation layer 15, 16.
  • the GaAs layer 7 acts as a vertical etching stop.
  • the structure of 7a and 6a from 6 and 7 is then etched using the known methods for wet chemical etching of GaAs and InGaP (FIG. 11).
  • the etching is preferably carried out selectively in two steps, the GaAs layer 7 being removed in a first step and the undercut ⁇ of the mask ⁇ 5a remaining small owing to its very small thickness.
  • the etching of the InGaP layer 6 preferably takes place again using HCI, so that the GaAs layer 7a again acts as a lateral etching stop.
  • the emitter is now in the area of 8a, while the area outside is defined as a ledge.
  • the ledge with semiconductor layers 6a, 7a has a very uniform lateral extension, which is primarily determined by the initial underetching of the oxide mask 13a during the manufacture of the mesa, against the mesa due to this self-aligning manufacture to the emitter mesa.
  • FIG. 2a The process stage of FIG. 1g is taken up in FIG. 2a.
  • the photoresist layer 17 shown in FIGS. 1 h and 1i is replaced in FIG. 2 b by the self-aligned photoresist spacers 21 as a protective layer.
  • the photoresist is applied over the entire surface and exposed by flood exposure.
  • the oxide mask 13a is transparent for this exposure.
  • the metal layers 11a and 12a overhanging the semiconductor layers 9a and 10a provide protection against exposure of the photoresist on the flanks of 9a and 10a, which after development leads to the photoresist remaining on these flanks as a protective layer (FIG.
  • the resist spacers 21 protect following the etching of the InGaP layer 8, the InGaAs contact layer 10a before a lateral attack of the concentrated HCI (FIG. 2c).
  • the further process sequence corresponds to the previous embodiment.
  • the masking of a protective layer covering the semiconductor layers 9a, 10a, here the photoresist layer 21, by the metallic contact layer is generally of particular advantage for producing a protective layer on the lateral flanks of an emitter mesa.
  • BCB is, for example, spun on in liquid form, solidified at elevated temperature, planarized (18 in FIG. 2d) and removed again by etching outside the cavity, so that permanent filling 18a with BCB remains.
  • the filling of the cavity which can also be inserted in the process sequence according to FIG. 1, ensures that no lacquer or chemical residues remain in this area in later process steps, which may influence the component properties.
  • the oxide layer 13 is structured only slightly larger than the intended lateral dimension of the emitter semiconductor mesa in the form 13c and in the metallic layers 12c, 11c and the semiconductor layers 10c, 9c and 8c only underetched with slight lateral indentation, as illustrated in FIG. 3a.
  • a passivation layer 15, again preferably made of nitride, is deposited over the entire surface of this mesa structure and the layer 7 exposed in the process.
  • the structure 15c of the passivation layer serves as a mask for producing the ledge 6c, 7c in the semiconductor layers 6 and 7.
  • the ledge structure is not self-aligned with the emitter mesa (FIG. 3c).
  • a metal layer 20 is deposited over the entire surface, which forms the metallic base contacts 20c on the semiconductor layer 5 (FIG. 3d).
  • the base contacts extend up to the structure 15c of the passivation layer.
  • the metal layer deposited on the photoresist mask 20 is removed (FIG. 3e).
  • the photoresist mask 19 has a slight overhang and side flanks drawn in downwards.
  • the structure 15a in the passivation layer can also slightly recede against the vertical projection of the photoresist mask, which can be achieved by weakening the anisotropy during the etching of the passivation layer.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

L'invention se rapporte à un transistor bipolaire à hétérojonction, en particulier à base de GaAs, qui présente une structure avantageuse, ainsi qu'à un procédé de production d'un transistor bipolaire à hétérojonction qui permet d'obtenir un composant avantageux et stable à long terme.
EP03732493A 2002-06-10 2003-05-30 Procede de production d'un transistor bipolaire a heterojonction et transistor bipolaire a heterojonction Withdrawn EP1518266A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10225525 2002-06-10
DE10225525A DE10225525A1 (de) 2002-06-10 2002-06-10 Verfahren zur Herstellung eines Hetero-Bipolar-Transistors und Hetero-Bipolar-Transistor
PCT/EP2003/005658 WO2003105211A1 (fr) 2002-06-10 2003-05-30 Procede de production d'un transistor bipolaire a heterojonction et transistor bipolaire a heterojonction

Publications (1)

Publication Number Publication Date
EP1518266A1 true EP1518266A1 (fr) 2005-03-30

Family

ID=29557686

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03732493A Withdrawn EP1518266A1 (fr) 2002-06-10 2003-05-30 Procede de production d'un transistor bipolaire a heterojonction et transistor bipolaire a heterojonction

Country Status (7)

Country Link
US (1) US6946355B2 (fr)
EP (1) EP1518266A1 (fr)
CN (1) CN100378927C (fr)
AU (1) AU2003238428A1 (fr)
CA (1) CA2484791A1 (fr)
DE (1) DE10225525A1 (fr)
WO (1) WO2003105211A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10225525A1 (de) 2002-06-10 2003-12-18 United Monolithic Semiconduct Verfahren zur Herstellung eines Hetero-Bipolar-Transistors und Hetero-Bipolar-Transistor
US7655529B1 (en) * 2004-08-20 2010-02-02 Hrl Laboratories, Llc InP based heterojunction bipolar transistors with emitter-up and emitter-down profiles on a common wafer
JP2008004779A (ja) * 2006-06-23 2008-01-10 Matsushita Electric Ind Co Ltd 窒化物半導体バイポーラトランジスタ及び窒化物半導体バイポーラトランジスタの製造方法
US9530708B1 (en) 2013-05-31 2016-12-27 Hrl Laboratories, Llc Flexible electronic circuit and method for manufacturing same
CN107910363B (zh) * 2017-11-22 2020-01-14 成都海威华芯科技有限公司 一种异质结双极晶体管基极基座使用单层光罩蚀刻方法
CN109817701B (zh) * 2018-12-25 2022-05-10 泉州三安半导体科技有限公司 一种异质结双极晶体管发射极结构和发射极的薄化方法

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Also Published As

Publication number Publication date
DE10225525A1 (de) 2003-12-18
AU2003238428A1 (en) 2003-12-22
US6946355B2 (en) 2005-09-20
CN1659693A (zh) 2005-08-24
US20040175895A1 (en) 2004-09-09
CN100378927C (zh) 2008-04-02
WO2003105211A1 (fr) 2003-12-18
CA2484791A1 (fr) 2003-12-18

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