Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
  • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
  • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
  • H01L29/7923—Programmable transistors with more than two possible different levels of programmation

Definitions

• Determination arrangement method for determining electrical charge carriers and using an ONO field-effect transistor for determining an electrical charge
• the invention relates to a determination arrangement, a method for determining electrical charge carriers and the use of an ONO field-effect transistor for determining an electrical charge.
• the CVD process is a coating technology for forming a thin layer from the gas phase on a solid substrate.
• the principle of the CVD process is that gaseous starting materials are passed over a substrate and chemically broken down into their constituent parts, whereby a new layer grows on the substrate surface.
• the starting materials, the so-called precursors are usually broken down thermally, that is to say by heating the substrate, and the deposition takes place with the participation of a chemical reaction.
• a volatile gaseous component reacts with another gas to form a solid material that is deposited on the substrate.
• PECVD plasma enhanced chemical vapor deposition
• the gas phase reaction is triggered by thermal energy due to the heating of the substrate
• the PECVD process is based on the conversion of a gas into the plasma state in the vicinity of the substrate surface.
• One of the reaction products is a solid material that is deposited on the surface and thereby forms a new layer.
• the PECVD method and other plasma-based methods for example the plasma etching method
• other methods in which electrically charged particles occur for example ion beam etching
• the field effect transistor An important standard component in integrated circuits is the field effect transistor.
• Essential parameters for the functionality of a field effect transistor are the length and the material of the gate insulating layer, which is often formed as a silicon dioxide layer on a substrate.
• the gate insulating layer has the functionality of electrically decoupling the gate electrode from the conductive channel between the two source / drain regions of the field effect transistor. If you subject the gate insulating layer to one
• Amount of charge due to an electrical leakage current due to a damaged gate insulating layer leads to a loss of the stored information.
• Such a stress-induced leakage current is an example of an adverse effect based on damage to a gate insulating layer.
• the described damage to a gate-insulating layer or another functional layer of an integrated component can arise, for example, when electrical charge carriers are accumulated on an uncovered surface of a layer sequence during a plasma process and cause an electrical current flow through the layer due to a potential difference to the substrate , This can result in damage to the gate insulating layer or electrical breakdown of the gate insulating layer.
• Another known method for determining an electrical charge of an electrically chargeable structure on a substrate is based on the analysis of surface charges on a thick silicon dioxide layer (so-called “surface charge analysis”).
• a threshold voltage of a transistor is to be understood as the minimum voltage to be applied between the gate region and one of the source / drain regions, which is necessary for an electrical current that cannot be neglected to flow between the two source / drain regions of the transistor.
• a multiplicity of EEPROM memory cells are integrated into a wafer in the form of a matrix, as a result of which a so-called “CHARME” wafer is formed.
• Each of the EEPROM memory cells is coupled to a so-called “charge collection electrode” (CCE), that is to say a charge collection electrode for accumulating electrical charge carriers to be ascertained on the wafer surface.
• CCE charge collection electrode
• charge collecting electrode (clearly an antenna structure) is also applied to other standard integrated semiconductor components.
• the strength of the gate leakage current (“stress induced leakage current") is also recorded according to the prior art, this leakage current being greater the more electrical charge carriers in a associated gate-insulating layer are undesirably introduced.
• the known methods for determining an electrical charge of an electrically chargeable structure have a number of disadvantages.
• the results obtained using test structures are not readily transferable to real wafers because of the often special arrangement and dimension of the components can have an influence on local differences in plasma processes.
• the formation of antenna structures on test structures represents an intervention in the charging process and can therefore lead to artifacts.
• the spatial resolution of the charging of a substrate is impaired.
• the methods known from the prior art, in particular the "CHARME" wafer are complex and expensive to produce.
• [4] discloses a non-volatile memory structure with a protective structure to limit process-induced damage that can occur during a manufacturing process.
• [5] discloses a programmable read-only memory with a dielectric trapping layer, into which electrical charge carriers can be introduced, which trapping layer is arranged between two silicon oxide layers.
• [6] discloses an apparatus for determining the current density versus voltage characteristic of integrated circuit processing equipment such as a plasma etcher.
• [7] discloses a protective device with a protective transistor and an antenna that is active during a manufacturing process of a semiconductor chip.
• the invention is based on the problem of providing a determination arrangement for determining electrical charge carriers, with which a charge phenomenon in a substrate can be detected with reasonable effort and good spatial resolution.
• the problem is solved by a determination arrangement, by a method for determining electrical charge carriers and by using an ONO field-effect transistor for determining an electrical charge with the features according to the independent claims.
• the determination arrangement for determining electrical charge carriers has an ONO field effect transistor formed in or on a substrate, which is set up in such a way that the charge carriers to be determined can be introduced in the ONO layer sequence, and has a detection unit coupled to the ONO field effect transistor , which is set up in such a way that it detects an electrical signal that is characteristic of the quantity and / or the charge carrier type of the electrical charge carriers introduced in the ONO layer sequence, and has a determination unit for determining the quantity and / or the charge carrier type that is used in the ONO layer sequence introduced electrical charge carriers from the characteristic electrical signal.
• the substrate is subjected to a process step in which electrical charge carriers are introduced into the ONO layer sequence of the ONO field-effect transistor, in which the detection unit uses the the quantity and / or the charge carrier type of the electrical charge carriers characteristic in the ONO layers olge is detected and the quantity and / or the charge carriers type of those introduced in the ONO layer sequence by means of the determination unit electrical charge carrier is determined from the characteristic electrical signal.
• an ONO field-effect transistor is used according to the invention to determine the electrical charge of an electrically chargeable structure on and / or in a substrate.
• An ONO transistor is a field effect transistor in which the gate-insulating layer is designed as a layer sequence which is referred to as an ONO layer sequence.
• An ONO layer sequence consists of a first silicon dioxide layer, a silicon nitride layer on the first silicon dioxide layer and a second silicon dioxide layer on the silicon nitride layer.
• An ONO layer sequence has in particular the property that electrical charge carriers injected in the silicon nitride layer remain permanently in the silicon nitride layer, with these electrical charge carriers flowing away through one of the two silicon dioxide layers (at least in the absence of a strong electrical voltage) the electrically insulating property of the ONO layer sequence is avoided.
• a field effect transistor with an ONO layer sequence is used according to the invention to determine electrical charge carriers which are generated, for example, in a semiconductor technology process step. If, for example, electrical charge carriers are generated during a semiconductor technology process step (e.g. during a PECVD process), these charge carriers can be introduced into the ONO layer sequence in the inventive determination arrangement, more precisely into the silicon nitride layer of the ONO layer sequence.
• the physical processes on which the introduction of such charge carriers into a gate-insulating layer is based can be examined and quantified using the test structure according to the invention.
• the electrical properties of the ONO field-effect transistor, in particular its threshold voltage, clearly change as a result of the introduction of the electrical charge carriers into the ONO layer, the sign and value of the shift being a measure of the type of charge carrier of the electrical charge carriers of the charge carriers introduced into the ONO layer sequence or is a measure of the amount of charge carriers introduced therein.
• the shift in the threshold voltage of the ONO field-effect transistor is only mentioned here as an example of a possible characteristic electrical signal that can be detected in order to determine the electrical charge carriers in the ONO layer sequence.
• the detection unit of the determination arrangement is generally set up in such a way that it detects this characteristic electrical signal.
• the determination unit according to the invention determines the quantity or the charge carrier type of the electrical charge carriers to be determined from this characteristic electrical signal.
• an integrated field effect transistor with an oxide-nitride-oxide layer sequence is formed as a gate-insulating layer, that is to say with a layer sequence with a silicon nitride layer (Si 3 N 4 ) between two silicon dioxide layers (Si0 2 ).
• An ONO layer sequence can store electrical charge carriers locally. The electrical charge carriers are located in the electrically insulating silicon nitride layer of the ONO layer sequence.
• Electric charge carriers are usually introduced into the ONO layer sequence by means of tunneling electrical charge carriers through one of the silicon dioxide layers due to a sufficiently high energy of the charge carriers, for example due to high potential differences between the connections of the ON0 transistor or due to a high kinetic energy of the charge carriers.
• the presence of electrical charge carriers in the ONO layer influences the electrical properties of the transistor in a characteristic and detectable manner.
• Such a change in the electrical properties of the ONO field-effect transistor with a charged silicon nitride layer compared to an ONO field-effect transistor whose silicon nitride layer is free of charge carriers can be detected, for example, by applying a constant source-drain voltage and the electrical source - Drain current or its change is detected. If a predeterminable gate voltage is varied until a source-drain current no longer occurs, the threshold voltage of the ONO transistor or its shift as a result of the introduction of electrical charge carriers into the ONO layer sequence can be detected.
• the electrical charge carriers to be determined are introduced into the silicon nitride layer from the gate region via the upper silicon dioxide layer of the ONO layer sequence.
• the determination arrangement according to the invention has an arrangement for determination that is known from the prior art electrical charge carriers have a number of advantages.
• the determination arrangement according to the invention is inexpensive, in particular considerably less expensive than a "CHARME" wafer.
• the determination arrangement according to the invention offers the advantage that it is used to determine an electrical charge on a real substrate (for example a wafer) or on component structures.
• the use of the determination arrangement according to the invention allows a direct comparison between different process plants.
• An ONO layer sequence is charged during the processing of the substrate.
• an ONO field effect transistor of the inventive determination arrangement can be formed and its threshold voltage can be detected.
• Integrated components can then be formed on the first surface area of the substrate using a plasma process.
• the "stress" occurring in this process due to generated electrical charge carriers can be recorded by detecting the change in the threshold voltage of the ONO field-effect transistor by means of the inventive determination unit.
• the determination arrangement according to the invention is also not limited to plasma and ion beam processes, but rather enables the quantification of any electrical charge of an electronic component as a result of a process step.
• the determination arrangement according to the invention can at least partially be embodied as an integrated circuit.
• An ONO field effect transistor is therefore mature Semiconductor technology processes can be formed in very small dimensions down to the nanometer range. As a result of this small structural dimension, a high spatial resolution can be achieved when the charge phenomena are detected.
• charging of an electrical layer can be simulated on the basis of charging the ONO layer sequence of the determination arrangement of the invention on the basis of an externally applied sufficiently high voltage. It is therefore possible to calibrate the relationship between the amount of electrical charge carriers to be determined and a change in an electrical signal, for example a threshold voltage.
• the determination arrangement according to the invention it is possible to determine not only the quantity but also the type of charge carrier (i.e. positively or negatively electrically charged charge carriers) of the electrical charge carriers introduced in the ONO layer sequence.
• the type of charge carrier i.e. positively or negatively electrically charged charge carriers
• the ONO field-effect transistor according to the invention can be designed as a field-effect transistor of the n-line type or p-line type. Consequently, both electrons and holes can be the electrical charge carriers to be determined.
• the layer thicknesses of the determination arrangement furthermore in particular the individual layer thicknesses of the ONO layer sequence, are preferably adapted to the sign of the charge carriers to be determined or are adapted to the fact whether an n-FET or a p-FET is present.
• the thickness of the layer sequences is preferably set variably depending on the scenario, whether there are electrons or holes.
• Determination arrangement is used to determine the quantity and the type of charge carrier introduced in the ONO layer sequence electrical charge carrier as a characteristic electrical signal detected the shift in the threshold voltage of the ONO field transistor.
• the type of charge carrier can be determined depending on whether the threshold voltage shifts to a higher or a lower threshold voltage.
• an electrical voltage applied externally to the gate region of the ONO field effect transistor is either amplified or weakened, as a result of which the threshold voltage of the ONO field effect transistor increases or humiliated.
• a PECVD method is applied to a wafer with the determination arrangement formed thereon and / or therein, as a result of which, as a result of the plasma, electrical charge carriers enter the silicon nitride layer of the ONO layer sequence of the ONO field-effect transistor Investigation order can be introduced.
• the characteristic electrical signal which represents the threshold voltage of the ONO field-effect transistor, is shifted, and this shift is detected by magnitude and sign using the detection unit.
• the amount of the shift of the threshold voltage is characteristic of the quantity and the sign of the shift of the threshold voltage is characteristic of the charge carrier type of the electrical charge carriers introduced in the ONO layer sequence.
• the determination unit is used to determine the sign and amount of the shift of the
• the voltage of the charge carrier type and the amount of electrical charge carriers introduced in the ONO layer sequence are determined.
• the detection unit of the determination arrangement according to the invention can have a first detection subunit coupled to the two source / drain regions of the ONO transistor, which is set up in such a way that it can be used to set a first predeterminable voltage between the two source / drain - Connections of the ONO transistor can be applied, and that it detects the strength of an electrical current flow between the two source / drain regions.
• the latter has a second detection subunit coupled to the gate region of the ONO transistor, which is set up in such a way that it can be used to apply a second, predefinable electrical voltage to the gate region of the ONO transistor is.
• Detection subunit comprising detection unit, the dependence of the electrical source-drain current on the source-gate voltage can be detected.
• a transistor characteristic curve can clearly be recorded.
• the threshold voltage of the ONO field effect transistor or a shift in the threshold voltage can be detected.
• the electrical signal which is recorded by the detection unit and which is characteristic of the quantity and / or the charge carrier type of the electrical charge carriers introduced in the ONO layer sequence can change the threshold voltage of the ONO transistor as a result of the introduction of electrical charge carriers into the ONO Layer sequence.
• the two source / drain regions are preferably two in one Doped surface areas of the substrate arranged at a distance from one another, the ONO layer sequence is composed of a first silicon dioxide layer on the substrate between the two source / drain regions, a silicon nitride layer on the first silicon dioxide layer and a second silicon dioxide layer. Layer formed on the silicon nitride layer and the gate region is formed as an electrically conductive layer on the second silicon dioxide layer.
• the substrate can in particular be a silicon substrate and further in particular a p-doped or an n-doped silicon substrate. If the substrate is a p-doped silicon substrate, then the two source / drain regions are n-doped, and if the substrate is an n-doped silicon substrate, then the two source / drain regions are p-doped areas.
• the ONO field-effect transistor can be designed as a field-effect transistor of the n-type or the p-type.
• the determination arrangement can furthermore have a charge collecting electrode coupled via the gate region to the ONO layer sequence for accumulating electrical charge carriers to be determined.
• the charge collection electrode is an illustrative antenna structure, preferably arranged on the surface of the determination arrangement, which can accumulate electrical charge carriers to be determined and these via the gate region of the ONO field effect transistor can provide electrical charge carriers of the ONO layer sequence in such a way that the electrical charge carriers to be determined can be at least partially stored in the silicon nitride layer of the ONO layer sequence.
• the charge collecting electrode is preferably made of an electrically highly conductive material. If a charge collecting electrode is used, the detection sensitivity of the determination arrangement according to the invention can be increased. If, for example, charge carriers occur in a small amount that is difficult to detect in a process to be characterized, they can be accumulated by the charge collecting electrode, which can be formed over a sufficiently large area, and then made available to the ONO layer sequence. This is the
• the determination arrangement can have at least one reaction chamber, which is set up in such a way that a process step for processing the substrate can be carried out after the ONO field-effect transistor has been produced.
• reaction chambers can be used as plasma
• Reaction chambers and, in particular, be set up as a plasma etching chamber for carrying out a plasma etching process.
• the plasma reaction chamber can be set up as a plasma deposition chamber for carrying out a plasma deposition process.
• a layer on the surface of a substrate can be etched back or removed in the plasma etching process by forming a plasma in the plasma reaction chamber. From this plasma excited neutral atoms or molecules (radicals) can diffuse to the substrate and react chemically with atoms on the substrate surface. This leads to the removal or removal of a layer on the substrate if, as a result of the chemical reaction, volatile reaction products are formed which, for example, can be sucked off by a vacuum pump.
• electrical charge carriers can be in undesired areas of the Substrate (for example, in a gate insulating layer) are accumulated, such .electric charge carriers can be determined according to the invention.
• a layer is deposited on the surface of the substrate using plasma material, for example using the PECVD method, electrical charge carriers being able to occur in undesired areas, for example on the gate insulating layer a trained field effect transistor.
• plasma material for example using the PECVD method
• electrical charge carriers being able to occur in undesired areas, for example on the gate insulating layer a trained field effect transistor.
• the threshold voltage of the ONO field-effect transistor is detected as a characteristic ' 1 -o. ° ⁇ electrical signal, and becomes a
• Use voltage of the ONO field-effect transistor according to amount and sign to the amount and type of charge carrier of electrical charge carriers introduced, for example as a result of a plasma process, into the silicon nitride layer of an ONO layer sequence.
• a reference measurement can be carried out on a reference field effect transistor, ie on a field effect transistor that is not exposed to the electrical charge carriers, and its reference threshold voltage can be determined.
• the reference field effect transistor can be an ONO field effect transistor different from the ONO field effect transistor.
• the reference field effect transistor can also be the ONO field effect transistor itself, before the electrical charge carriers to be determined are introduced into it.
• Figure 1A shows a determination arrangement according to a preferred
• FIG. 1B shows an enlarged section of the determination arrangement shown in FIG. 1A
• FIG. 2 is a diagram which shows the dependence of the change in the threshold voltage of an ONO field-effect transistor of a determination arrangement on the stress voltage as a result of the action of electrical charge carriers on the ONO field-effect transistor.
• a determination arrangement 100 according to a preferred exemplary embodiment of the invention is described below with reference to FIGS. 1A, 1B.
• the determination arrangement 100 shown in FIG. 1A for determining electrical charge carriers has an ONO field-effect transistor formed in or on a silicon substrate 101, which is set up in such a way that in of the ONO layer sequence 102, the electrical charge carriers 103 to be determined can be introduced. According to the exemplary embodiment described, the electrical charge carriers 103 are positively (“+”) charged.
• the determination arrangement 100 furthermore has a coupling coupled to the ONO field effect transistor
• Detection unit 104 which is set up in such a way that it detects an electrical signal which is characteristic of the quantity and the charge carrier type (positive charge) of the electrical charge carriers 103 introduced in the ONO layer sequence 102. Furthermore, the determination arrangement 100 has a determination unit 105 for determining the quantity and the type of charge carrier of the electrical charge carriers 103 introduced in the ONO layer sequence 102 from the characteristic electrical signal.
• the detection unit 104 has a first detection subunit 104a, which is coupled to the two source / drain regions 106, 107 of the ONO field-effect transistor and is set up in such a way that it provides a first, predefinable voltage between the two source / drain Areas 106, 107 of the ONO field effect transistor can be applied, and that it detects the strength of an electrical current flow between the two source / drain areas 106, 107.
• the detection unit 104 also has a second detection subunit 104b, which is coupled to the gate region 108 of the ONO field-effect transistor and is set up in such a way that it can be used to apply a second predeterminable electrical voltage to the gate region 108 of the ONO field-effect transistor is.
• the first detection subunit 104a has a voltage source for providing the first voltage and an ammeter for detecting the
• the second detection subunit 104b has a voltage source with which a variable voltage can be applied to the gate region 108 of the ONO field-effect transistor.
• the quantity and charge carrier type that is detected by the detection unit 104 is that in the ONO layer sequence 102 introduced electrical charge carrier 103 characteristic electrical signal a change in the threshold voltage of the ONO transistor due to the introduction of electrical charge carriers 103 in the ONO layer sequence 102.
• the detection unit 104 it is possible to create a transistor characteristic curve, that is to say the dependence on the size of the source-drain current to detect the size of the gate-source voltage and therefore to detect the threshold voltage of the ONO field effect transistor.
• the two source / drain regions 106, 107 are designed as two doped surface regions of the silicon substrate 101 arranged at a distance from one another.
• the ONO layer sequence 102 is composed of a first silicon dioxide layer 102a, applied to the silicon substrate 101 between the two source / drain regions 106, 107, a silicon nitride layer 102b applied to the first silicon dioxide layer 102a, and one formed on the silicon nitride layer 102b second silicon dioxide layer 102c.
• the structure of a partial area 150 of the ONO layer sequence 102 is shown in FIG. 1B as an enlarged view.
• the thickness di of the first silicon dioxide layer 102a is 10.5 nm
• the thickness of the silicon nitride layer 102 b d is 7 nm
• the thickness of the second silicon dioxide layer 102 c d 3 is 8 nm. It should be noted that the illustration in FIGS. 1A, 1B is not to scale.
• the layer thicknesses are preferably set depending on whether electrons or holes are present as charge carriers to be determined in accordance with a present scenario.
• the gate region 108 of the ONO field effect transistor is formed as an electrically conductive layer made of polycrystalline silicon on the second silicon dioxide layer 102c. Furthermore, the determination arrangement 100 has a charge collecting electrode 109 coupled via the gate region 108 to the ONO layer sequence 102 for accumulating electrical charge carriers 103 to be determined.
• the surface area of the charge collection electrode 109 is larger than the corresponding surface of the gate area 108, so that an increased amount of electrical charge carriers, which are produced, for example, in a plasma process, are clearly accumulated on the charge collection electrode 109 and are provided via the gate region 108 of the ONO layer sequence 102 than in the case of an arrangement which does not have a charge collecting electrode 109.
• the larger surface area of the charge collection electrode 109 compared to the surface area of the gate electrode 108 results from the increased horizontal extension l ⁇ of the charge collection electrode 109 according to FIG. 1A compared to the horizontal extension 1 2 of the gate electrode 108.
• Arrows 110 shown in Fig. 1A illustrate how a plasma process (e.g., a PECVD-
• the thickness di of the first silicon dioxide layer 102a on the silicon substrate 101 is selected to be substantially larger at 10.5 nm than the thickness of the third
• Silicon dioxide layer 102c d 3 8nm.
• the electrical charge carriers to be determined according to FIG. 1A are introduced from above, that is to say from the gate electrode 108 through the third silicon dioxide layer 102c into the silicon nitride layer 102b as a result of the quantum mechanical tunnel effect.
• the tunnel current of electrical charge carriers through an electrically insulating layer decreases approximately exponentially with the thickness of the layer.
• the thicknesses di, d 3 are set such that a tunneling of charge carriers is only possible from above according to FIG.
• a method for determining the electrical charge carriers with the determining arrangement 100 is described below with reference to the determining arrangement 100.
• the silicon substrate 101 is subjected to a PECVD process step in which the electrical charge carriers 103 are introduced into the ONO layer sequence 102, more precisely into the silicon nitride layer 102b of the ONO layer sequence 102. Furthermore, the detection unit 104 detects the electrical signal which is characteristic of the quantity and the charge carrier type of the electrical charge carriers 103 introduced into the ONO layer sequence 102. According to the exemplary embodiment described, the shift in the threshold voltage of the ONO field-effect transistor is determined as a characteristic electrical signal using the detection unit 104.
• the threshold voltage of a field effect transistor is the minimum potential difference that must be applied between a source / drain region and the gate region of the transistor in order to have a given potential difference between the two source / drain regions 106, 107 to cause electrical current flow between the two source / drain regions 106, 107.
• a constant first electrical voltage is applied between the two source / drain regions 106, 107 by means of the first detection subunit 104a.
• a changeable second electrical voltage is applied to the gate region 108 by means of the second detection subunit 104b.
• Ammeter of the first detection subunit 104a is the strength of a possible electrical current flow between the two source / drain regions 106, 107 are determined.
• first electrical voltage the electrical current between the two source / drain regions 106, 107 becomes dependent on the changed second voltage at the gate region (that is, depending on a variable gate-source voltage).
• the threshold voltage of the ONO field-effect transistor is therefore recorded as a characteristic electrical signal. More specifically, a change in the threshold voltage of the ONO field-effect transistor is determined, based on an electrically uncharged reference field-effect transistor.
• the threshold voltage of the ONO field-effect transistor of the determination arrangement 100 is initially detected in a scenario that deviates from FIG. 1A, in which the ONO layer sequence 102 is free of electrical charge carriers 103 (reference threshold voltage). Then, according to the scenario shown in Fig.la, the threshold voltage of the ONO-
• Determination unit 105 determines the quantity and the charge carrier type of the electrical charge carriers 103 introduced in the ONO layer sequence 102. This functionality can consist, for example, in that the determination unit detects a table of values contained therein
• Assignment voltage shift assigns a charge quantity.
• a table of values can be obtained, for example, from a previous calibration.
• the text below describes how the charge voltage of the ONO layer can be made by introducing electrical charge carriers into the silicon nitride layer 102b of the ONO layer sequence 102.
• Field effect transistor is changed. 1A, positively charged electrical charge carriers from a plasma process are directed onto the charge collecting electrode 109, these electrical charge carriers 109 being provided by the charge collecting electrode 109 to the gate region 108.
• electrically positive charge carriers 103 are built into the silicon nitride layer 102b, as shown in FIG. 1A, FIG. IB.
• the positively charged charge carriers 103 in the silicon nitride layer 102b have the same effect as a positive gate voltage at the gate electrode 109. This means that the positively charged electrical charge carriers 103 generate an electric field like a positive gate bias which characteristically changes the conductivity of the channel region 111.
• the transistor is changed by a contribution generated by the electrical charge carriers 103, depending on the quantity and the sign of the charge carriers. Then, the second detection subunit 104b must apply an electrical voltage changed by this contribution to the gate region 106 in order to make the n-MOS transistor conductive.
• the electrical charge carriers 103 produce (depending on the sign of the charge carrier type electrical charge) a positive or negative shielding effect, i.e. an amplification or attenuation of the electric field generated by a voltage externally applied to the gate region.
• the ONO field effect transistor is clearly biased due to the charge carriers 103.
• the electrons in the silicon nitride layer 102b of the ONO layer sequence 102 generate an electric field with compared to the scenario described above ( Holes in the ONO layer sequence) opposite signs.
• a positive voltage is applied to the gate area, weakened the electric field of the electrons.
• the negative bias voltage generated by the electrons partially compensates for the external positive gate voltage in its effect on the conductivity of the channel region, so that a depletion of charge carriers in the
• Channel area is the result.
• the electrical field generated by the external voltage is weakened by this shielding effect. This results in a characteristic change in the threshold voltage.
• a second electrical voltage increased by a corresponding contribution is to be applied from the second detection subunit 104b to the gate region 108 in order to bring the channel region 111 between the two source / drain regions 106, 107 into a conductive state.
• the threshold voltage is negatively charged due to the introduction
• Charge carriers in the ONO layer sequence 102 are increased. In this way, an increase or a decrease in the threshold voltage can be clearly associated with the sign of the electrical charge of the electrical charge carriers 103.
• the diagram 200 shown in FIG. 2 shows the change in the threshold voltage of an ONO field effect transistor ⁇ V th (in volts) as a function of a “stress voltage” V s (in volts), as was obtained for an ONO field effect transistor .
• the stress voltage V s is the electrical voltage due to the introduction of electrical charge carriers in the ONO layer sequence. Such charge carriers have the same physical effect as an additional voltage which is applied to the gate region of the ONO field-effect transistor.
• FIG. 2 shows a first curve 201 which was obtained from a connection of data points 202. Furthermore, a second curve 203 is shown in FIG. 2, which was obtained from a connection of data points 204.

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