Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
  • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
  • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L21/8232—Field-effect technology
  • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
  • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
  • H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
  • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
  • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L21/8232—Field-effect technology
  • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
  • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Definitions

• the present invention relates to the field of fabrication of integrated circuits, and, more particularly, to semiconductor devices having metal-silicide portions on semiconductor regions to reduce the sheet resistance of the semiconductor regions. Furthermore, the present invention relates to a method of manufacturing these semiconductor devices.
• CD critical dimension
• the individual semiconductor devices such as field effect transistors, capacitors and the like, are primarily based on silicon, wherein the individual devices are connected by silicon lines and metal lines. While the resistivity of the metal lines may be improved by replacing the commonly used aluminium by, for example, copper, process engineers are confronted with a challenging task when an improvement in the electrical characteristics of silicon- containing semiconductor lines and semiconductor contact regions is required.
• a semiconductor structure 100 includes a substrate 101, for example, a silicon substrate, in which a first semiconductor element 110 and a second semiconductor element 130 are formed.
• the first semiconductor element 110 may, as depicted in Figure la, represent a field effect transistor of a first conductivity type, such as an n-channel transistor, and the second semiconductor element 130 may represent a field effect transistor of a second conductivity type, such as a p-channel transistor.
• the first semiconductor element 110 comprises shallow trench isolations (STI) 113 that are formed of an insulated material, such as silicon dioxide, and that define an active region 112 in the substrate 101.
• a gate electrode 115 is formed over a gate insulation layer 118 that separates the gate electrode 115 from the active region 112.
• Spacer elements 116 made of, for example, silicon dioxide or silicon nitride, are located at the sidewalk of the gate electrode 115.
• source and drain regions 114 are formed and exhibit an appropriate dopant profile required to connect to a conductive channel that builds up between the drain and the source region during operation of the first semiconductor element 110.
• the second semiconductor element 130 comprises substantially the same parts as the first semiconductor element 110 and corresponding parts are denoted by the same reference numerals except for a "leading 13" instead of a "leading 11.”
• the second semiconductor element 130 may differ from the first semiconductor element 110 in, for example, type of conductivity, that is, type and concentration of dopants provided in the active regions 112 and 132, lateral extension of the gate electrode, also referred to as gate length, cross-sectional area, and the like.
• the first and second semiconductor elements 110 and 130 in Figs, la and lb are depicted as transistor elements, the first and second semiconductor elements 110 and 130 may represent any silicon-containing region that is used for charge carrier transportation.
• relatively long polysilicon lines may connect semiconductor elements on different locations of a single chip area and these polysilicon lines may be regarded as first and second semiconductor elements 110, 130, the electrical characteristics of which are to be improved so as to obtain an enhanced device performance with respect to signal propagation delay.
• the gate length of the first and second semiconductor elements 110 and 130 determines the channel length of these devices and, therefore, as previously pointed out, significantly affects the electrical characteristics of the first and second semiconductor elements 110 and 130, whereby a reduced gate length will result in an increased resistance of the gate electrodes 115, 135 owing to the reduction of the cross-sectional area of the gate electrodes 115, 135.
• a typical process flow for forming the semiconductor structure 100 may comprise the following steps. After formation of the shallow trench isolations 113 and 133 by well-known photolithography techniques, implantation steps are performed to create a required dopant concentration in the active regions 112 and 132. Subsequently, the gate insulation layers 118 and 138 are formed according to design requirements. Thereafter, the gate electrodes 115 and 135 are formed by patterning, for instance a polysilicon layer, by means of sophisticated photolithography and trim etch methods. Then, a further implantation step for forming so-called source and drain extensions within the source and drain regions 114 and 134 is performed and the spacer elements 116 and 126 are formed by deposition and anisotropic etching techniques.
• the spacer elements 116 and 126 are used as an implantation mask for a subsequent implantation step in which dopant particles are implanted into the source and drain regions 114 and 134 to create the required high dopant concentrations in those regions. It is to be noted that the dopant concentration varies in Figure la in the horizontal direction, i.e., in the length direction of the gate electrodes 115, 135, as well as in the vertical direction, which will hereinafter be referred to as depth direction.
• the dopant profile of the source and drain regions 114 and 134 is depicted as a region having a sharp boundary, in reality the dopant profile varies continuously due to the nature of the implantation process and the subsequent annealing steps that are performed for activating the implanted atoms and for curing the crystalline damage caused by the implantation step.
• the dopant profile has to be selected in conformity with other parameters of the first and second semiconductor elements 110 and 130.
• a short gate length and thus a short channel length, requires a "shallow" dopant profile in order to avoid the so-called “short channel effect.”
• the peak concentration in the depth direction may be located a few hundred nanometers below the surface of the drain and source regions 114 and 134.
• p-channel transistors may require a different dopant profile than an n-channel transistor element.
• a metal layer 140 is deposited over the first and second semiconductor elements 110 and .130.
• the metal layer 140 comprises titanium, cobalt or other refractory metals.
• a first heat treatment for example, a rapid thermal annealing, is carried out to initiate a chemical reaction between the silicon in the source and drain regions 114, 134, the gate electrodes 115,
• an average temperature of the first heat treatment may be set to about 400°C to create a meta-stable cobalt silicon compound exhibiting a relatively high resistivity. Since the silicon contained in the spacer elements 116,
• the metal of the metal layer 140 does not substantially react with the material of the spacer element 115, 136 and the shallow trench isolations 113, 133.
• the material of the metal layer 140 that has not reacted with the underlying material is removed by, for example, a selective wet etching process.
• a second heat treatment is performed, for example, a second rapid annealing step with a temperature higher than in the first annealing step, to convert the meta-stable metal-silicon compound into a metal suicide.
• a cobalt disilicide is formed in the second annealing step.
• the metal suicide shows a significantly lower resistance than the meta-stable metal-silicon compound as well as a significantly lower resistance, by a factor of about 5-10, than the sheet resistance of the doped polysilicon.
• Figure lb schematically shows the finally obtained first and second semiconductor elements 110 and 130 having formed on the respective source and drain regions 114, 134 and the gate electrodes 115, 135 a metal suicide region 141.
• the metal suicide regions 141 significantly improve the electrical characteristics of the first and second semiconductor elements 110 and 130, there is still room for improvement since, in the conventional process flow, the metal suicide regions 141 have to be formed so as to meet the requirements of the first semiconductor element 110 and the second semiconductor element 130, so that optimizing the characteristics of the suicide regions 141 of the first semiconductor element 110 compromises the effect of the suicide regions 141 of the second semiconductor element 130, and vice verse. It is thus desirable to have a semiconductor and a method of forming the same in which the characteristics of the conductive semiconductor regions may be individually optimized for different semiconductor elements.
• the present invention is directed to a method that may solve, or at least reduce, some or all of the aforementioned problems.
• the present invention is generally related to a method of manufacturing a semiconductor device in which silicon-containing regions receive a metal suicide portion to enhance the electrical properties of these regions, wherein the type of material and or a thickness of the metal suicide portion is individually adjusted to meet the requirements of different semiconductor regions in view of the electrical resistance.
• a method of forming a semiconductor device comprises providing a substrate having formed thereon a first and a second conductive silicon-containing region and forming a first resist mask for covering a second conductive silicon-containing region while exposing the first conductive silicon-containing region. Moreover, a first metal layer of a predefined thickness is deposited over the substrate and the first resist mask is removed. Furthermore, the method includes forming a second resist mask for covering the first conductive silicon-containing region and exposing the second conductive silicon- containing region. Thereafter, a second metal layer of a second predefined thickness is deposited over the substrate and then the second resist mask is removed. Additionally, the method includes a heat treatment of the substrate to form a first suicide layer on the first conductive silicon-containing region and a second suicide layer on the second conductive silicon-containing region.
• a method of forming a semiconductor device comprises forming a plurality of conductive silicon-containing regions on a substrate. Thereafter, a plurality of different metal layers are sequentially deposited on the substrate using a deposition mask such that each of the plurality of conductive silicon-containing regions is covered by substantially a single metal layer, wherein the metal layers differ from each other by their type of material and/or their layer thickness.
• the method further comprises annealing the substrate at a first average temperature for a first time interval to form a metal silicon compound on each of the conductive silicon-containing regions and selectively removing excess metal from the substrate.
• the method includes annealing the substrate at a second average temperature for a second time interval to convert the metal silicon compound into a metal suicide portion, wherein at least one of the first and second average temperatures and the first and second time intervals are controlled to adjust a thickness of the metal suicide portions.
• a semiconductor device comprises at least one first conducive silicon-containing region and at least one second conductive silicon-containing region, wherein the first and second conductive silicon-containing regions are formed in a common layer. Moreover, the semiconductor device comprises a first metal suicide portion formed on the first conductive silicon-containing region and a second metal suicide portion formed in the second conductive silicon-containing region, wherein at least one of the first and second metal suicide portions contains a noble metal.
• Figures la and lb show schematic cross-sectional views of a first and second semiconductor element having a suicide portion formed in conductive areas, wherein the first and second semiconductor elements are manufactured in accordance with a typical prior art process;
• FIGS. 2a-2f schematically show cross-sectional views of a semiconductor structure during various manufacturing stages, which is formed in accordance with one illustrative embodiment of the present invention.
• two or more different conductive silicon-containing regions receive a suicide portion, the type of material and/or the thickness of which are correspondingly designed to improve the electrical conductivity of these regions.
• a suicide portion the type of material and/or the thickness of which are correspondingly designed to improve the electrical conductivity of these regions.
• different suicide portions are formed on these silicon lines to improve the overall characteristics and to substantially compensate for the different cross-sectional areas.
• the present invention also allows one to appropriately form corresponding suicide portions in the devices to individually optimize the performance of the devices.
• short channel devices generally require a different type of suicide portion than do long channel devices since, for example, in long channel devices the peak dopant concentration is located more deeply in the drain and source regions than in short channel devices which require relatively shallow junctions.
• a semiconductor structure 200 comprises a substrate 201, for example, a silicon substrate or any other substrate appropriate for the formation of semiconductor elements.
• a first semiconductor element 210 comprises an active region 212 defined by shallow trench isolations 213.
• a gate electrode 215 is separated from the active region 212 by a gate insulation layer 218.
• Spacer elements 216 of an insulating material, such as silicon dioxide or silicon nitride, are formed adjacent to the sidewalls of the gate electrode 215.
• source and drain regions 214 are formed in the active region 212.
• the semiconductor structure 200 further includes a second semiconductor element 230 comprising substantially the same components as the first semiconductor element 210.
• a second semiconductor element 230 comprising substantially the same components as the first semiconductor element 210.
• corresponding parts are denoted by the same reference numerals except for a leading "23" in stead of a leading "21.”
• the first and the second semiconductor elements 210 and 230 differ from each other in the sense as pointed out above.
• a resist mask 250 is formed on the second semiconductor element 230.
• a typical process flow for forming the semiconductor structure 200 may be quite similar to the processing as described with reference to Figures la and lb and, thus, the description of these process steps is omitted.
• the resist mask 250 may be formed by means of conventional photolithography wherein, however, any overlay considerations are of no great concern since the precise location of the resist mask 250 on the shallow trench isolations 233 is not critical.
• Figure 2b schematically shows the semiconductor structure 200 with a first metal layer 240 deposited, over the semiconductor structure 200.
• the first metal layer 240 may comprise any refractory metal or compound of metals that is suitable to provide for the required characteristics of the metal suicide to be formed in the silicon-containing regions 214 and .215. Suitable metals may include cobalt, titanium, nickel, tungsten and combinations thereof. In one particular. embodiment, the first metal layer 240 may comprise a noble metal such as platinum, palladium, gold and the like.
• a thickness of the first metal layer 240 and the composition thereof is selected such that in a subsequent annealing step an interdiffusing of silicon and metal atoms takes place and a metal suicide portion may form having a required penetration depth, i.e., a required thickness, and a required barrier height to yield a minimum transition resistance for the charge carriers.
• a cobalt layer may be deposited with a thickness of 30 to 80 nm.
• the first metal layer 240 covers a surface of the resist mask 250, whereas sidewall portions 252 of the resist mask 250 remain substantially uncovered.
• a deposition technique may be employed that allows one to minimize the coverage of the sidewall portions 252 with metal.
• PVD physical vapor deposition
• sputter deposition a physical vapor deposition technique
• process parameters are adjusted so that atoms and ions sputtered off of a target hit the semiconductor structure 200 in a substantially perpendicular direction. Consequently, the deposition of the first metal layer 240 at the sidewall portions 252 is minimized.
• Hitting the semiconductor structure 200 substantially perpendicularly may be obtained by using a collimator in the sputter deposition chamber in the vicinity of the substrate 201 to "guide" the ions and atoms approaching the substrate 201.
• the required directionality of the incoming ions and atoms may also be obtained by adjusting the magnetic and electrical fields within the sputter deposition chamber to obtain a minimal step coverage.
• Figure 2c schematically shows the semiconductor structure 200 with the resist mask 250 and the overlaying first metal layer 240 removed.
• Removing the resist mask 250 and, thus, portions of the first metal layer 240 over the second semiconductor element 230 may be achieved by a selective wet etching process using a chemical agent having a significantly higher etch rate for the resist mask 250 than for the first metal layer 240.
• the predefined thickness of the initially deposited first metal layer 240 may accordingly be selected so that in the subsequent etching process the thickness of the first metal layer 240 over the first semiconductor element 210 does not remain under a required minimum thickness.
• the initial layer thickness is selected to about 10 nm thicker than at least that required for forming a metal suicide meeting the design requirements.
• the resist mask 250 can be removed, although at a prolonged etching time because the metal layer thickness at the sidewall portions is considerably smaller than the thickness of the first metal layer 240 at substantially horizontal surface portions of the substrate 201. Typically, the metal layer thickness at the sidewall portions 252 will not exceed about 10% of the horizontal surface portions.
• the first semiconductor element 210 receives a first metal layer 240 that is configured to provide for the required characteristics of a suicide portion to be formed.
• a second photoresist mask 255 is formed over the first semiconductor element 210 and a second metal layer 242 is blanket-deposited over the semiconductor structure 200.
• the same criteria apply here as pointed out with reference to the photoresist mask 250.
• the same is true for the deposition- method for forming the second metal layer 242.
• sidewall portions 257 of the second photoresist mask 255 are substantially uncovered or at least significantly less covered by metal than the surface portions of the semiconductor substrate 200.
• the composition and the thickness of the second metal layer 242 the same criteria as given above apply in this case.
• a plurality of different semiconductor elements may be provided, wherein in subsequent masking steps in each of the plurality of semiconductor elements a different metal layer is deposited.
• a further resist mask (not shown) may be provided, wherein the resist masks 250, 255 and the further resist mask are designed such that a third metal layer may be deposited on a third semiconductor element (not shown).
• This masking sequence may be repeated with suitably designed masks so that a plurality of different metal layers may be deposited on a corresponding plurality of different types of semiconductor elements that are individually optimized to provide for the required suicide portions in these semiconductor elements.
• Figure 2e schematically shows the first and second semiconductor elements 210 and 230 having the first metal layer 240 and the second metal layer 242, respectively.
• the first and second metal layers 240 and 242 comprise a material and exhibit a thickness, both of which are targeted, when transformed into a metal suicide, to optimize the characteristics of the first and second semiconductor elements 210, 230.
• the first metal layer 240 and/or the second metal layer 242 may comprise at least one noble metal.
• a heat treatment is performed, for example, a rapid thermal annealing step, to initiate the chemical reaction between the metal in the first and second metal layers 240, 242 and the silicon contained in the regions 214, 234 and 215, 235.
• a heat treatment is performed, for example, a rapid thermal annealing step, to initiate the chemical reaction between the metal in the first and second metal layers 240, 242 and the silicon contained in the regions 214, 234 and 215, 235.
• diffusion of the atoms of the regions 214, 234, 215, 235 and of the atoms of the first and second metal layers 240, 242 takes place so that a continuous reaction between the silicon and the metal is maintained.
• the degree of diffusion, and thus of metal-silicon compound depends on the type of material, the temperature and the duration of the annealing process.
• the thickness of the metal-silicon compound may be partially adjusted by controlling the first average temperature and the first time interval. Subsequently, excess metal from the surface of the semiconductor structure 200 is removed and a second rapid thermal annealing step may be performed with a second temperature for a second time interval. Typically, the second average temperature is higher than the first temperature to obtain a stable metal suicide having a relatively low electrical resistance. The second average temperature and the second time interval may be controlled to obtain the required sheet resistance in each of the regions 214, 215, 234, 235.
• the sheet resistance in the first and second semiconductor elements 210 and 230 may nevertheless be individually adjusted in a common heat treatment since the reaction characteristics of the materials comprising the first and second metal layers 240, 242 are well known and may be selected to yield the desired sheet resistance.
• the excess metal of the first and second metal layers 240, 242 may be removed by a selective etch process, wherein advantageously metal and metal compounds do not need to be selectively removable with respect to each other.
• the non-reacted metal of the first and the second metal layer 240, 242 may be removed in a common etching process.
• no additional heat treatment compared to the previously described conventional processing, is required and, thus, a "thermal budget" is not incurred.
• Figure 2f schematically shows the finally-obtained semiconductor structure 200, wherein the first semiconductor element 210 comprises first suicide portions 241, the composition and/or the. thicknesses of which are adapted to provide for the required sheet resistance in the silicon-containing semiconductor regions 214 and 215.
• the second semiconductor element 230 comprises second suicide portions 243 adapted to meet the specific requirements of the second semiconductor element 230.
• the first suicide portions 241 and/or the second suicide portions 243 may comprise a noble metal such as platinum, palladium, gold and the like, in combination with refractory metals such as cobalt, titanium, zirconium, tungsten and the like.
• the thickness of the first and second suicide portions 241, 243 that is the degree of "penetration" of the suicide in the depth direction into the region 214, 215, 234 and 235, is adjusted to obtain the required sheet resistance.
• the first semiconductor element represents a p-channel transistor in which the peak concentration of p-type dopants is located at a depth of approximately 200 nm
• the thickness, i.e., the penetration, of the suicide portion may be adjusted to about 180-220 nm. Similar considerations apply to an n-channel transistor, which generally exhibits a shallow dopant profile.

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• Insulated Gate Type Field-Effect Transistor (AREA)
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• 2002
  • 2002-12-20 JP JP2003577322A patent/JP2005520341A/ja active Pending
  • 2002-12-20 WO PCT/US2002/041089 patent/WO2003079424A1/en active Application Filing
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