TW200303603A - Semiconductor device having different metal silicide portions and method for fabricating the semiconductor device - Google Patents
Semiconductor device having different metal silicide portions and method for fabricating the semiconductor device Download PDFInfo
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- TW200303603A TW200303603A TW92104156A TW92104156A TW200303603A TW 200303603 A TW200303603 A TW 200303603A TW 92104156 A TW92104156 A TW 92104156A TW 92104156 A TW92104156 A TW 92104156A TW 200303603 A TW200303603 A TW 200303603A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 127
- 239000002184 metal Substances 0.000 title claims abstract description 127
- 239000004065 semiconductor Substances 0.000 title claims abstract description 103
- 238000000034 method Methods 0.000 title claims abstract description 64
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 59
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 58
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 75
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 75
- 239000010703 silicon Substances 0.000 claims abstract description 75
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 38
- 239000000463 material Substances 0.000 claims description 22
- 239000002019 doping agent Substances 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 16
- 230000008569 process Effects 0.000 claims description 16
- 238000000137 annealing Methods 0.000 claims description 13
- 230000008021 deposition Effects 0.000 claims description 7
- 230000005669 field effect Effects 0.000 claims description 7
- 239000003795 chemical substances by application Substances 0.000 claims description 6
- 239000010970 precious metal Substances 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000004575 stone Substances 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 2
- 230000035699 permeability Effects 0.000 claims description 2
- 239000002923 metal particle Substances 0.000 claims 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims 4
- 238000001465 metallisation Methods 0.000 claims 2
- 229910052763 palladium Inorganic materials 0.000 claims 2
- 229910052697 platinum Inorganic materials 0.000 claims 2
- 238000007740 vapor deposition Methods 0.000 claims 2
- 241000238631 Hexapoda Species 0.000 claims 1
- 238000001312 dry etching Methods 0.000 claims 1
- 230000001568 sexual effect Effects 0.000 claims 1
- 150000002739 metals Chemical class 0.000 abstract description 6
- 229910000510 noble metal Inorganic materials 0.000 abstract 1
- 125000006850 spacer group Chemical group 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000002513 implantation Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000004151 rapid thermal annealing Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 239000002800 charge carrier Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 150000003377 silicon compounds Chemical class 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 150000002736 metal compounds Chemical class 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- -1 silicon Chemical compound 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000013043 chemical agent Substances 0.000 description 1
- AIOWANYIHSOXQY-UHFFFAOYSA-N cobalt silicon Chemical class [Si].[Co] AIOWANYIHSOXQY-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000010433 feldspar Substances 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000005871 repellent Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
200303603 鬌 ，五、發明說明（1) [發明所屬之技術領域] 一般而言，本發明係關於積體電路之製造領域，而且 _更特別地，關於具有於半導體區域上金屬矽合物部份以降 低半導體區域之薄層電阻的半導體裝置。更者，本發明係 彌於一種製造這些半導體裝置的方法。 [先前技術] 在現代超高密度的積體電路中，裝置零件不斷地縮 小，以提高裝置性能與功能。不管怎樣，使零件尺寸縮小 會承擔著某些問題，該些問題可能抵銷部份縮小零件尺寸 德得到的優點。一般而言，縮小例如電晶體元件的零件 尺寸，其係導致電晶體元件的降低通道電阻5並且從而導 致該電晶體之較高的驅動電流能力以及提高的切換速度。 不過5縮小這些電晶體元件的特徵尺寸時導線與接觸區域 亦即提供導電到電晶體元件周邊的區域所增加的電阻，會 S為這些導線及接觸區域的截面積會隨零件尺寸縮小而減 少而變成一嚴重問題。然而截面面積結合包含導線與接觸 區域之材料的特性，其乃決定各導線或者接觸區域的電 阻。 以上問題可是用於此態樣中一典型關鍵零件尺寸的例 子_亦稱為臨界規格（CD) ’譬如在電晶體的源極區域與 汲極區域之間之閘電極下方形成場效電晶體之通道的延長 部份。減少此通道的延長部份，一般稱為通道長度，其係 可能因為閘電極與通道之間的較小電容值以及因為較短通 道的降低電阻值，而明顯地改善電晶體元件中與升降次數200303603 鬌, V. Description of the invention (1) [Technical field to which the invention belongs] Generally speaking, the present invention relates to the field of manufacturing integrated circuits, and more specifically, to having a metal silicide portion on a semiconductor region A semiconductor device for reducing the sheet resistance of a semiconductor region. Furthermore, the present invention relates to a method for manufacturing these semiconductor devices. [Previous technology] In modern ultra-high-density integrated circuits, device parts are continuously shrinking to improve device performance and functionality. In any case, reducing the size of the part will bear some problems, which may offset some of the advantages of reducing the size of the part. In general, reducing the size of parts such as transistor elements results in a reduction of the channel resistance 5 of the transistor element and thus the higher drive current capability and increased switching speed of the transistor. However, when reducing the characteristic size of these transistor components, the increased resistance of the wires and contact areas that provide conduction to the area around the transistor components will increase the cross-sectional area of these wires and contact areas as the part size decreases. Becomes a serious problem. However, the cross-sectional area, combined with the characteristics of the material including the wires and contact areas, determines the resistance of each wire or contact area. The above question is an example of the size of a typical key part in this aspect. Also known as the critical specification (CD) 'For example, a field effect transistor is formed under the gate electrode between the source region and the drain region of the transistor. The extension of the channel. Reducing the extension of this channel, generally referred to as the channel length, may be due to the smaller capacitance value between the gate electrode and the channel and the lower resistance value of the shorter channel, which significantly improves the number of rises and falls in the transistor element.
92308.ptd 第6頁 200303603 五、發明說明（2) 有關的裝置性能。不過，通道長度之縮短同樣需要任何導 線尺寸的縮短’譬如一般由多晶發形成之場效電晶體的閘 電極，以及用於電性接觸電晶體之汲極與源極區域之接觸 區域，以便因而將用於電荷載體輸送的有效截面縮小。結 果，除非縮小的截面藉由改善形成線與接觸區域，譬如閘 電極、以及汲極與源極接觸區域之材料的電性特徵而受到 補償，不然的話導線與接觸區域會呈現出一較高的電阻 值。 因此改善大致上包含如矽的半導體材料在導電區域上 的特性乃特別地重要，例如，在現代的積體電路中，個別 的半導體裝置，譬如之主要以矽為基礎之場效電晶體、電 容器、以及類似物，每一裝置皆係由矽線與金屬線所導 接。雖然金屬線的電阻率可藉著以例如銅來取代一般所使 用的鋁而改善，但是當需要改善含矽半導體線與半導體接 觸區域的電性特徵時，製程工程師仍會面臨到一挑戰性的 任務。 參考第1 a圖與第1 b圖，現將說明製造包含例如複數個 M0S (金屬-氧化物-半導體）電晶體之積體電路的示範性 製程，以便更詳細地說明在改善含矽半導體區域之電性特 徵上所包含的諸問題。 在第1 a圖中，半導體結構1 0 0包括一基板1 0 1，例如一 矽基板，其中形成有一第一半導體元件110與一第二半導 體元件1 3 0。如第1 a圖所描述的，第一半導體元件1 1 0可能 代表一第一導電型態的一場效電晶體，譬如一 η-通道電晶92308.ptd Page 6 200303603 V. Description of the invention (2) Relevant device performance. However, the shortening of the channel length also requires the shortening of any wire size, such as the gate electrode of a field effect transistor generally formed by polycrystalline silicon, and the contact area between the drain and source regions for electrically contacting the transistor in order to The effective cross-section for charge carrier transport is thus reduced. As a result, unless the reduced cross-section is compensated by improving the electrical characteristics of the materials forming the line and contact areas, such as the gate electrode and the drain and source contact areas, otherwise the wires and contact areas will exhibit a higher resistance. Therefore, it is particularly important to improve the characteristics of semiconductor materials containing silicon, such as silicon, in the conductive region. For example, in modern integrated circuits, individual semiconductor devices, such as field-effect transistors and capacitors mainly based on silicon, , And the like, each device is connected by a silicon wire and a metal wire. Although the resistivity of metal lines can be improved by replacing copper, which is commonly used, with copper, for example, when it is necessary to improve the electrical characteristics of silicon-containing semiconductor lines and semiconductor contact areas, process engineers still face a challenging task. Referring to FIGS. 1a and 1b, an exemplary process for manufacturing an integrated circuit including, for example, a plurality of MOS (metal-oxide-semiconductor) transistors will now be described in order to explain in more detail the improvement of a silicon-containing semiconductor region. The problems involved in the electrical characteristics. In FIG. 1a, the semiconductor structure 100 includes a substrate 101, such as a silicon substrate, in which a first semiconductor element 110 and a second semiconductor element 130 are formed. As described in Figure 1a, the first semiconductor element 1 1 0 may represent a field-effect transistor of a first conductivity type, such as an η-channel transistor.
92308.ptd 第7頁 200303603 鬌 五、發明說明（3) 體，而第二半導體元件1 3 0則可能代表第二導電型態的一 場效電晶體，譬如P-通道電晶體。第一半導體元件1 1 0包 含淺溝隔離物（ST I) 11 3，其係由絕緣材料所形成，譬如 二氧化矽，其係並且定義一主動區域1 1 2於基板1 0 1中。閘 ~電極1 1 5係形成於閘絕緣層1 1 8上，該閘絕緣層將閘電極 1 1 5與主動區域1 1 2隔開。由例如二氧化矽或者氮化矽製成 的墊片元件1 1 6，其係放置於閘電極1 1 5的邊牆上。在主動 區域1 1 2中，形成有源極與汲極區域1 1 4，其係並且顯示連 接到一傳導通道所需要的一適當摻雜物剖面，該傳導通道 在操作第一半導體元件11 〇期間内建立於汲極與源極區 域之間。 第二半導體元件13 0包含與第一半導體元件110大致相 同的部件，而相對應的部件則藉由相同的參考數字所代 表，除了 ''導管13〃替代''導管1 Γ以外。如先前所注意 的是，在例如傳導型態、亦即設置於主動區域1 1 2與1 3 2之 摻雜物的型態與濃度、閘電極的水平延伸部份（同樣稱為 閘長度）、截面面積、以及類似物上，第二半導體元件1 3 0 可能不同於第一半導體元件1 1 0。更者，應該注意的是， 雖然將在第1 a圖與第1 b圖中的第一與第二半導體元件1 1 0 與· 3 0描述為電晶體元件，但是第一與第二半導體元件1 1 0 與1 3 0則可能代表使用於電荷載體輸送的任何含矽區域。 例如，相當長的多晶矽線可能在單一晶片區域之不同位置 上連接半導體元件，而且這些多晶矽線可能予以視為第一 與第二半導體元件1 1 〇、1 3 0，電性特徵則予以改善以獲得92308.ptd page 7 200303603 鬌 5. Description of the invention (3), and the second semiconductor element 130 may represent a field-effect transistor of the second conductivity type, such as a P-channel transistor. The first semiconductor device 110 includes a shallow trench spacer (ST I) 11 3, which is formed of an insulating material, such as silicon dioxide, and defines an active region 1 12 in the substrate 101. The gate ~ electrode 1 1 5 is formed on the gate insulating layer 1 1 8 which separates the gate electrode 1 1 5 from the active area 1 1 2. A spacer element 1 16 made of, for example, silicon dioxide or silicon nitride is placed on the side wall of the gate electrode 1 15. In the active region 1 1 2, a source electrode and a drain region 1 1 4 are formed, which show and show a proper dopant profile required for connection to a conductive channel which is operating the first semiconductor element 11. The period is established between the drain and source regions. The second semiconductor element 130 includes substantially the same components as the first semiconductor element 110, and the corresponding components are represented by the same reference numerals, except that the `` conduit 13〃 replaces '' the duct 1 Γ. As previously noted, for example, in the conduction type, that is, the type and concentration of the dopants provided in the active regions 1 12 and 1 32, the horizontal extension of the gate electrode (also referred to as the gate length) , The cross-sectional area, and the like, the second semiconductor element 1 3 0 may be different from the first semiconductor element 1 1 0. Furthermore, it should be noted that although the first and second semiconductor elements 1 1 0 and · 3 0 in FIGS. 1 a and 1 b are described as transistor elements, the first and second semiconductor elements 1 1 0 and 1 3 0 may represent any silicon-containing region used for charge carrier transport. For example, relatively long polycrystalline silicon wires may be connected to semiconductor elements at different locations in a single chip area, and these polycrystalline silicon wires may be considered as first and second semiconductor elements 1 10, 130, and electrical characteristics may be improved to obtain
92308.ptd 第8頁 200303603 五、發明說明（4) 相關於信號傳播延遲之提高的裝置性能。 又參考第la圖，特別在於，第一與第二半導體元件 I 1 0與1 3 0之閘長度決定這些裝置的通道長度，而且如先前 所指出的，其係因此明顯地影響第一與第二半導體元件 II 0與1 3 0的電性特徵，藉此，一縮短的閘長度將因為閘電 極1 1 5、 1 3 5之截面面積的縮小而導致閘電極1 1 5、 1 3 5電阻 的增力口。 用來形成半導體結構1 0 0的基本製程可包含以下步 驟。在藉由熟知的光學微影技術而形成淺溝隔離物1 1 3與 1 3 3之後，乃進行植入步驟，以產生一於主動區域1 1 2與 1 3 2中需要的摻雜物濃度。接著，根據設計規格形成閘絕 緣層1 1 8與1 3 8。此後，閘電極1 1 5與1 3 5則藉由圖案化而形 成，例如一多晶矽層，其乃藉由複雜的光學微影與縮減的 蝕刻方法。然後，進一步進行植入步驟以用來形成所謂源 極與汲極區域1 1 4與1 3 4内源極與汲極延伸部份，並且將墊 片元件1 1 6與1 2 6經由沈積與各向異性蝕刻技術而形成。將 墊片元件1 1 6與1 2 6使用作一植入遮罩，以用於一接著的植 入步驟，其中將摻雜物顆粒植入於源極與汲極區域11 4與 1 3 4内，以於這些區域中產生需要的高摻雜物濃度。應該 注意的是，在第1 a圖中的摻雜濃度會於水平方向中改變， 亦即在閘電極1 1 5、1 3 5的長度方向，以及垂直方向，此後 將稱為深度方向。雖然將源極與汲極區域1 1 4與1 3 4之摻雜 物剖面描述為具有鮮明輪廓的一區域，但是實際上，該摻 雜物剖面則會因為植入製程與接著之退火步驟的特性而連92308.ptd Page 8 200303603 V. Description of the Invention (4) Device performance related to the improvement of signal propagation delay. Referring again to FIG. 1a, in particular, the gate lengths of the first and second semiconductor elements I 1 0 and 1 30 determine the channel length of these devices, and, as previously noted, it significantly affects the first and second Electrical characteristics of the two semiconductor elements II 0 and 130, whereby a shortened gate length will result in the gate electrode 1 1 5 and 1 3 5 resistance due to the reduction in the cross-sectional area of the gate electrodes 1 1 5 and 1 3 5 Booster mouth. The basic process for forming a semiconductor structure 100 may include the following steps. After the shallow trench spacers 1 1 3 and 1 3 3 are formed by the well-known optical lithography technology, an implantation step is performed to generate a required dopant concentration in the active regions 1 1 2 and 1 3 2 . Next, the gate insulation layers 1 1 8 and 1 3 8 are formed according to the design specifications. Thereafter, the gate electrodes 115 and 135 are formed by patterning, for example, a polycrystalline silicon layer, which is formed by a complicated optical lithography and reduced etching method. Then, further implantation steps are performed to form the so-called source and drain regions 1 1 4 and 1 3 4 inside the source and drain extensions, and the spacer elements 1 1 6 and 1 2 6 are deposited by Anisotropic etching technology. The spacer elements 1 1 6 and 1 2 6 are used as an implantation mask for subsequent implantation steps, in which dopant particles are implanted in the source and drain regions 11 4 and 1 3 4 Within these regions, the required high dopant concentration is generated in these regions. It should be noted that the doping concentration in Fig. 1a will change in the horizontal direction, that is, the length direction of the gate electrodes 1 15 and 1 35, and the vertical direction, which will hereinafter be referred to as the depth direction. Although the dopant profiles of the source and drain regions 1 1 4 and 1 3 4 are described as a region with a sharp outline, in fact, the dopant profile is due to the implantation process and the subsequent annealing step. Characteristics
92308.ptd 第9頁 200303603 .五、發明說明（5) 續地改變，該些退火步驟乃為了活化該些植入原子以及固 化由植入步驟所導致的結晶傷害而進行。通常，必須選擇 .摻雜物剖面，以符合第一與第二半導體元件1 1 0與1 3 0的其 它參數。例如，一短閘長度，以及因此的一短通道長度， 1要一 ''淺〃摻雜物剖面，以避免所謂的、'短通道效 應〃。於是，在深度方向中的峰值濃度則可能放置於汲極 與源極區域1 1 4與1 3 4之表面下的數百奈米處。更者，p-通 道電晶體可能需要與η-通道電晶體元件不同的摻雜物剖 面〇 鲁如先前所述，可能予以視為多晶矽線之閘電極1 1 5與 1 3 5的截面，以及在源極與汲極區域1 1 4與1 3 4頂部上的接 觸面積，其係明顯地影響第一與第二半導體元件11 0與1 3 0 的電性特徵。因為，一般而言，這些裝置區域主要地包含 一半導體材料，譬如以結晶、多晶與非結晶型式的矽，所 以這些區域，雖然它們通常包括摻雜物，但與例如金屬線 相較，顯現出一相當高的電阻。而後，處理這些區域，以 提高這些區域的傳導率，從而改進該些裝置的整體性能。 為了此目的，根據第1 a圖，將金屬層1 4 0沈積於第一 與第二半導體元件110與13 0上。基本上，金屬層14 0包含 敍•鈷、或者其它耐火金屬。接著，將第一熱處理，例如 實施快速的熱退火步驟，以在源極與汲極區域1 1 4、1 3 4、 閘電極1 1 5、1 3 5之矽以及包含於金屬層1 4 0的金屬之間起 始一化學反應。假如，例如金屬層1 4 0大致上包含始的 話，第一熱處理的平均溫度則可能設定在大約4 0 0°C，以92308.ptd page 9 200303603. V. Description of the invention (5) Continuously changing, the annealing steps are performed to activate the implanted atoms and to solidify the crystal damage caused by the implantation step. In general, the dopant profile must be selected to meet other parameters of the first and second semiconductor elements 110 and 130. For example, a short gate length, and therefore a short channel length, requires a '' shallow '' dopant profile to avoid the so-called 'short channel effect'. Therefore, the peak concentration in the depth direction may be placed hundreds of nanometers below the surface of the drain and source regions 1 1 4 and 1 3 4. Furthermore, the p-channel transistor may require a different dopant profile from the η-channel transistor element. As previously mentioned, it may be considered as a cross-section of the gate electrodes 1 1 5 and 1 3 5 of the polycrystalline silicon wire, and The contact area on top of the source and drain regions 1 1 4 and 1 3 4 significantly affects the electrical characteristics of the first and second semiconductor elements 110 and 130. Because, in general, these device regions mainly consist of a semiconductor material, such as silicon in crystalline, polycrystalline, and amorphous forms, these regions, although they usually include dopants, appear to be compared to, for example, metal wires. Out of a fairly high resistance. These areas are then processed to increase the conductivity of these areas and thereby improve the overall performance of the devices. For this purpose, according to Fig. 1a, a metal layer 140 is deposited on the first and second semiconductor elements 110 and 130. Basically, the metal layer 140 comprises Sycobalt or other refractory metals. Next, a first heat treatment, for example, a rapid thermal annealing step is performed to form silicon in the source and drain regions 1 1 4, 1 3 4, the gate electrodes 1 1 5, 1 3 5, and the metal layer 1 4 0 A chemical reaction is initiated between the metals. If, for example, the metal layer 1 4 0 contains approximately the beginning, the average temperature of the first heat treatment may be set at about 4 0 ° C to
92308.pid 第10頁 200303603 五、發明說明（6) 產生呈現相當高電阻率之亞穩鈷矽化合物。因為將包含於 墊片元件1 1 6、1 3 6以及淺溝隔離物1 1 3、1 3 3的矽以二氧化 物或者氮化物的形式化學結合，金屬層1 4 0的金屬則不會 實質地與墊片元件1 1 5、1 3 6以及淺溝隔離物1 1 3、1 3 3之材 料反應。在第一熱處理之後，將已經不與打底材料反應之 金屬層1 4 0的材料藉由例如選擇性濕式蝕刻製程而來移 除。此後，進行第二熱處理，例如以高於第一退火步驟之 溫度的第二快速退火步驟，將該亞穩金屬-矽化合物轉換 成金屬矽化物。在以上實例中，當使用鈷時，二矽化鈷則 形成於第二退火步驟中。金屬矽化物顯示出比亞穩金屬矽 化合物還明顯更低的電阻，以及以大約5至1 0之因數明顯 低於摻雜多晶矽之薄層電阻的電阻。 弟1 b圖圖式地顯不袁後得到的第一與第二半導體元件 1 1 0與1 3 0，其具有一金屬矽化物區域1 4 1形成於個別的源 極與汲極區域1 1 4、1 3 4以及閘電極1 1 5、1 3 5上。 雖然金屬矽化物區域1 4 1明顯地改善第一與第二半導 體元件1 1 0與1 3 0的電性特徵，但是卻仍有改善的空間，其 乃因為在習知生產流程中，必須形成金屬矽化物區域 1 4 1，以符合第一半導體元件1 1 0與第二半導體元件1 3 0的 條件，故可有效進行第一半導體元件1 1 0之矽化物區域 1 4 1，累及第二半導體元件1 3 0之矽化物區域1 4 1效果之特 徵，反之亦然。 因此令人希望的則是具有一半導體以及其形成方法， 其中導電性半導體區域的特徵可分別地有效進行，以用於92308.pid Page 10 200303603 V. Description of the invention (6) Produce metastable cobalt-silicon compounds with relatively high resistivity. Because the silicon contained in the spacer element 1 1 6, 1 3 6 and the shallow trench spacer 1 1 3, 1 3 3 is chemically bonded in the form of dioxide or nitride, the metal of the metal layer 1 4 0 does not Substantially reacts with the materials of the spacer elements 1 1 5, 1 3 6 and the shallow trench spacers 1 1 3, 1 3 3. After the first heat treatment, the material of the metal layer 140 which has not reacted with the primer material is removed by, for example, a selective wet etching process. Thereafter, a second heat treatment, such as a second rapid annealing step at a temperature higher than the first annealing step, is performed to convert the metastable metal-silicon compound into a metal silicide. In the above example, when cobalt is used, cobalt disilicide is formed in the second annealing step. The metal silicide shows a significantly lower resistance than the metastable metal silicon compound, and is significantly lower than the resistance of the doped polycrystalline silicon sheet by a factor of about 5 to 10. Brother 1b diagrammatically shows the first and second semiconductor elements 1 1 0 and 1 3 0 obtained later, which has a metal silicide region 1 4 1 formed in individual source and drain regions 1 1 4, 1 3 4 and gate electrodes 1 1 5 and 1 3 5. Although the metal silicide region 1 4 1 obviously improves the electrical characteristics of the first and second semiconductor elements 1 10 and 1 30, there is still room for improvement because it must be formed in the conventional production process. The metal silicide region 1 4 1 meets the conditions of the first semiconductor element 1 10 and the second semiconductor element 130, so the silicide region 1 4 1 of the first semiconductor element 1 1 0 can be effectively performed, affecting the second Characteristics of the effect of the silicide region 1 41 of the semiconductor device 130 are vice versa. Therefore, it is desirable to have a semiconductor and a method for forming the same, in which the characteristics of the conductive semiconductor region can be effectively performed separately for use in
92308.ptd 第11頁 200303603 ι五、發明說明（7) 不同的半導體元件。 本發明乃針對一種可能解決、或者至少減少一些或者 所有上述問題的方法。 [内容] ~ 本發明一般係關於製造一半導體裝置的方法，其中含 矽區域容納一金屬矽化物部份，以提高這些區域的電性特 性，其中金屬矽化物部份的材料型態與/或厚度個別地予 以調整，以鑑於電阻而符合不同半導體區域的需求條件。 根據本發明的一說明性具體實施例，一種形成一半導 翻^置的方法包含提供一基板，其上形成有一第一與一第 二導電性含石夕區域，並且形成一第一抗钱劑遮罩，以用於 覆蓋一第二傳導性含矽區域，而卻暴露出第一傳導性含矽 區域。更者，將一預定厚度的一第一金屬層沈積於基板 上，並且移除第一抗钱劑遮罩。進一步，該方法包括形成 一第二抗蝕劑遮罩，以用來覆蓋第一傳導性含矽區域以及 暴露第二傳導性含矽區域。此後，將一第二預定厚度的一 第二金屬層沈積於基板上，並且隨後將第二抗蝕劑遮罩移 除。此外，該方法包括該基板的一熱處理，以於第一傳導 性含矽區域上形成一第一矽化物層以及於第二傳導性含矽 區儀^上一第二石夕化物層形成。 根據一進一步的具體實施例，一種形成半導體裝置的 方法包含形成複數個傳導性含矽區域於基板上。此後，使 用一沈積遮罩而將複數層不同金屬層連續地沈積於基板 上，以致使複數個傳導性含矽區域的每一個皆大致地由一92308.ptd Page 11 200303603 ι V. Description of the invention (7) Different semiconductor components. The present invention is directed to a method that may solve, or at least reduce, some or all of the above problems. [Content] ~ The present invention generally relates to a method for manufacturing a semiconductor device, in which a silicon-containing region contains a metal silicide portion to improve the electrical characteristics of these regions, wherein the material type of the metal silicide portion and / or The thickness is individually adjusted to meet the requirements of different semiconductor regions in view of resistance. According to an illustrative embodiment of the present invention, a method for forming a semi-conductive device includes providing a substrate on which a first and a second conductive stone-containing region are formed, and a first anti-money agent is formed. A mask for covering a second conductive silicon-containing region while exposing the first conductive silicon-containing region. Furthermore, a first metal layer of a predetermined thickness is deposited on the substrate, and the first anti-money mask is removed. Further, the method includes forming a second resist mask for covering the first conductive silicon-containing region and exposing the second conductive silicon-containing region. Thereafter, a second metal layer of a second predetermined thickness is deposited on the substrate, and the second resist mask is subsequently removed. In addition, the method includes a heat treatment of the substrate to form a first silicide layer on the first conductive silicon-containing region and a second silicide layer on the second conductive silicon-containing region. According to a further specific embodiment, a method of forming a semiconductor device includes forming a plurality of conductive silicon-containing regions on a substrate. Thereafter, a plurality of different metal layers are successively deposited on the substrate using a deposition mask such that each of the plurality of conductive silicon-containing regions is substantially formed by a
92308.ptd 第12頁 200303603 五、發明說明（8) 單一金屬層所覆蓋，其中該些金屬層則藉由它們的材料型 態與/或者它們的層厚度而彼此不同。該方法進一步包含 在一第一時間間隔内、以一第一平均溫度而將該基板退 火，以於各傳導性含矽區域上形成一金屬矽化合物，以及 選擇性地自基板將過量的金屬移除。此外，該方法包括在 一第二時間間隔内、以一第二平均溫度而將該基板退火， 以將金屬矽化合物轉變成一金屬矽化物部份，其中控制第 一與第二平均溫度以及第一與第二時間間隔的至少其中一 者，以調整金屬矽化物部份的厚度。 根據一進一步的說明性具體實施例，半導體裝置包含 至少一第一傳導性含矽區域與至少一第二傳導性含矽區 域，其中第一與第二傳導性含矽區域係形成於一共同層 中。更者，該半導體裝置包含一形成於第一傳導性含矽區 域上之第一金屬矽化物部份，以及一之形成於第二傳導性 含矽區域中第二金屬矽化物部份，其中第一與第二金屬矽 化物部份的至少其中一者包含一貴重金屬。 [實施方式] 將本發明之說明性具體實施例說明如下。為了清晰起 見，並非一真實實施過程的所有特徵均說明於本說明書 中。當然將理解的是，在任何此種真實具體實施例的發展 中，必須進行種種明確實施的決定，以得到發展者的明確 目標，譬如與系統相關以及企業相關限制的一致性，其係 將從一實施過程改變到另一實施過程。更者，將令人理解 到的是，此一發展努力可能既複雜且耗時，不過卻是那些92308.ptd Page 12 200303603 V. Description of the invention (8) Covered by a single metal layer, wherein the metal layers are different from each other by their material type and / or their layer thickness. The method further includes annealing the substrate at a first average temperature within a first time interval to form a metal silicon compound on each of the conductive silicon-containing regions, and selectively removing excess metal from the substrate. except. In addition, the method includes annealing the substrate at a second average temperature at a second time interval to convert the metal silicon compound into a metal silicide portion, wherein the first and second average temperatures and the first And at least one of the second time interval to adjust the thickness of the metal silicide portion. According to a further illustrative embodiment, the semiconductor device includes at least a first conductive silicon-containing region and at least a second conductive silicon-containing region, wherein the first and second conductive silicon-containing regions are formed on a common layer. in. Furthermore, the semiconductor device includes a first metal silicide portion formed on the first conductive silicon-containing region, and a second metal silicide portion formed on the second conductive silicon-containing region, wherein the first At least one of the first and second metal silicide portions includes a precious metal. [Embodiment] An illustrative specific embodiment of the present invention will be described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will be understood, of course, that in the development of any such real embodiment, decisions must be made to implement it explicitly in order to obtain the clear goals of the developer, such as the consistency of system-related and enterprise-related restrictions, which will be derived from Change from one implementation to another. What's more, it will be understood that this development effort may be complex and time-consuming, but it is only those
9230S.ptd 第13頁 200303603 五、發明說明（9) 一般熟諳該技藝者所著手進行的例行公事，其係具有本發 明之優點。 參考第2 a至2 f圖，現將說明本發明的說明性具體實施 例，其中，如先前所指出的，將兩個或更多個不同的導電 性含矽區域容納一矽化物部份，而其材料型態與/或者其 厚度乃相應地予以設計，以改善這些區域的導電率。例 如，如有必要得到連接兩不同晶片區域之長石夕線用的一類 似信號傳播延遲，則根據本發明，其中一矽線係顯示出比 另一矽線還大的截面面積，不同的矽化物部份係形成於這 #夕線上，以改善全部的特徵並且大致地補償不同的截面 面積。相同的情形應用在不同型態的電晶體元件，譬如η-通道電晶體與ρ-通道電晶體，該些電晶體一般而言具有不 同的摻雜物剖面，並且亦具有一不同的阻障物高度，該阻 障物高度則在矽化物部份與摻雜含矽區域之間的介面上經 歷一電荷載體。既然如此，本發明於該裝置中同樣允許任 何人恰當地形成相對應的矽化物部份，以個別地將該些裝 置的性能最佳化。同樣地，短通道裝置一般需要與長通道 裝置之一不同型態的矽化物部份，因為例如，比起需要相 當淺連接介面的短通道裝置，在長通道裝置中，峰值摻雜 度乃更深地放置於汲極與源極區域中。本發明允許任 何人分別地調整在一深度之矽化物部份的過度重疊，而峰 值摻雜物濃度乃大約地放置於該深度上，以便得到用於電 荷載體的最小過渡電阻，特別在同樣地選擇金屬矽化物之 阻障高度，以符合普遍出現於電晶體裝置之主動區域之摻9230S.ptd Page 13 200303603 V. Description of the invention (9) The routine work performed by the artist who is generally familiar with this technique has the advantages of the present invention. Referring to Figures 2a to 2f, an illustrative embodiment of the present invention will now be described, in which, as previously indicated, two or more different conductive silicon-containing regions accommodate a silicide portion, The material type and / or thickness are designed accordingly to improve the conductivity of these regions. For example, if it is necessary to obtain a similar signal propagation delay for feldspar wires connecting two different chip regions, according to the present invention, one of the silicon lines shows a larger cross-sectional area than the other silicon line, and different silicides Parts are formed on this line to improve all features and roughly compensate for different cross-sectional areas. The same situation applies to different types of transistor elements, such as η-channel transistors and ρ-channel transistors. These transistors generally have different dopant profiles and also have different barriers. Height, the barrier height undergoes a charge carrier on the interface between the silicide portion and the doped silicon-containing region. In this case, the present invention also allows anyone in the device to properly form the corresponding silicide portions to individually optimize the performance of the devices. Similarly, short-channel devices generally require a different type of silicide part than one of the long-channel devices, because, for example, the peak doping level is deeper in a long-channel device than a short-channel device that requires a relatively shallow connection interface. Ground is placed in the drain and source regions. The present invention allows anyone to individually adjust the excessive overlap of the silicide portion at a depth, and the peak dopant concentration is approximately placed at that depth in order to obtain the minimum transition resistance for the charge carrier, especially at the same Select the barrier height of the metal silicide to comply with the doping commonly found in active areas of transistor devices
92308.ptd 第14頁 200303603 五、發明說明（ίο) 雜物型態的時候。因此，雖然在以下的詳細說明中，將代 表一令人讚賞電晶體對的第一與第二半導體元件列為參 考，但是本發明則涵蓋所有的態樣，在該些態樣中，含矽 區域是需要的，以容納個別適合的矽化物部份，而改善個 別半導體區域的性能或者改善半導體裝置的整體性能。 在第2a圖中，半導體結構2 0 0包含一基板201，例如一 矽基板或者適合形成半導體元件的任何其它基板。在基板 2 0 1中，第一半導體元件2 1 0包含由淺溝隔離物2 1 3所界定 的一主動區域2 1 2。將閘電極2 1 5藉由閘絕緣層2 1 8而與主 動區域2 1 2分隔。譬如二氧化石夕或者氮化石夕之絕緣材料的 墊片元件2 1 6，其係鄰近閘電極2 1 5之邊牆而形成。在主動 區域2 1 2中，有源極與汲極區域2 1 4形成。 半導體結構20 0進一步包括一第二半導體元件230，其 大致上包含與第一半導體元件2 1 0相同的部件。因此，相 對應的部件則由相同的參考數字所表示，除了導管'' 2 3〃 替代導管'' 2 Γ之外。應該注意的是，雖然描述非常類 似，但是第一與第二半導體元件2 1 0與2 3 0則在以上所指出 的意義上彼此不同。更者，在第二半導體元件2 3 0上形成 有抗钱劑遮罩2 5 0。 用來形成半導體結構2 0 0的基本生產流程可非常類似 參考第1 a圖與第1 b圖所說明的製程，因此遂將這些製程步 驟的說明予以刪除。抗蝕劑遮罩2 5 0可能藉由習知的光學 微影術而形成，不過，其中既然在淺溝隔離物2 3 3上抗蝕 劑遮罩2 5 0的精確位置不具關鍵性，所以不須太過顧慮。92308.ptd Page 14 200303603 V. Description of invention (ίο) When the type of sundries. Therefore, although in the following detailed description, the first and second semiconductor elements representing an admirable transistor pair are listed as a reference, the present invention covers all aspects in which silicon-containing Regions are needed to accommodate individual suitable silicide portions to improve the performance of individual semiconductor regions or the overall performance of semiconductor devices. In Figure 2a, the semiconductor structure 200 includes a substrate 201, such as a silicon substrate or any other substrate suitable for forming a semiconductor element. In the substrate 2 01, the first semiconductor element 2 1 0 includes an active region 2 1 2 defined by the shallow trench spacer 2 1 3. The gate electrode 2 1 5 is separated from the active region 2 1 2 by a gate insulating layer 2 1 8. For example, the spacer element 2 1 6 of the insulating material of the stone dioxide or the nitride stone is formed adjacent to the side wall of the gate electrode 2 1 5. In the active region 2 1 2, a source electrode and a drain region 2 1 4 are formed. The semiconductor structure 200 further includes a second semiconductor element 230, which includes substantially the same components as the first semiconductor element 210. Therefore, the corresponding parts are indicated by the same reference numerals, except for the conduit `` 2 3〃 instead of the conduit '' 2 Γ. It should be noted that, although the descriptions are very similar, the first and second semiconductor elements 210 and 230 are different from each other in the sense indicated above. Furthermore, an anti-money mask 2 50 is formed on the second semiconductor element 230. The basic production processes used to form the semiconductor structure 2000 can be very similar. Referring to the processes illustrated in Figures 1a and 1b, the description of these process steps has been deleted. The resist mask 2 50 may be formed by conventional optical lithography, but since the precise position of the resist mask 2 5 0 on the shallow trench spacer 2 3 3 is not critical, so Don't worry too much.
92308.ptd 第15頁 200303603 、峰 、五、發明說明（11) 第2b圖圖式地顯示半導體結構2 0 0，有一第一金屬層 2 4 0沈積於半導體結構2 0 0上。該第一金屬層2 4 0可包含適 .合形成於含矽區域2 1 4與2 1 5之金屬矽化物的需要特徵之任 何耐火金屬或者金屬化合物，合適的金屬可包括始、鈦、 為、鎢、以及其結合物。在一特別的具體實施例中，第一 金屬層2 4 0可包含一貴重金屬，譬如#、把、金與類似 物。選擇第一金屬層2 4 0的厚度與其成分，以致使在接著 的退火步驟中，會發生矽與金屬原子的相互擴散，而可形 成具所需滲透深度，亦即產生一最小的過渡電阻給該電荷 所需之厚度及所需之阻障物高度之金屬矽化物部份。 例如，可使鈷層沈積至具有30至80nm的厚度。在第2b圖 中，第一金屬層24 0覆蓋抗餘劑遮罩2 5 0的表面，然而抗姓 劑遮罩2 5 0的邊牆部份2 5 2則大致上並未遮蓋。為達成此目 的，可應用一沈積技術，該沈積技術得以任何具金屬而使 邊牆部份2 5 2的覆蓋範圍最小化之技術。例如，可使用物 理氣相沈積（PVD)技術，譬如濺鍍沈積，其中將製程參 數調整，以使從一目標物濺鍍出的原子與離子撞擊到在一 大致垂直方向中的半導體結構2 0 0。因而，使在邊牆部份 2 5 2上之第一金屬層24 0的沈積最小化。大致上垂直地撞擊 言#導體結構2 0 0，可藉由使用鄰近基板2 0 1之濺鍍沈積室 中的準直管而得到，以''引導〃該些離子與原子接近該基 板2 0 1。進來之離子與原子所需要的方向性藉由調整濺鍍 沈積室内的磁場與電場亦可同樣地得到，以獲得一最小步 驟範圍。92308.ptd page 15 200303603, peak, five, description of the invention (11) Figure 2b schematically shows the semiconductor structure 200, and a first metal layer 2 40 is deposited on the semiconductor structure 2000. The first metal layer 2 4 0 may include any refractory metal or metal compound suitable for the required characteristics of the metal silicide formed in the silicon-containing regions 2 1 4 and 2 1 5. Suitable metals may include starting, titanium, and , Tungsten, and combinations thereof. In a specific embodiment, the first metal layer 240 may include a precious metal, such as #, bar, gold, and the like. The thickness and composition of the first metal layer 2 40 are selected so that in the subsequent annealing step, interdiffusion of silicon and metal atoms will occur, and a desired penetration depth can be formed, that is, a minimum transition resistance is generated. The metal silicide portion of the required thickness of the charge and the required barrier height. For example, a cobalt layer can be deposited to a thickness of 30 to 80 nm. In Fig. 2b, the first metal layer 24 0 covers the surface of the anti-residue mask 2 50, but the side wall portion 2 5 2 of the anti-resistance mask 2 50 is substantially uncovered. To achieve this, a deposition technique can be applied, which can be any technique that has metal to minimize the coverage of the side wall portion 2 5 2. For example, physical vapor deposition (PVD) techniques, such as sputtering deposition, can be used, in which process parameters are adjusted so that atoms and ions sputtered from a target impact the semiconductor structure in a substantially vertical direction. 0. Thus, the deposition of the first metal layer 240 on the side wall portion 252 is minimized. Impacting the conductor structure 2 0 substantially vertically can be obtained by using a collimator in a sputtering deposition chamber adjacent to the substrate 2 1 to guide the ions and atoms closer to the substrate 2 0 1. The required directivity of the incoming ions and atoms can also be obtained by adjusting the magnetic and electric fields in the sputtering deposition chamber to obtain a minimum step range.
92308.ptd 第16頁 200303603 五、發明說明（12) 第2 c圖圖式顯示抗蝕劑遮罩2 5 0與覆蓋之第一金屬層 2 4 0移除的半導體結構2 0 0。移除抗蝕劑遮罩2 5 0以及第二 半導體元件2 3 0上之第一金屬層2 4 0部份可藉由一選擇性濕 式蝕刻製程而獲得，該製程使用具有蝕刻速率明顯高於第 一金屬層2 4 0所用之抗蝕劑遮罩2 5 0之化學試劑。依據以第 一金屬層2 4 0之金屬來覆蓋邊牆部份2 5 2的程度，可能會相 應地選擇最初沈積之第一金屬層2 4 0的預定厚度，以使在 接著的蝕刻製程中，第一半導體元件2 1 0上第一金屬層2 4 0 的厚度不會保持小於所需之最小厚度。假如例如移除抗蝕 劑遮罩2 5 0大約花6 0秒，而且第一金屬層24 0之I虫刻速率大 概為每分鐘1 0nm的話，那麼選擇最初的層厚度比至少形成 符合設計規格之金屬矽化物所需要者還厚大約1 0nm。藉著 從邊牆部份2 5 2而將抗钮劑遮罩2 5 0〜底钱〃，在餘刻抗姓 劑遮罩2 5 0的過程期間内，在抗勉劑遮罩2 5 0頂部之第一金 屬層2 4 0的機械整體性會受到侵蝕，而且自第一金屬層2 4 0 分離的個體部份則將予以洗淨。既使邊牆部份2 5 2稍微由 金屬覆蓋，延長蝕刻時間仍可將抗蝕劑遮罩2 5 0移除，其 乃因為在邊牆部份的金屬層厚度頗小於基板2 0 1大致上水 平表面部份上之第一金屬層24 0的厚度。一般而言，邊牆 部份2 5 2的金屬層厚度將不超過水平表面部份的大約1 0 °/〇 。因此，第一半導體元件2 1 0能容納C形成矽化物部份所 需之特徵而組成之第一金屬層2 4 0。 在第2 d圖中，第二光阻遮罩2 5 5係形成於第一半導體 元件210上，而第二金屬層24 2則覆蓋式地沈積於半導體結92308.ptd Page 16 200303603 V. Description of the invention (12) Figure 2c schematically shows the resist mask 2 50 and the first metal layer 2 4 0 covering the removed semiconductor structure 2 0 0. Removal of the resist mask 250 and the first metal layer 240 on the second semiconductor device 230 can be obtained by a selective wet etching process, which uses a significantly higher etching rate. The resist used on the first metal layer 24 0 masks the 2 500 chemical agent. Depending on the extent to which the side wall portion 2 5 2 is covered with the metal of the first metal layer 2 4 0, a predetermined thickness of the first metal layer 2 4 0 deposited initially may be selected accordingly so that in the subsequent etching process The thickness of the first metal layer 2 4 0 on the first semiconductor element 2 10 will not remain less than the required minimum thickness. For example, if it takes about 60 seconds to remove the resist mask 250, and the etch rate of the first metal layer 240 is about 10 nm per minute, then the initial layer thickness ratio is selected to at least meet the design specifications. The metal silicide is also about 10 nm thick. By covering the anti-buttoning agent from the side wall portion 2 5 2 to 2 0 0 to 5 〃, during the remaining process of the anti-surgical agent covering 2 5 0, the anti-repellent agent is covered by 2 5 0 The mechanical integrity of the top first metal layer 240 will be eroded, and the individual parts separated from the first metal layer 240 will be washed away. Even if the side wall portion 2 5 2 is slightly covered by metal, the resist mask 2 50 can be removed by prolonging the etching time because the thickness of the metal layer in the side wall portion is considerably smaller than that of the substrate 2 0 1 The thickness of the first metal layer 240 on the upper horizontal surface portion. In general, the thickness of the metal layer of the side wall portion 2 5 2 will not exceed about 10 ° / 〇 of the horizontal surface portion. Therefore, the first semiconductor element 210 can accommodate the first metal layer 24 which is composed of the features required for the silicide portion of C. In Fig. 2d, a second photoresist mask 2 5 5 is formed on the first semiconductor element 210, and a second metal layer 24 2 is deposited on the semiconductor junction in a covered manner.
92308.pid 第17頁 200303603 、五、發明說明（13) 構2 0 0上。就形成第二光阻遮罩2 5 5而言，相同的標準乃如 參考光阻遮罩2 5 0所指出的應用於此。相同的情形乃適用 於形成第二金屬層2 4 2用的沈積方法。同樣地，在此情形 中，第二光阻遮罩2 5 5的邊牆部份2 5 7大致上未受遮蓋，或 者至少比半導體基板2 0 0之表面部份還明顯較少受到遮 蓋。就第二金屬層2 4 2的成分以及厚度而言，以上所設之 相同標準可應用於此情形中。 在一具體實施例中，可提供複數個不同半導體元件， 其中在後續之遮罩步驟中，在複數個半導體元件的各個 ，沈積一不同金屬層。例如，除了抗餘劑遮罩2 5 0與2 5 5 之外，可提供進一步的抗蝕劑遮罩（未顯示），其中可設 計該抗姓劑遮罩2 5 0、2 5 5與進一步的抗钱劑遮罩使一第三 金屬層沈積於一第三半導體元件上（未顯示）。此遮罩順 序可以適當設計的遮罩予以重複，以便可將複數層不同金 屬層沈積於相對應之複數個不同種類的半導體元件上，該 些元件係予以個別地最佳化，以為了在這些半導體元件中 所必須要的矽化物部份。 第2 e圖圖式地顯示第一與第二半導體元件2 1 0與2 3 0， 其分別具有第一金屬層24 0與第二金屬層242。第一與第二 層2 4 0與2 4 2包含一材料並且顯示出一厚度，而當轉變 成一金屬矽化物時，兩者的目標皆是使第一與第二半導體 元件2 1 0、2 3 0的特徵最佳化。特別是，第一金屬層2 4 0以 及/或者第二金屬層24 2可能包含至少一貴重金屬。 接著，進行一熱處理，例如一快速的熱退火步驟，以92308.pid Page 17 200303603 V. Description of the invention (13) Structure 2 0 0. As far as forming the second photoresist mask 2 5 5, the same criteria apply as indicated with reference to the photoresist mask 2 50. The same applies to the deposition method for forming the second metal layer 242. Similarly, in this case, the side wall portion 2 5 7 of the second photoresist mask 2 5 5 is substantially uncovered, or at least significantly less covered than the surface portion of the semiconductor substrate 2000. With regard to the composition and thickness of the second metal layer 2 4 2, the same criteria set above can be applied in this case. In a specific embodiment, a plurality of different semiconductor elements may be provided. In a subsequent masking step, a different metal layer is deposited on each of the plurality of semiconductor elements. For example, in addition to the anti-residue masks 2 5 0 and 2 5 5, further resist masks (not shown) may be provided, where the anti-surname masks 2 5 0, 2 5 5 and further The anti-money mask causes a third metal layer to be deposited on a third semiconductor element (not shown). This mask sequence can be repeated with appropriately designed masks so that a plurality of different metal layers can be deposited on a corresponding plurality of different types of semiconductor components, which are individually optimized in order to The necessary silicide in semiconductor devices. FIG. 2e schematically shows the first and second semiconductor elements 2 1 0 and 2 3 0, which respectively have a first metal layer 24 0 and a second metal layer 242. The first and second layers 2 4 0 and 2 4 2 contain a material and show a thickness, and when converted into a metal silicide, the goal of both is to make the first and second semiconductor elements 2 1 0, 2 30 features are optimized. In particular, the first metal layer 24 and the second metal layer 24 2 may contain at least one precious metal. Next, a heat treatment, such as a rapid thermal annealing step, is performed to
92308.ptd 第18頁 200303603 五、發明說明（14) 起始在第一與第二金屬層240、242中之金屬以及包含於區 域2 1 4、2 3 4與2 1 5、2 3 5中之矽之間的化學反應。在一具體 實施例中，在以第一溫度持續一第一時間間隔的一第一快 速熱退火步驟之後，發生區域2 1 4、2 3 4、2 1 5、2 3 5之原子 及第一與第二金屬層2 4 0、2 4 2之原子擴散，俾維持矽與金 屬之間的連續反應。金屬矽化物的擴散程度取決於材料型 態、退火過程的溫度以及所持續的時間。一般而言，具有 較高溶化溫度的金屬傾向於顯示出一較低的擴散活性。因 此，金屬矽化物的厚度可藉控制第一平均溫度與第一時間 間隔而予以部份地調整。接著，將過量的金屬從半導體結 構2 0 0的表面移除，並可以第二溫度、在第二時間間隔 内、進行第二快速熱退火步驟。一般而言，第二平均溫度 高於第一溫度，以得到具有相當低電阻的一穩定金屬矽化 物。第二平均溫度與第二時間間隔可受到控制，以得到在 區域214、215、234、23 5之每一個中所需要的薄層電阻。 應該注意的是，雖然第一與第二金屬層2 4 0、2 4 2彼此不 同，但是因為包含第一與第二金屬層240、24 2之材料的反 應特徵眾所皆知，而且可能選擇為能產生希望的薄層電 阻，所以在第一與第二半導體元件2 1 0與2 3 0中的薄層電阻 仍然可能以一般的熱處理而作個別地調整。在第一與第二 快速熱退火步驟之間，第一與第二金屬層2 4 0、2 4 2的過量 金屬可藉由一選擇性的姓刻製程而移除，其中金屬與金屬 化合物不需彼此相關地予以有利地選擇性移除。因此，第 一與第二金屬層240、24 2的非反應性金屬則可能以一般的92308.ptd Page 18 200303603 V. Description of the invention (14) Metals starting in the first and second metal layers 240, 242 and contained in the regions 2 1 4, 2 3 4 and 2 1 5, 2 3 5 Chemical reaction between silicon. In a specific embodiment, after a first rapid thermal annealing step at a first temperature for a first time interval, the atoms in the region 2 1 4, 2 3 4, 2 1 5, 2 3 5 and the first Diffusion with the atoms of the second metal layers 2 40 and 2 4 2 allows the continuous reaction between silicon and metal. The degree of metal silicide diffusion depends on the material type, the temperature of the annealing process, and the duration. In general, metals with higher melting temperatures tend to show a lower diffusion activity. Therefore, the thickness of the metal silicide can be partially adjusted by controlling the first average temperature and the first time interval. Next, the excess metal is removed from the surface of the semiconductor structure 200, and a second rapid thermal annealing step can be performed at a second temperature and within a second time interval. Generally, the second average temperature is higher than the first temperature to obtain a stable metal silicide having a relatively low resistance. The second average temperature and the second time interval can be controlled to obtain the required sheet resistance in each of the regions 214, 215, 234, 235. It should be noted that although the first and second metal layers 24 0, 2 4 2 are different from each other, because the reaction characteristics of materials including the first and second metal layers 240, 24 2 are well known, and may be selected In order to generate a desired sheet resistance, the sheet resistance in the first and second semiconductor elements 210 and 230 may still be individually adjusted by ordinary heat treatment. Between the first and second rapid thermal annealing steps, excess metal in the first and second metal layers 24 0, 2 4 2 can be removed by a selective surname process, in which the metal and metal compounds are not They need to be advantageously selectively removed in relation to each other. Therefore, the non-reactive metals of the first and second metal layers 240, 24 2 may
9230S.ptd 第19頁 200303603 五、發明說明（15) % 钱刻製程來移除。更者，相較於先前所說的習知加工處 理，不需任何額外的熱處理，因此不會引起 ''熱預算〃。 ，第2 f圖圖式顯示最後得到的半導體結構2 0 0，其中第 一半導體元件2 1 0包含第一矽化物部份2 4 1，其成分與/或 滹度係適合含矽半導體區域2 1 4與2 1 5上所需之薄層電阻。 同樣地，第二半導體元件23 0包含適於符合第二半導體元 件2 3 0的具體規格之第二矽化物部份2 4 3，。如先前所注意 的，第一矽化物部份2 4 1與/或者第二矽化物部份2 4 3可能 包含一貴重金屬，譬如舶、妃、金與類似物，合併以对火 譬如始、鈦、錄、鎢與類似物。甚者，將第一與第 二矽化物部份2 4 1、2 4 3的厚度，亦即矽化物在深度方向 ''滲透〃入區域2 1 4、2 1 5、2 3 4與2 3 5的程度作調整，以得 到需要的薄層電阻。如果，例如第一半導體元件代表一 p-通道電晶體的話，在該電晶體中，P-型摻雜物的峰值濃度 則放置於大約20 Onm的深度，而矽化物部份的厚度，亦即 滲透度，則可調整到大約180至22 On m。相同的考量亦可應 用在一般呈現淺摻雜物剖面之η -通道電晶體。 以上所揭露的特定具體實施例僅供說明，雖然本發明 可能以那些熟諳該技藝者所明瞭之不同但等同的方式來修 改^實施，但卻仍具有在此學說的優點。例如，以上所述 之製程步驟可能以不同的順序來進行。甚者，並不打算將 在此所示之結構或者設計的細節設限，除了以下所說明的 申請專利範圍之外。因此明顯的是，以上所說明的特定具 體實施例可能予以更改或者修改，而且在本發明的範圍與9230S.ptd Page 19 200303603 V. Description of the invention (15)% Money engraving process to remove. Moreover, compared with the conventional processing mentioned previously, no additional heat treatment is required, so it does not cause a `` thermal budget ''. Figure 2f schematically shows the finally obtained semiconductor structure 2 0 0, where the first semiconductor element 2 1 0 includes a first silicide portion 2 4 1 whose composition and / or degree are suitable for the silicon-containing semiconductor region 2 The required sheet resistance on 1 4 and 2 1 5. Similarly, the second semiconductor element 23 0 includes a second silicide portion 2 4 3 ′ suitable for meeting the specific specifications of the second semiconductor element 230. As previously noted, the first silicide portion 2 4 1 and / or the second silicide portion 2 4 3 may contain a precious metal, such as sea, princess, gold, and the like, merged to counteract the fire such as, Titanium, tungsten, tungsten and the like. Furthermore, the thickness of the first and second silicide portions 2 4 1, 2 4 3, that is, the silicide penetrates into the region 2 1 4, 2 1 5, 2 3 4 and 2 3 in the depth direction. The degree of 5 is adjusted to obtain the required sheet resistance. If, for example, the first semiconductor element represents a p-channel transistor, in the transistor, the peak concentration of the P-type dopant is placed at a depth of about 20 Onm, and the thickness of the silicide portion, that is, The permeability can be adjusted to approximately 180 to 22 On m. The same considerations apply to η-channel transistors, which generally exhibit shallow dopant profiles. The specific embodiments disclosed above are for illustration only. Although the present invention may be modified and implemented in different but equivalent ways known to those skilled in the art, it still has the advantages of this teaching. For example, the process steps described above may be performed in a different order. Furthermore, it is not intended to limit the details of the structure or design shown here, except for the scope of patent application described below. Therefore, it is obvious that the specific embodiments described above may be changed or modified, and within the scope of the present invention and
9230S.ptd 第20頁 200303603 五、發明說明（16) 精神内的所有此些變更則予以列入考慮。相應地，在此所 尋求的保護乃陳述於以下的申請專利範圍中。9230S.ptd Page 20 200303603 V. Description of Invention (16) All such changes within the spirit are considered. Accordingly, the protection sought herein is set forth in the scope of the patent application below.
9230S.ptd 第21頁 200303603 ;圖式簡單說明 [圖式簡單說明] 本發明可能參考結合附圖的以下說明來理解，其中相 同的參考符號指的是相同元件，而且其中： 第la圖與第lb圖顯示第一與第二半導體元件的圖式截 面圖，其具有一矽化物部份形成於傳導區域中，其中第一 與第二半導體元件則根據一般的習知技術製程而來製造； 以及 第2 a至2 f圖圖式地顯示，根據本發明的一說明性具體 實施例而形成之半導體結構，於各製造階段之剖面示意 _。 雖然本發明容許有種種的修改與替代形式，但是其特 定的具體實施例則已經藉由圖式中的實例來說明，其係並 且在此予以詳細說明。不過，應該理解的是，特定具體實 施例在此的說明並不打算將本發明限制於揭露出來的特別 型態，相反地，本發明反而包含位於附加申請專利範圍所 定義之發明精神與範圍内的所有變更、等同物以及替代 物。 100 半導體結構 1 0 1、2 0 1基板 1¾、2 1 0第一半導體元件 1 1 2、2 1 2主動區域 113 淺溝隔離物（S T I) 1 1 4 源極與汲極區域 1 1 5、 1 3 5、2 1 5、2 3 5 閘電極 1 1 6、 1 2 6、 1 3 6、 2 1 6 墊 >1 元件 1 1 8、 1 3 8、2 1 8 閘絕緣層9230S.ptd Page 21 200303603; Brief description of the drawings [Simplified description of the drawings] The present invention may be understood with reference to the following description in conjunction with the accompanying drawings, wherein the same reference symbols refer to the same elements, and wherein: FIG. 1a and FIG. The lb diagram shows a schematic cross-sectional view of a first and a second semiconductor element having a silicide portion formed in a conductive region, wherein the first and the second semiconductor element are manufactured according to a conventional conventional technology process; and Figures 2a to 2f diagrammatically show a semiconductor structure formed in accordance with an illustrative embodiment of the present invention, with schematic cross-sections at various manufacturing stages. Although the present invention allows various modifications and alternative forms, specific embodiments thereof have been described by way of example in the drawings, and they are described in detail herein. However, it should be understood that the description of specific specific embodiments herein is not intended to limit the present invention to the disclosed specific forms. On the contrary, the present invention instead encompasses the spirit and scope of the invention as defined by the scope of the additional patent application. All changes, equivalents, and replacements for. 100 Semiconductor structure 1 0 1, 2 0 1 Substrate 1¾, 2 1 0 First semiconductor element 1 1 2, 2 1 2 Active region 113 Shallow trench isolation (STI) 1 1 4 Source and drain regions 1 1 5, 1 3 5, 2 1 5, 2 3 5 Gate electrode 1 1 6, 1 2 6, 1 3 6, 2 1 6 Pad > 1 Element 1 1 8, 1 3 8, 2 1 8 Gate insulation
92308.pid 第22 1 200303603 圖式簡單說明 130 第 二 半 導 體 70 133> 213 233 134、 214 234 140 金 屬 層 200 半 導 體 結 構 240 第 一 金 屬 層 242 第 二 金 屬 層 250 抗 ik 劑 遮 罩 255 第 光 阻 遮 罩 13 2 主動區域 淺溝隔離物 源極與汲極區域 141 金屬矽化物區域 2 3 0 第二半導體元件 241 第一矽化物部份 2 4 3 第二矽化物部份 2 5 2、2 5 7邊牆部份92308.pid No. 22 1 200303603 Schematic description 130 Second semiconductor 70 133 > 213 233 134, 214 234 140 Metal layer 200 Semiconductor structure 240 First metal layer 242 Second metal layer 250 Anti-ik agent mask 255 No. photoresist Mask 13 2 Active area shallow trench isolation source and drain area 141 metal silicide area 2 3 0 second semiconductor element 241 first silicide portion 2 4 3 second silicide portion 2 5 2, 2 5 7 side wall section
92308.ptd 第23頁92308.ptd Page 23
Claims (1)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10208728A DE10208728B4 (en) | 2002-02-28 | 2002-02-28 | A method for producing a semiconductor element having different metal silicide regions |
| US10/260,926 US7217657B2 (en) | 2002-02-28 | 2002-09-30 | Semiconductor device having different metal silicide portions and method for fabricating the semiconductor device |
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| Publication Number | Publication Date |
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| TW200303603A true TW200303603A (en) | 2003-09-01 |
| TWI277174B TWI277174B (en) | 2007-03-21 |
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| TW92104156A TWI277174B (en) | 2002-02-28 | 2003-02-27 | Semiconductor device having different metal silicide portions and method for fabricating the semiconductor device |
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| Country | Link |
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| EP (1) | EP1479100A1 (en) |
| JP (1) | JP2005520341A (en) |
| CN (1) | CN100481333C (en) |
| AU (1) | AU2002365054A1 (en) |
| TW (1) | TWI277174B (en) |
| WO (1) | WO2003079424A1 (en) |
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| US7405112B2 (en) | 2000-08-25 | 2008-07-29 | Advanced Micro Devices, Inc. | Low contact resistance CMOS circuits and methods for their fabrication |
| JP4011024B2 (en) | 2004-01-30 | 2007-11-21 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
| KR101226653B1 (en) | 2006-06-28 | 2013-01-25 | 엘지디스플레이 주식회사 | An array sbstrate for LCD and method of fabricating thereof |
| JP5500784B2 (en) * | 2008-05-12 | 2014-05-21 | 信越半導体株式会社 | Multilayer silicon semiconductor wafer and method for producing the same |
| CN102571135B (en) * | 2012-02-15 | 2014-05-14 | 京信通信系统（中国）有限公司 | Radio frequency semi-integrated application device |
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| US4824544A (en) * | 1987-10-29 | 1989-04-25 | International Business Machines Corporation | Large area cathode lift-off sputter deposition device |
| JPH04188868A (en) * | 1990-11-22 | 1992-07-07 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPH04349660A (en) * | 1991-05-28 | 1992-12-04 | Toshiba Corp | Semiconductor devicce and its manufacture |
| US5352631A (en) * | 1992-12-16 | 1994-10-04 | Motorola, Inc. | Method for forming a transistor having silicided regions |
| JPH07235606A (en) * | 1994-02-22 | 1995-09-05 | Mitsubishi Electric Corp | Complimentary semiconductor device and manufacture thereof |
| US6020242A (en) * | 1997-09-04 | 2000-02-01 | Lsi Logic Corporation | Effective silicide blocking |
| US6133130A (en) * | 1998-10-28 | 2000-10-17 | United Microelectronics Corp. | Method for fabricating an embedded dynamic random access memory using self-aligned silicide technology |
| US6040606A (en) * | 1998-11-04 | 2000-03-21 | National Semiconductor Corporation | Integrated circuit structure with dual thickness cobalt silicide layers and method for its manufacture |
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2002
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- 2002-12-20 CN CNB028284178A patent/CN100481333C/en not_active Expired - Fee Related
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| WO2003079424A1 (en) | 2003-09-25 |
| CN1623221A (en) | 2005-06-01 |
| TWI277174B (en) | 2007-03-21 |
| CN100481333C (en) | 2009-04-22 |
| JP2005520341A (en) | 2005-07-07 |
| EP1479100A1 (en) | 2004-11-24 |
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