EP1385199A1 - Verfahren zur Herstellung von Dünnfilmelementen für Solarzellen oder SOI Anwendungen - Google Patents

Verfahren zur Herstellung von Dünnfilmelementen für Solarzellen oder SOI Anwendungen Download PDF

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Publication number
EP1385199A1
EP1385199A1 EP02447146A EP02447146A EP1385199A1 EP 1385199 A1 EP1385199 A1 EP 1385199A1 EP 02447146 A EP02447146 A EP 02447146A EP 02447146 A EP02447146 A EP 02447146A EP 1385199 A1 EP1385199 A1 EP 1385199A1
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EP
European Patent Office
Prior art keywords
substrate
thin film
semiconductor layer
layer
fabrication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02447146A
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English (en)
French (fr)
Inventor
Chetan Singh Solanti
Renat Bilyalov
Jef Poortmans
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Interuniversitair Microelektronica Centrum vzw IMEC
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Interuniversitair Microelektronica Centrum vzw IMEC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Interuniversitair Microelektronica Centrum vzw IMEC filed Critical Interuniversitair Microelektronica Centrum vzw IMEC
Priority to EP02447146A priority Critical patent/EP1385199A1/de
Priority to AT03447188T priority patent/ATE473518T1/de
Priority to EP03447188A priority patent/EP1385200B1/de
Priority to ES03447188T priority patent/ES2347141T3/es
Priority to DE60333245T priority patent/DE60333245D1/de
Priority to US10/627,576 priority patent/US7022585B2/en
Publication of EP1385199A1 publication Critical patent/EP1385199A1/de
Priority to US11/392,372 priority patent/US20060184266A1/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer

Definitions

  • the present invention is related to microelectronics and more particular to the field of thin film device applications such as silicon-on-insulator (SOI) structures or solar cells in particular. Furthermore, the present invention is relating to a manufacturing method of such devices.
  • SOI silicon-on-insulator
  • the silicon wafers found in existing semiconductor devices usually have a thickness of several hundred microns.
  • the electrically active domain of a wafer is limited to its surface, in fact, less than a few microns of thickness is needed.
  • the remained part of a wafer is used as substrate.
  • This excess of material causes both a rise in power consumption and a fall in the operating speed of the device.
  • the SOI wafers incorporate an insulating layer between its very thin (less than a few microns) active domain and its much thicker substrate. The substrate is isolated and can thus no longer deteriorate the speed or efficiency of the active layer.
  • Silicon on insulator technology involves the formation of a monocrystalline silicon semi-conductor layer on an insulating material such as silicon oxide.
  • Solar cells usually comprise on the top of a silicon wafer an active surface in the form of a thin film device deposited on said silicon wafer.
  • the preparation of a porous semiconductor layer on a substrate as a sacrificial layer for solar cell usually comprises several steps such as at least a porous semiconductor layer formation on an original substrate, epitaxial silicon layer deposition, device fabrication on said substrate and separation of the device from the original substrate and transfer to a foreign substrate in order to possibly re-use the original substrate.
  • This sequence is largely illustrated in the documents US-B- 6 258 698 (Iwasaki et al, Canon), US-B- 6 211 038 (Nakagawa et al, Canon) and US-B- 6 326 280 (Tayanaka, Sony Corporation).
  • a lift-off process is described in EP-A-1132952 where it is shown that a thin porous silicon film of 5 to 50 ⁇ m can be separated from the silicon substrate whereon it is deposited. In such case, the substrate can be re-used many times for getting new porous silicon films.
  • Other possible techniques for thin film separation are ion implantation or wafer bonding techniques.
  • the present invention aims to provide a method for the preparation of thin-film devices for structures being highly efficient and low-cost.
  • Examples of such structures are silicon-on-insulator (SOI) structures or solar cells.
  • SOI silicon-on-insulator
  • the use of thin film in SOI structures in general and in solar cells in particular allows the reduction of the amount of material consumed per structure, which significantly reduces the high costs of the active substrate, while the quality of the film provides the good characteristics of the whole device.
  • the present invention relates to a method for manufacturing a semiconductor device, said method comprising at least the following subsequent steps:
  • the step of the fabrication of the device comprises the transfer of said thin film to a dummy support whereon the deposition of an active semiconductor layer is performed on said thin film, optionally followed by the fabrication of a contacted device on said active semiconductor layer.
  • the lift-off process according to the present invention is achieved by immersing the substrate in a HF solution in concentration between 12 and 35% and using current densities between 50 and 250 mA/cm 2 without changing any other parameters.
  • the deposition of the active layer is performed by epitaxial Chemical Vapour Deposition.
  • the porous semiconductor layer according to the present invention can be a crystalline or amorphous semiconductor material including silicone germanium, III-V materials such as GaAs, InGaAs and semiconducting polymers.
  • the foreign substrate comprises a low-cost substrate such as glass, polymeric material.
  • Figs. 1 (a) and (b) represent two manufacturing sequences of the prior art for the fabrication of solar cells (PSI process and ELTRAN® process).
  • Fig. 2 represents the manufacturing sequence of the present invention for the fabrication of a solar cell.
  • Fig. 3 represents the first and the second steps of the manufacturing sequence of the present invention where pore branching results in increased lateral porosity followed by the film separation (lift-off process). This process is described in detail in EP-A-1132952.
  • Fig. 4 represents a picture of the free-standing thin film device after peeling and before the transfer to the support.
  • Fig. 5 represents the set-up used for the porous semiconductor layer formation according to EP-A-1132952.
  • Fig. 6 is representing the dummy substrate to hold the porous semiconductor film during the epitaxial layer deposition.
  • Fig.7 represents an adhesived device on a foreign substrate
  • SOI silicon on insulator
  • a particular embodiment of the present invention is related to the fabrication of solar cells which are described in details in Figs. 1 and 2.
  • Fig. 1 The sequence of the prior art process is described in Fig. 1 while Fig. 2 represents the manufacturing process for the fabrication of a solar cell according to the present invention.
  • Fig. 1 represents according to the prior art the preparation of a porous silicon layer (double layer 1+2) on a substrate 3 (step 1 in Fig. 1) followed by an epitaxial silicon layer 7 deposition (step 2 in Fig. 1), and the device 6 fabrication of said substrate (step 3 in Fig. 1) and finally the separation of said device from the substrate 3 and the transfer to a foreign substrate 4 in order to possibly re-use the original substrate (step 4 in Fig. 1).
  • Fig. 2 is representing the sequence of the method for manufacturing a solar cell according to the present invention.
  • Said method comprises as step 1 the formation of a porous semiconductor layer (double layer 1+2) in the form of a thin-film 10 on an original substrate 3, said formation being immediately followed by the separation of said thin-film 10 by a lift-off process from said original substrate 3 (step 2), the transfer of said thin film 10, and the preparation of the device 6 including epitaxial silicon layer 7 deposition and contact fabrication (step 3). Finally the transfer of the whole device to a foreign substrate 4 in order to realise the solar cell (step 4).
  • the pore formation starts at a certain position, it goes straight down in the semiconductors as shown in Figure 3.
  • the reaction occurs at the bottom of the pore.
  • Porosity of the layer increases with decrease in the concentration of HF in solution. Although the initial F-containing solution is not replaced, an in-situ change of concentration is obtained. Therefore, as we go deeper, porosity of the layer increases.
  • the porosity gradient occurs from the point where the availability of the fluoride ion is affected by the diffusion through the pores.
  • the fluoride ion concentration at the point of reaction reduces to a very low level as compared to the surface concentration. This results in the shift of the point of reaction to a slightly higher level because of very high resistance of the lowest part of the pore. This shift in the reaction gives rise to the formation of the branches of the pores.
  • one hydrogen molecule results as a product of the electrochemical etching. The hydrogen molecules exert force on the walls of the pores. At some points, because of the branching of pores, the walls become very thin and not able to withstand the hydrodynamic pressure exerted by the hydrogen molecules. This results in horizontal cracks in the layer. The presence of sufficient horizontal cracks results in the separation of the layer from the substrate.
  • the approach of the present invention opens new possibilities in the formation of porous layers in form of thin films by proposing a new sequence for the preparation of free standing thin-film devices to be used for SOI structures or solar cells in particular.
  • porous semiconductor layers called hereunder as PSL could be crystalline and amorphous semiconductor material including silicon, germanium, III-V materials such as Ga As, InGaAs and semiconducting polymers.
  • a double porosity layer is prepared by electrochemical etching and by changing one of the formation parameters such as the electrolytic current density or the HF concentration of the electrolytic solution.
  • the parameters of the porous silicon formation remain unchanged and the separation is not reached by changing the current density of the electrochemical solution but by allowing the current to flow for sufficient time.
  • Fig. 5 is representing the set-up used for the formation of the porous semiconductor layer (PSL).
  • the platinum electrode 8 which is resistant against hydrofluoric acid, acts as a negative electrode.
  • the bottom plate 13 e.g. stainless steel plate
  • the rubber ring 12 prevents the outflow of the solution from the contact area of the Teflon® beaker 9 and wafer substrate 3.
  • the rubber ring is kept under pressure by the beaker 9, which in turn is pressurised by a stainless steel threaded ring (not shown).
  • the film obtained is immediately separated from the substrate by a list of processes and then the fabrication of the device for the solar cell is carried out without permanently transferring the film on other substrates.
  • the fabrication of the device itself is performed by transferring the lift-off film 10 to a dummy support 17 in order to realise the epitaxial deposition (see Fig. 6).
  • the present invention discloses a very attractive method for the preparation of low-cost, high quality structures, such as SOI structures or solar cells.
  • Figure 7 is representing the final structure such as a solar cell whereon the active device 6 has been attached by an adhesive 15 on the low-cost substrate 4.
  • the processing is more simple and provides a total freedom in terms of processing parameters, compared to the conventional techniques, e.g. using porous silicon sacrificial layers for thin film transfer processes.
  • the transfer process according to the present invention occurs directly after the preparation of the porous silicon film on a dummy substrate which makes an intermediate layer as in the prior art useless.
  • Such intermediate layers e.g. hydrogen silsequioxane
  • similar requirements are necessary.
  • no transfer to the real substrate is performed and therefore no intermediate layer is used.
  • the handling of the thin layer (film) is the biggest challenge but this difficulty is compensated by fewer constraints due to the reduced number of layers and more freedom in terms of process parameters.
  • the monocrystalline Si thin film solar cells can be attached to any substrate (even flexible substrates) and the handling of this film remains the most critical point.
  • the present invention discloses a method able to transfer a thin porous semiconductor film, with a high quality epitaxial layer on the top of said porous semiconductor layer, onto a foreign substrate.
  • the resulting device can be used for the following applications:
  • a 20 ⁇ m porous silicon film is separated from highly doped P-type, ⁇ 100> silicon by electrochemical etching in an electrolyte bath containing HF. After annealing of a porous silicon film at 1050°C in H 2 , P-type silicon layer with 20 ⁇ m thickness is deposited using conventional CVD. In the first trial, a simple two side-contacted solar cell without any photolithography is applied for such free-standing film. An efficiency of 10.6% is achieved for a small area cell (1 cm 2 ). The other cell parameters are as follows: V oc - 581.3 mV, I sc - 30.29 mA/cm 2 and FF - 60.1 %. IQE analysis reveals that the spectral response of free-standing film with Al backside metallization is significantly increased in the infrared wavelength region as compared to the cell transferred to conventional ceramic substrates.
  • the process of the present invention comprises five steps of fabrication:
  • Porous silicon formation is carried out in a conventional PTFE (Teflon) cell with a silicon sample as anode and a platinum counter electrode as shown in Fig. 1.
  • the electrolyte contained of HF and acetic acid is used.
  • Porous silicon formation is carried out at current density ranging from 50 to 250 mA/cm 2 and HF concentration ranging from 12 to 35 vol % at room temperature under background illumination.
  • the porous semiconductor layer is not really attached to the dummy substrate but fixed in between two supports to give mechanical strength to the porous semiconductor layer.
  • Deposition of active layer is carried out with and without pre-annealing of porous layer in H 2 ambient at 1050°C for 30 min.
  • the aim is to convert the porous silicon into quasi monocrystalline silicone (QMS) which provides a good seeding layer for a CVD layer deposition.
  • An active layer of 10-30 microns is deposited using dichlorosilane (DCS) or trichlorosilane (TCS) at 1050°C and 1130°C respectively.
  • the porous silicon film is kept (no permanent bonding) between two silicon substrates, with the window on the top substrate for CVD deposition.
  • One side contacted and two side contacted solar cell are fabricated while keeping the Porous-Silicon+Epi essentially free-standing (no permanent bonding to any substrate). Efficiency of 10.6% has been achieved on 1 cm 2 area.
EP02447146A 2002-07-24 2002-07-24 Verfahren zur Herstellung von Dünnfilmelementen für Solarzellen oder SOI Anwendungen Withdrawn EP1385199A1 (de)

Priority Applications (7)

Application Number Priority Date Filing Date Title
EP02447146A EP1385199A1 (de) 2002-07-24 2002-07-24 Verfahren zur Herstellung von Dünnfilmelementen für Solarzellen oder SOI Anwendungen
AT03447188T ATE473518T1 (de) 2002-07-24 2003-07-18 Verfahren zur herstellung von dünnschichtbauelementen für solarzellen oder soi- anwendungen
EP03447188A EP1385200B1 (de) 2002-07-24 2003-07-18 Verfahren zur Herstellung von Dünnschichtbauelementen für Solarzellen oder SOI-Anwendungen
ES03447188T ES2347141T3 (es) 2002-07-24 2003-07-18 Procedimiento para la elaboracion de dispositivos de pelicula delgada destinados para celulas solares o aplicaciones soi.
DE60333245T DE60333245D1 (de) 2002-07-24 2003-07-18 Verfahren zur Herstellung von Dünnschichtbauelementen für Solarzellen oder SOI-Anwendungen
US10/627,576 US7022585B2 (en) 2002-07-24 2003-07-24 Method for making thin film devices intended for solar cells or silicon-on-insulator (SOI) applications
US11/392,372 US20060184266A1 (en) 2002-07-24 2006-03-29 Method for making thin film devices intended for solar cells or silicon-on-insulator (SOI) applications

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02447146A EP1385199A1 (de) 2002-07-24 2002-07-24 Verfahren zur Herstellung von Dünnfilmelementen für Solarzellen oder SOI Anwendungen

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EP1385199A1 true EP1385199A1 (de) 2004-01-28

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US (2) US7022585B2 (de)
EP (1) EP1385199A1 (de)
AT (1) ATE473518T1 (de)
DE (1) DE60333245D1 (de)
ES (1) ES2347141T3 (de)

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US20060184266A1 (en) 2006-08-17
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