WO2006131177A3 - Verfahren zur herstellung von saatschichten zur abscheidung von halbleitermaterial - Google Patents

Verfahren zur herstellung von saatschichten zur abscheidung von halbleitermaterial Download PDF

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Publication number
WO2006131177A3
WO2006131177A3 PCT/EP2006/004171 EP2006004171W WO2006131177A3 WO 2006131177 A3 WO2006131177 A3 WO 2006131177A3 EP 2006004171 W EP2006004171 W EP 2006004171W WO 2006131177 A3 WO2006131177 A3 WO 2006131177A3
Authority
WO
WIPO (PCT)
Prior art keywords
layers
semiconductor material
seed layers
depositing
producing seed
Prior art date
Application number
PCT/EP2006/004171
Other languages
English (en)
French (fr)
Other versions
WO2006131177A2 (de
Inventor
Philipp Johannes Rostan
Juergen Werner
Christopher Berge
Original Assignee
Univ Stuttgart
Philipp Johannes Rostan
Juergen Werner
Christopher Berge
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Stuttgart, Philipp Johannes Rostan, Juergen Werner, Christopher Berge filed Critical Univ Stuttgart
Publication of WO2006131177A2 publication Critical patent/WO2006131177A2/de
Publication of WO2006131177A3 publication Critical patent/WO2006131177A3/de

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Classifications

    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00—Electrolytic etching or polishing
    • C25F3/02—Etching
    • C25F3/12—Etching of semiconducting materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3063—Electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

Es wird ein Verfahren zur Herstellung von Saatschichten zur Abscheidung eines Halbleitermaterials angegeben, bei dem ein monokristallines Halbleitersubstrat (12) in einer wässrigen Lösung mit F-Ionen elektrochemisch geätzt wird. Dabei wird eine Folge von abwechselnd niederporösen und hochporösen Schichten erzeugt, die sämtlich am Halbleitersubstrat (12) anhaften. Nach Beendigung des Ätzvorgangs kann die Schichtenfolge durch Eintauchen in Wasser nach und nach abgelöst werden. Hierbei ergibt sich eine Mehrzahl von niederporösen Schichten, die als Saatschichten für eine Epitaxiebehandlung zur Abscheidung von monokristallinem Halbleitermaterial auf den Saatschichten genutzt werden können.
PCT/EP2006/004171 2005-06-06 2006-05-04 Verfahren zur herstellung von saatschichten zur abscheidung von halbleitermaterial WO2006131177A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102005027196 2005-06-06
DE102005027196.0 2005-06-06

Publications (2)

Publication Number Publication Date
WO2006131177A2 WO2006131177A2 (de) 2006-12-14
WO2006131177A3 true WO2006131177A3 (de) 2007-03-08

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2006/004171 WO2006131177A2 (de) 2005-06-06 2006-05-04 Verfahren zur herstellung von saatschichten zur abscheidung von halbleitermaterial

Country Status (1)

Country Link
WO (1) WO2006131177A2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009024613A1 (de) * 2009-06-12 2010-12-23 Institut Für Solarenergieforschung Gmbh Verfahren zum Bilden von dünnen Halbleiterschichtsubstraten sowie Verfahren zum Herstellen eines Halbleiterbaulements, insbesondere einer Solarzelle, mit einem solchen Halbleiterschichtsubstrat
DE102009053262A1 (de) * 2009-11-13 2011-05-19 Institut Für Solarenergieforschung Gmbh Verfahren zum Bilden von dünnen Halbleiterschichtsubstraten sowie Verfahren zum Herstellen eines Halbleiterbauelements, insbesondere einer Solarzelle, mit einem solchen Halbleiterschichtsubstrat

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2708630A1 (fr) * 1993-08-03 1995-02-10 France Telecom Matériau semi-conducteur à porosité variable et son procédé de fabrication.
EP0993029A2 (de) * 1998-09-10 2000-04-12 Universität Stuttgart , Institut für Physikalische Elektronik Verfahren zur Herstellung kristalliner Halbleiterschichten
US6376859B1 (en) * 1998-07-29 2002-04-23 Texas Instruments Incorporated Variable porosity porous silicon isolation
EP1385199A1 (de) * 2002-07-24 2004-01-28 IMEC vzw, Interuniversitair Microelectronica Centrum vzw Verfahren zur Herstellung von Dünnfilmelementen für Solarzellen oder SOI Anwendungen

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2708630A1 (fr) * 1993-08-03 1995-02-10 France Telecom Matériau semi-conducteur à porosité variable et son procédé de fabrication.
US6376859B1 (en) * 1998-07-29 2002-04-23 Texas Instruments Incorporated Variable porosity porous silicon isolation
EP0993029A2 (de) * 1998-09-10 2000-04-12 Universität Stuttgart , Institut für Physikalische Elektronik Verfahren zur Herstellung kristalliner Halbleiterschichten
EP1385199A1 (de) * 2002-07-24 2004-01-28 IMEC vzw, Interuniversitair Microelectronica Centrum vzw Verfahren zur Herstellung von Dünnfilmelementen für Solarzellen oder SOI Anwendungen

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
SOLANKI C S ET AL: "Porous silicon layer transfer processes for solar cells", SOLAR ENERGY MATERIALS AND SOLAR CELLS, ELSEVIER SCIENCE PUBLISHERS, AMSTERDAM, NL, vol. 83, no. 1, 1 June 2004 (2004-06-01), pages 101 - 113, XP004507474, ISSN: 0927-0248 *
VINCENT G: "OPTICAL PROPERTIES OF POROUS SILICON SUPERLATTICES", APPLIED PHYSICS LETTERS, AIP, AMERICAN INSTITUTE OF PHYSICS, MELVILLE, NY, US, vol. 64, no. 18, 2 May 1994 (1994-05-02), pages 2367 - 2369, XP000440967, ISSN: 0003-6951 *

Also Published As

Publication number Publication date
WO2006131177A2 (de) 2006-12-14

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