EP1284046B1 - Circuit oscillateur - Google Patents

Circuit oscillateur Download PDF

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Publication number
EP1284046B1
EP1284046B1 EP01936358A EP01936358A EP1284046B1 EP 1284046 B1 EP1284046 B1 EP 1284046B1 EP 01936358 A EP01936358 A EP 01936358A EP 01936358 A EP01936358 A EP 01936358A EP 1284046 B1 EP1284046 B1 EP 1284046B1
Authority
EP
European Patent Office
Prior art keywords
output
oscillator circuit
transistors
coupled
circuit according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP01936358A
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German (de)
English (en)
Other versions
EP1284046A1 (fr
Inventor
Andreas Rusznyak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
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Filing date
Publication date
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Publication of EP1284046A1 publication Critical patent/EP1284046A1/fr
Application granted granted Critical
Publication of EP1284046B1 publication Critical patent/EP1284046B1/fr
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/20—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator
    • H03B5/24—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
    • H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
    • H03B5/36—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
    • H03B5/364—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device the amplifier comprising field effect transistors

Definitions

  • This invention relates to oscillator circuits for use in integrated circuits.
  • Pierce-type two-pin oscillator One of the most frequently-used analog circuits in today's IC's is the Pierce-type two-pin oscillator. Typically, this type of oscillator is used to generate clock signals in microprocessors and other integrated systems.
  • Such an oscillator is typically formed by a resonator embedded between two capacitors connected to ground and between the input and output of an inverter.
  • FIG. 1 shows the schematic circuit of such an oscillator.
  • This oscillator is of simple construction, but presents several disadvantages:
  • FIG. 2 shows a prior art circuit known from U.S. patent no. 4,405,906 which avoids the above mentioned drawbacks by regulation of the oscillation amplitude.
  • this known circuit two DC bias current sources polarize the driver transistors, whereas the currents from these current sources are sunk to the supply rails across transistors connected between the driver transistors common drain and their gate.
  • This known circuit presents two important drawbacks. Firstly, well-controlled DC current sources are needed to polarize correctly the driver transistors. Secondly, a start-up circuit is needed to ensure that both driver transistors remain in saturation when the circuit is powered on.
  • an oscillator circuit as claimed in claim 1.
  • a Pierce-type two-pin oscillator 100 is formed by a resonator Q embedded between two capacitors C1 and C2.
  • the capacitors are commonly connected at terminals remote from the resonator Q to a voltage node VSS.
  • a CMOS transistor pair MP, MN have their source and drain electrodes connected in series between voltage nodes VDDA and VSS.
  • the CMOS transistors MP and MN form an inverter whose input IN is connected to the transistors' gate electrodes and whose output OUT is connected to a point between the transistors' current electrodes.
  • the input IN and output OUT are connected respectively to the capacitors C1 and C2 at terminals remote from the voltage node VSS.
  • a resistance R0 is connected between the input IN and output OUT.
  • the known Pierce-type two-pin oscillator 100 has the advantage of simple construction, it presents several disadvantages: (i) the amplitude at the output is limited by non-linearities generating harmonics which may cause electro-magnetic coupling (EMC) problems; (ii) the amplitude across the resonator Q is high, resulting in high power dissipation in the resonator, limiting its long-term frequency stability; (iii) since both transistors MP and MN constituting the inverter conduct simultaneously during a large portion of the period of oscillation, the oscillator has high current consumption; and (iv) a high impedance current path R is needed between the input IN and output OUT of the inverter to ensure its correct biasing, and leakage of external components connected to this path may alter operating conditions of the oscillator.
  • EMC electro-magnetic coupling
  • a known oscillator circuit 200 avoids these disadvantages.
  • the oscillator circuit 200, resonator Q, transistors T1 and T2 and capacitor C2 in are analogous to respectively the resonator Q, the transistors MP and MN, and the capacitor C2 in FIG. 1.
  • the capacitors C3' and C4' (together with capacitors C3 and C4) in FIG. 2 are analogous to the capacitor C1 in FIG. 1.
  • nodes a and b serve as input and output nodes respectively.
  • the oscillator circuit 200 avoids the above-discussed drawbacks of the oscillator circuit 100 by regulation of the oscillation amplitude.
  • the oscillation amplitude is regulated by two DC bias current sources (formed by transistors T3 and T4 respectively) which polarize the driver transistors T1 and T2, whereas the currents from these current sources are sunk to the supply rails P and M across transistors T5, T6 and T8 connected between the driver transistors' common drain and their gate.
  • the oscillator circuit 200 avoids the disadvantages of the oscillator circuit 100, the oscillator circuit 200 has two important drawbacks. Firstly, well-controlled DC current sources T3 and T4 are needed to polarize correctly the driver transistors T1 and T2. Secondly, a start-up circuit (not shown) is needed to ensure that both driver transistors remain in saturation when the circuit is powered on.
  • an oscillator circuit 300 exhibits the above-discussed advantages of the known circuits of FIG. 1 and FIG. 2, but avoids their above-discussed disadvantages.
  • a resonator Q is embedded between two capacitors C1 and C2.
  • the capacitors are commonly connected at terminals remote from the resonator Q to a voltage node VSS.
  • a CMOS transistor pair MP, MN have their source and drain electrodes connected in series between voltage nodes VDDA and VSS.
  • the CMOS transistors MP and MN form an inverter whose input IN is connected to the transistors' gate electrodes via respective capacitors CP and CN, and whose output OUT is connected to a point between the transistors' current electrodes.
  • the input IN and output OUT are connected respectively to the capacitors C1 and C2 at terminals remote from the voltage node VSS.
  • the gate electrodes of the transistors MP and MN are connected via two series-connected resistances PX and NX. A point between the resistances PX and NX is connected to the output OUT.
  • the gate electrodes of the transistors MP and MN are connected respectively via diode-connected CMOS transistors MND and MNP to node NF, which is connected to the output OUT via an amplifier A.
  • the correct biasing condition of the driver transistors MN and MP is ensured by high impedance paths through the transistors NX and PX between the output of these driver transistors and their gates. In this way at start-up both driver transistors MN and MP are in saturation.
  • the transistors MND and MPD connected in diode configuration, accomplish the amplitude regulation in a similar way to that in the prior art circuit of FIG. 1.
  • the transistors MND and MPD connected between the gates of the driver transistors MN and MP and the node NF, are able to sink the current sourced by the high impedance paths when the amplitude on the oscillator output OUT rises. In steady state condition, the charge transferred periodically through the transistors MND and MPD is equal to that provided by the high impedance paths through the resistances NX and PX respectively.
  • the oscillator circuit 300 of FIG. 3 exhibits the above-discussed advantages of the known circuits of FIG. 1 and FIG. 2, but avoids their above-discussed disadvantages.
  • FIG. 4 shows a practical embodiment of the oscillator circuit 300 of FIG. 3.
  • the high impedance resistances PX and NX of the oscillator circuit 300 of FIG. 3 between the output of the driver transistors MPD, MND and their gates are realized by adequately controlled, long channel CMOS transistors MPX and MNX respectively.
  • connections to the transistors MPD and MND are arranged as follows.
  • CMOS transistors MP1 and MN1 and capacitors CP2 and CN2 are connected in series.
  • the transistor MP1 has its gate electrode connected to its source electrode (at a node PF) and to the drain electrode of the driver transistor MPD.
  • a capacitor CP1 is connected between the source and drain electrodes of the transistor MP1.
  • the transistor MN1 has its gate electrode connected to its source electrode (at a node NF) and to the drain electrode of the driver transistor MND.
  • a capacitor CN1 is connected between the source and drain electrodes of the transistor MN1.
  • amplitude regulation occurs by means of the charge stored in capacitors CN2, CP2 and transferred to nodes NG, PG. It will be understood that in this embodiment there is no need to build amplifiers. Current consumption of the complete circuit under the conditions as already defined above is 0.25mA when the voltage on IN and on OUT oscillates between 10% and 90% of the supply voltage.
  • FIG. 5 shows another practical embodiment of the oscillator circuit 300 of FIG. 3.
  • connections to the transistors MPD and MND are arranged as follows.
  • CMOS transistors MPX and MNX are connected in series, a point between the transistors MPX and MNX being connected to a point between the driver transistors MP and MN.
  • CMOS transistors MPX and MNX are connected in series, a point between the transistors MNA0 and MPA0 forming a node DIV.
  • Transistors MPA1 and MPA2 have their gate electrodes commonly connected to the node DIV, and have their source electrodes commonly coupled to the voltage node VDDA.
  • the transistor MPA1 has its drain electrode connected to the node DIV.
  • the transistor MPA2 has its drain electrode connected to the node NC.
  • Transistors MNA1 and MNA2 have their gate electrodes commonly connected to the node DIV, and have their source electrodes commonly coupled to the voltage node VSS.
  • the transistor MNA1 has its drain electrode connected to the node DIV.
  • the transistor MNA2 has its drain electrode connected to the node PC.
  • the growing voltage on the output terminal OUT causes transistors MND, MPD to open and so to sink the current provided by transistors MNX and MPX, respectively.
  • control voltage of transistors MNX, MPX representing high-impedance connections between the oscillator output and the gates of the driver transistors, is adjusted to be at the DC voltage on the output terminal OUT at start-up plus the threshold voltage of transistors MNX, MPX. In this way, the currents provided by these transistors track process, temperature and supply voltage variations, so as to counter performance variations elsewhere in the circuit.
  • transistors MNX and MPX can be stabilized by means of an auxiliary circuit (not shown) generating a DC current proportional to the value of an integrated capacitor, to the supply voltage and to the frequency of the oscillator itself.
  • a further feature of the oscillator circuit 500 of FIG. 5 is the incorporation of a resistive transmission gate, formed by CMOS transistors TG1 and TG2, connected between the input IN and output OUT.
  • the gate electrodes of the transistors TG1 and TG2 are connected respectively to supply voltages VDDA and VSS. It will be understood that the effect of this transmission gate is to define the voltage on the input at low frequencies. It will further be understood that, if desired, such a transmission gate could be incorporated into the oscillator circuit 300 of FIG. 3 and/or the oscillator circuit 400 of FIG. 4.

Landscapes

  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
  • Oscillators With Electromechanical Resonators (AREA)

Claims (11)

  1. Montage oscillateur comprenant :
    une entrée et une sortie disposées en vue de la connexion d'un résonateur entre elles ;
    un onduleur comprenant un premier transistor d'attaque et un second transistor d'attaque couplés en série via ladite sortie ;
    un dispositif de polarisation comprenant un premier élément de polarisation couplé entre ladite sortie et une électrode de commande du premier transistor d'attaque pour polariser le premier transistor d'attaque, et un second élément de polarisation couplé entre ladite sortie et l'électrode de commande du second transistor d'attaque pour polariser le second transistor d'attaque ;
    un premier dispositif limiteur couplé entre l'électrode de commande du dit premier transistor d'attaque et un premier noeud pour recevoir un signal représentatif du signal à la sortie, et un second dispositif limiteur couplé entre l'électrode de commande du dit second transistor d'attaque et un second noeud pour recevoir un signal représentatif du signal à la sortie,
    les entrées de commande du premier et du second transistor d'attaque étant couplées par capacité à l'entrée.
  2. Montage oscillateur selon la revendication 1, comprenant de plus un dispositif amplificateur dont une entrée est couplée à la sortie et dont une sortie est couplée aux noeuds pour recevoir un signal représentatif du signal à la sortie.
  3. Montage oscillateur selon la revendication 1, comprenant de plus :
    un premier dispositif capacitif couplé entre la sortie et ledit premier noeud pour recevoir un signal représentatif du signal à la sortie ; un premier dispositif de définition de courant pour définir le courant circulant dans le premier dispositif limiteur ; un second dispositif capacitif couplé entre la sortie et ledit second noeud pour recevoir un signal représentatif du signal à la sortie ; et un second dispositif de définition de courant pour définir le courant circulant dans le second dispositif limiteur.
  4. Montage oscillateur selon la revendication 3, où le premier dispositif de définition de courant comprend un transistor monté en diode et un condensateur entre le premier noeud pour recevoir un signal représentatif du signal à la sortie et un premier noeud d'alimentation, et où le second dispositif de définition de courant comprend un transistor monté en diode et un condensateur entre le second noeud pour recevoir un signal représentatif du signal à la sortie et un second noeud d'alimentation.
  5. Montage oscillateur selon l'une quelconque des revendications précédentes, où le dispositif de polarisation comprend des transistors résistifs munis d'électrodes de commande.
  6. Montage oscillateur selon la revendication 5, où les électrodes de commande des transistors résistifs du premier et du second élément de polarisation sont couplées respectivement au premier et au second noeud d'alimentation.
  7. Montage oscillateur selon la revendication 5, où les électrodes de commande des transistors résistifs sont couplées à un dispositif fournissant des tensions de commande pour s'assurer que les transistors résistifs sont conducteurs lorsque la tension sur les électrodes de commande des transistors d'attaque est inférieure à une tension d'amorçage sur la sortie.
  8. Montage oscillateur selon la revendication 7, où le dispositif fournissant des tensions de commande comprend :
    un dispositif pour fournir une tension représentative de la tension d'amorçage et des tensions représentatives des tensions de seuil du dispositif de polarisation, et un dispositif pour générer les tensions de commande à partir de celles-ci.
  9. Montage oscillateur selon l'une quelconque des revendications précédentes, comprenant de plus une porte de transmission résistive couplée entre l'entrée et la sortie pour définir la tension sur la sortie à basses fréquences.
  10. Montage oscillateur selon la revendication 9, où la porte de transmission résistive comprend des électrodes de commande qui sont couplées respectivement au premier et au second noeud d'alimentation.
  11. Montage oscillateur selon l'une quelconque des revendications précédentes, où les transistors sont des transistors CMOS.
EP01936358A 2000-05-12 2001-05-11 Circuit oscillateur Expired - Lifetime EP1284046B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0011558A GB2362276A (en) 2000-05-12 2000-05-12 A low power clock oscillator with regulated amplitude
GB0011558 2000-05-12
PCT/EP2001/005481 WO2001086803A1 (fr) 2000-05-12 2001-05-11 Circuit oscillateur

Publications (2)

Publication Number Publication Date
EP1284046A1 EP1284046A1 (fr) 2003-02-19
EP1284046B1 true EP1284046B1 (fr) 2004-06-30

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP01936358A Expired - Lifetime EP1284046B1 (fr) 2000-05-12 2001-05-11 Circuit oscillateur

Country Status (9)

Country Link
US (1) US6759914B2 (fr)
EP (1) EP1284046B1 (fr)
JP (1) JP2003533115A (fr)
KR (1) KR100835130B1 (fr)
CN (1) CN1178377C (fr)
AU (1) AU2001262287A1 (fr)
DE (1) DE60104111T2 (fr)
GB (2) GB2362276A (fr)
WO (1) WO2001086803A1 (fr)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004096711A (ja) 2002-07-10 2004-03-25 Seiko Epson Corp 発振回路、電子機器、時計
US7123113B1 (en) * 2004-06-11 2006-10-17 Cypress Semiconductor Corp. Regulated, symmetrical crystal oscillator circuit and method
US7183868B1 (en) 2004-09-09 2007-02-27 Sandia Corporation Triple inverter pierce oscillator circuit suitable for CMOS
US7205823B2 (en) * 2005-02-23 2007-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. Oscillating buffer with single gate oxide devices
US7859355B2 (en) * 2005-03-24 2010-12-28 Cypress Semiconductor Corporation Regulated capacitive loading and gain control of a crystal oscillator during startup and steady state operation
US8035455B1 (en) 2005-12-21 2011-10-11 Cypress Semiconductor Corporation Oscillator amplitude control network
US7902933B1 (en) 2006-03-29 2011-03-08 Cypress Semiconductor Corporation Oscillator circuit
US7639097B2 (en) 2007-10-11 2009-12-29 Freescale Semiconductor, Inc. Crystal oscillator circuit having fast start-up and method therefor
KR200449528Y1 (ko) * 2010-05-10 2010-07-20 백민규 우산 탈수장치
JP5771489B2 (ja) * 2011-09-15 2015-09-02 ルネサスエレクトロニクス株式会社 半導体装置
US8957740B2 (en) * 2013-03-14 2015-02-17 Intel Mobile Communications GmbH Low power oscillator with negative resistance boosting
CN104104331B (zh) * 2013-04-15 2018-12-14 深圳先进技术研究院 跨导增强电路单元及晶体振荡器电路
US9007138B2 (en) 2013-05-31 2015-04-14 Freescale Semiconductor, Inc. Oscillator with startup circuitry
CN104038156B (zh) * 2014-06-12 2017-01-11 珠海市杰理科技股份有限公司 晶体振荡器
JP6442262B2 (ja) * 2014-12-09 2018-12-19 エイブリック株式会社 電圧検出回路
CN108449083B (zh) * 2018-02-27 2021-07-09 博流智能科技（南京）有限公司 一种自适应易启动的振荡器幅度控制电路

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2262782C2 (de) 1972-12-21 1975-01-30 Siemens Ag, 1000 Berlin Und 8000 Muenchen MH komplementären Transistoren in Gegentaktschaltung aufgebauter Oszillator
CH893373A4 (fr) 1973-06-20 1977-06-15
US4211985A (en) * 1975-09-03 1980-07-08 Hitachi, Ltd. Crystal oscillator using a class B complementary MIS amplifier
JPS5855685B2 (ja) * 1975-09-03 1983-12-10 株式会社日立製作所 ゾウフクカイロ
US4095195A (en) * 1977-03-25 1978-06-13 Kabushiki Kaisha Meidensha Low power dissipation crystal oscillator
JPS5484958A (en) 1977-11-22 1979-07-06 Seiko Epson Corp Crystal oscillation circuit
JPS5553906A (en) * 1978-10-17 1980-04-19 Citizen Watch Co Ltd Cmos crystal oscillator
US4282496A (en) 1979-08-29 1981-08-04 Rca Corporation Starting circuit for low power oscillator circuit
JPS5690604A (en) 1979-12-24 1981-07-22 Seiko Instr & Electronics Ltd Quartz oscillating circuit
US4459565A (en) * 1980-06-09 1984-07-10 Texas Instruments Incorporated Low current electronic oscillator system
CH640693B (fr) * 1980-07-21 Asulab Sa Circuit oscillateur c-mos.
JPH07154146A (ja) * 1993-11-30 1995-06-16 Nippon Precision Circuits Kk 発振用集積回路および発振回路
GB2305319B (en) 1995-09-16 2000-03-15 Motorola Inc A low power amplifier and an oscillating circuit incorporating the amplifier

Also Published As

Publication number Publication date
GB0011558D0 (en) 2000-06-28
AU2001262287A1 (en) 2001-11-20
US20030107445A1 (en) 2003-06-12
JP2003533115A (ja) 2003-11-05
WO2001086803A1 (fr) 2001-11-15
KR20030013412A (ko) 2003-02-14
GB0017894D0 (en) 2000-09-06
DE60104111D1 (de) 2004-08-05
GB2362276A (en) 2001-11-14
CN1419738A (zh) 2003-05-21
EP1284046A1 (fr) 2003-02-19
DE60104111T2 (de) 2005-08-25
US6759914B2 (en) 2004-07-06
KR100835130B1 (ko) 2008-06-05
CN1178377C (zh) 2004-12-01

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