EP1277280A1 - Verfahren und gerät für einen geschalteten oszillator in digitalen schaltungen - Google Patents

Verfahren und gerät für einen geschalteten oszillator in digitalen schaltungen

Info

Publication number
EP1277280A1
EP1277280A1 EP00917235A EP00917235A EP1277280A1 EP 1277280 A1 EP1277280 A1 EP 1277280A1 EP 00917235 A EP00917235 A EP 00917235A EP 00917235 A EP00917235 A EP 00917235A EP 1277280 A1 EP1277280 A1 EP 1277280A1
Authority
EP
European Patent Office
Prior art keywords
circuit
region
output
operating point
unstable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00917235A
Other languages
English (en)
French (fr)
Inventor
Jurianto The Centre for Wireless Commun. JOE
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National University of Singapore
Original Assignee
National University of Singapore
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National University of Singapore filed Critical National University of Singapore
Publication of EP1277280A1 publication Critical patent/EP1277280A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/313Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of semiconductor devices with two electrodes, one or two potential barriers, and exhibiting a negative resistance characteristic
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/313Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of semiconductor devices with two electrodes, one or two potential barriers, and exhibiting a negative resistance characteristic
    • H03K3/315Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of semiconductor devices with two electrodes, one or two potential barriers, and exhibiting a negative resistance characteristic the devices being tunnel diodes

Definitions

  • the present invention relates to oscillators and more particularly to gated oscillators.
  • Oscillators have a wide range of uses, For example, microprocessor operation is synchronized by the periodic timing signals provided by an oscillator. Digital tachometers and digital speedometers in an automobile require a precision, reference to provide accurate read-outs. Medical devices such as pacemakers require an accurate pulse generator to ensure proper rhythmic stimulation of the heart.
  • a gated oscillator is an oscillator that starts or stops oscillating by an enabling signal.
  • oscillations are produced by periodically charging and discharging a capacitor between first and second voltage levels when the oscillator is enabled. If it is disabled, the oscillations are stopped by preventing the capacitor from periodically charging and discharging,
  • the capacitor will continue to discharge past the first voltage level toward the lower power supply voltage when the oscillation is stopped.
  • the oscillator is enabled, a certain amount of time is needed to charge the capacitor from lower power supply voltage to the first voltage level and then to the second voltage level, whereupon oscillatory behavior ensues,
  • the delay in charging the capacitor from the lower power supply voltage to the first voltage level causes the first pulse in the pulse train to be wider than the rest of the pulses. This error is undesirable in applications which require and expect predictable pulse widths.
  • the error can be substantially corrected if extra circuitry is added to prevent the capacitor from discharging past the first voltage level.
  • Gated oscillators have many applications in digital circuits.
  • Gad oscillator emulates a flip-flop
  • a gated oscillator circuit is described in a flip-flop configuration.
  • Oscillator meets three requirements
  • a gated oscillator is described for use in clock circuit as the clocking source in a digital application.
  • a simplistic gated oscillator circuit can be built using an AND logic gate.
  • An enable signal is applied to one of its terminals and a continuous free running oscillator is applied to the other terminal, The output produces the desired gated oscillations.
  • This prior art gated oscillator requires an external continuous free running oscillator.
  • a problem with this design is the inability of the enable signal to synchronize with the free running oscillator, thus producing indeterminate behavior,
  • Another problem is that the free running oscillation fixes the frequency and duty cycle of the gated oscillator output.
  • the free running oscillator is continually running, even when the enable signal is removed. Consequently, there is unnecessary consumption of power.
  • a method for generating pulses in a digital circuit includes providing a circuit having a variable operating point.
  • the circuit is defined by a transfer function characterized by having an unstable operating region bounded by a first stable operating region and a second stable operating region,
  • the circuit produces oscillatory output when its operating point is moved into the unstable region.
  • the circuit produces a non- oscillatory output when its operating point is placed into either of the first and second stable regions.
  • the method further includes forcing the operating point into the unstable region to produce oscillatory output.
  • the method further includes forcing the operating point into one of the stable regions in order to terminate oscillations,
  • a gated oscillator circuit in accordance with the invention includes a circuit having a transfer function defined by an unstable operating region bounded by a first stable operating region and by a second stable operating region.
  • the transfer function defines a set of operating points.
  • the circuit is adapted to produce oscillatory output when the operating point is positioned in the unstable region.
  • the circuit is further adapted to produce a non-oscillatory output when its operating point is positioned in either of the first and second stable regions.
  • a function generator which selectively produces an output of a first level and an output of a second level is coupled to the circuit as an input signal.
  • the operating point is forced into the unstable region when the function generator output is at the first level. This level is called an enable signal.
  • the operating point is forced into one of the stable regions when the function generator output is at its second output level. This level is referred to as a disable signal.
  • the invention requires only the application of an enable signal to enable oscillations or a disable signal to terminate oscillations.
  • the inventive circuit is advantageous in that its oscillations start and stop substantially instantaneously. There are no transients between the ON and OFF state of the oscillator. Another advantage is that the period of the first cycle of oscillation during an ON period is the same as the subsequent cycles in that ON period. There is no need for additional supporting circuit elements or special circuits for maintaining standby levels in the capacitor.
  • the circuit does not require any external free running oscillation.
  • the circuit will generate its own oscillation.when triggered by the enable signal.
  • the circuit is inherently synchronized with the enable signal.
  • Figs. 1 A - 1C show how the present invention obviates the need for a clock in conventional clocked digital circuit designs.
  • Fig, 2 illustrates generally the transfer function of a circuit used in Figs, lb and lc.
  • Fig. 3 illustrates schematically a circuit arrangement for forcing the operating point between stable and unstable regions.
  • Figs. 4 - 6 are examples of circuit configurations in accordance with the invention.
  • Fig. 7 illustrates measurements taken from a circuit constructed in accordance with the invention.
  • FIG. 1 A a typical digital circuit such as the illustrated dual slope analog-to-dig ⁇ tal converter is shown, VR is a referenced voltage and V A is an analog voltage to be converted to a digital representation.
  • the output of integrator 110 is an analog waveform that contains information of the amplitude of V A with respect to VR.
  • a comparator that converts this analog waveform to an enable signal and AND gate combination 112 that receives an external clocking signal together produce a gated oscillation output 114 which drives the counter.
  • Fig. IB shows how a gated oscillator 100 in accordance with the present invention can be used to replace the conventional gated clock generation circuit 112 of conventional digital circuits.
  • Fig. 1C generally, the clock input of most conventional digital circuits can be driven by the gated oscillator circuit of the present invention.
  • inventive oscillator It is understood that digital circuits encompass a wide range of applications, The invention is therefore not limited to any one particular digital circuit. Rather, the invention relates to digital circuits having a clock/oscillation generation function provided by the circuit disclosed hereinbelow.
  • gated oscillator circuits in accordance with the present invention exhibit a transfer function whose curve has a generally N-shaped appearance.
  • the "transfer function" of a circuit refers to the relationship between any two state variables of that circuit
  • electronic circuits are typically characterized by their I-V curves, the two state variables being current (I) and voltage (V).
  • I current
  • V voltage
  • Such curves indicate how one state variable (e.g., current, I) changes as the other state variable (voltage, V) varies.
  • a transfer function curve 202 includes a portion which lies within a region 204, referred to herein as an "unstable" region.
  • the unstable region is bounded on either side by regions 206 and 208, each of which is herein referred to as the "stable" region.
  • portions of the transfer function curve 202 also lie in the stable regions.
  • a circuit in accordance with the invention has an associated "operating point" which is defined as its location on the transfer function 202.
  • Fig. 2 shows three operating point positions, 210, 210 s , and 210".
  • the nature of the output of the circuit depends on the location of the operating point along the transfer function. If the operating point is positioned along the portion 214 of the transfer function that lies within region 204, the output of the circuit will exhibit an oscillatory behavior. Hence, the region 204 in which this portion of the transfer function is found is referred to as an unstable region. If the operating point is positioned along the portions 216, 218 of the transfer function that lie within either of regions 206 and 208, the output of the circuit will exhibit a generally time-varying but otherwise non-oscillatory behavior. For this reason, regions 206 and 20S are referred to as stable regions.
  • circuit 302 having an input defined by terminals 303 and 305.
  • An inductive element 304 is coupled to terminal 305.
  • a function generator 310 is coupled between the other end of inductive element 304 and terminal 303 of circuit 302, thus completing the circuit.
  • circuit 302 has a transfer function which appears N-shaped.
  • circuit 302 is characterized in that its operating point can moved into and out of the unstable region 204 depending on the level of the output V s of function generator 310, This action controls the onset of oscillatory behavior, and cessation of such oscillatory behavior, at the output V ou t of circuit 302. Forcing the operation point to be on a portion of the transfer function that lies in the unstable region 204 will result in oscillatory behavior. Forcing the operating point to lie on the transfer function found in one of the stable regions 206, 08 will result in non-oscillatory behavior.
  • An example of a circuit that exhibits the N-shaped transfer function is an operation amplifier (op-amp) configured with a feedback resistor between the op-amp output and its non-inverting input.
  • Fig.4 shows such a circuit 400.
  • An op-amp 402 includes a positive feedback path wherein the op-amp's output V wt feeds back to its non- inverting input via feedback resistor 408 having a resistance R f , A portion of the output voltage of op-amp 402 is provided to its inverting input.
  • Fig, 4 shows a voltage dividing circuit comprising resistors 404 and 406, having respectively resistances Rj and R 2 , to supply a portion of the op-amp output back to its inverting input.
  • Completing the circuit is an inductor 410 and function generator 310 coupled in series between the non-inverting input of op-amp 402 and ground.
  • a typical off-the-shelf op-amp can be used, such as the commonly available LM-358 op-amp.
  • circuit 500 comprises a tunnel diode 502 coupled to function generator 310 through inductive element 1 .
  • the output V ovrt is taken across resistor 504, which is coupled between the other end of diode 502 and ground.
  • VdP Van der Pol
  • x and v are the state variables of the VdP oscillator
  • Z and ⁇ are parameters of the VdP oscillator
  • f(t) is a time varying forcing function that is controllable and can be used to move the operating point of the VdP oscillator
  • ⁇ (x) is a cubic function of variable x.
  • ⁇ (x) is the key for establishing a controllable VdP oscillator.
  • Equations (1) and (2) relate to the circuit of Fig.4 by replacing variables x and >> respectively with and / to represent physical variables that are commonly used in a circuit design.
  • Parameter C in Eq, (4) represents a small parasitic capacitor 420 across the voltage V, shown in Fig. 4 by phantom lines.
  • V s is the time varying voltage source of function generator 310 which acts as forcing function.
  • the negative sloped segment is said to lie in unstable region 204 as is operating point 210.
  • the operating point 210 1 , 210" is on a positive sloped segment, a non-oscillatory output is observed.
  • the positive segments are said to lie in stable regions 206, 208,
  • the operating point 210 can be moved along the transfer function by changing the output V s of function generator 310 as it is applied to the input of circuit 400.
  • the operating point can be moved into unstable region 204 when an enable signal is provided by the function generator.
  • the operating point can be moved out of the unstable region and into one of the stable regions 206, 208 by the application of a disable signal,
  • the resulting behavior of circuit 400 is that of a gated oscillator.
  • Fig, 6 shows yet another embodiment of the gated oscillator of the invention.
  • a function generator 10 provide a variable voltage signal V s . This signal feeds through inductor 410 into a first inverter 602, The output of inverter 602 is coupled to a second inverter 604, The output of inverter 604 is taken across resistor 608 to provide output V ou t- feedback path from the output of inverter 604 to the input of inverter 602 is provided via resistor 606.
  • Trace 1 is the output V s of function generator 310 as applied to the input of circuit 400.
  • a first portion of the trace constitutes the ENABLE signal.
  • the function generator output is a digital waveform
  • a typical digital waveform is a square wave such as shown in Fig. 7. It is noted that typically, the digital waveform will be asymmetric along the time axis, since the periods of ON time and OFF time will depend on the nature of the particular application of the gated oscillator.
  • Trace 2 is the output voltage V out of circuit 400.
  • the circuit begins to oscillate when an enable signal is received. The oscillations continue for the duration of the enable signal. It can be further seen that the first period Ti of the first cycle has the same duration as each of the remaining cycles, T 2 .
  • the pulse width can be varied by changing the circuit parameters R f , Ri, and R 2 or the op-amp DC bias Vcc. When the disable signal is received, the circuit stops oscillating instantaneously.
  • the location of the operating point along fhe transfer curve in the unstable region affects the period of oscillations of the output of circuit 400.
  • the location of the operating point within the unstable region can be determined by adjusting the level of the forcing function. It can be se ⁇ n, therefore, that different oscillation periods can be attained from circuit 400 by applying an enable signal of different levels.
  • the gated oscillator of the invention can thus be made to produce different pulse widths by the use of a function generator in which the level of the enable signal can be controlled.
  • the invention described herein uses an unconventional method of controlling the operating point of a VdP oscillator to provide a significantly simplified digital circuit design which obviates the need for a clock circuit.
  • the inventive circuit does not need additional supporting components.
  • the invention obviates the need for a charging and a discharging capacitor for generating pulses.
  • the invention dispenses with fhe support circuitry conventionally required to maintain capacitor potential when oscillation is stopped.
  • the invention requires only that an enabling signal be provided to "force" the VdP oscillator to oscillate and a disabling signal to stop oscillations. These signals can be readily generated by any of a number of known circuit designs.
  • the inventive gated oscillator circuit is advantageous , in that its oscillations start and stop substantially instantaneously. Consequently, there are no transients between the ON and OFF state of the oscillator. Another advantage is that fhe period of the first cycle of oscillation during an ON period is the same as the subsequent cycles during that ON period.
  • circuit does not require any external free running oscillator.
  • the circuit will generate its own oscillations when triggered by an enable signal. Consequently, this allows for significant reductions in power consumption in digital circuit applications. This is especially advantageous given the low power requirements of many of today's digital applications.
  • the circuit is inherently synchronized with the enable signal.
  • the duty cycle and the frequency of oscillation can be varied.
  • the gated oscillation at the output of the circuit does not overlap with the enable signal and therefore no additional circuitry is required to separate the signals, thus realizing a simplification in the gated oscillator circuitry,

Landscapes

  • Oscillators With Electromechanical Resonators (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
EP00917235A 2000-04-25 2000-04-25 Verfahren und gerät für einen geschalteten oszillator in digitalen schaltungen Withdrawn EP1277280A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2000/000509 WO2001082481A1 (en) 2000-04-25 2000-04-25 Method and apparatus for a gated oscillator in digital circuits

Publications (1)

Publication Number Publication Date
EP1277280A1 true EP1277280A1 (de) 2003-01-22

Family

ID=11003910

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Application Number Title Priority Date Filing Date
EP00917235A Withdrawn EP1277280A1 (de) 2000-04-25 2000-04-25 Verfahren und gerät für einen geschalteten oszillator in digitalen schaltungen

Country Status (6)

Country Link
EP (1) EP1277280A1 (de)
JP (1) JP2003532324A (de)
CN (1) CN1452810A (de)
AU (1) AU2000238324A1 (de)
CA (1) CA2403167A1 (de)
WO (1) WO2001082481A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030112862A1 (en) * 2001-12-13 2003-06-19 The National University Of Singapore Method and apparatus to generate ON-OFF keying signals suitable for communications

Citations (11)

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US3209282A (en) * 1962-05-16 1965-09-28 Schnitzler Paul Tunnel diode oscillator
CH758563A4 (de) * 1960-12-13 1966-03-31
US3303350A (en) * 1959-12-21 1967-02-07 Ibm Semiconductor switching circuits
DE1614189A1 (de) * 1966-10-03 1970-08-13 Metrawatt Ag Schaltung mit Tunneldioden-Charakteristik
US3569623A (en) * 1968-11-25 1971-03-09 Ultronic Systems Corp Electronic signal converter
DE2312771A1 (de) * 1972-04-04 1973-11-08 Inst Schienenfahrzeuge Schaltungsanordnung zur erfassung und ueberwachung von spannungen
DE2459531A1 (de) * 1974-12-17 1976-07-01 Daimler Benz Ag Rc-rechteck-generator nach dem ladestromverfahren
DE4207288A1 (de) * 1992-03-07 1993-09-09 Ulrich Dr Barjenbruch Vorrichtung zur messung magnetischer gleich- und wechselfelder
US5339053A (en) * 1993-09-17 1994-08-16 The United States Of America As Represented By The Secretary Of The Army Instant-on microwave oscillators using resonant tunneling diode
EP0746100A1 (de) * 1995-06-01 1996-12-04 Sentron Ag Schaltungsanordnung zum Betrieb eines resistiven, kapazitiven oder induktiven Sensors
JPH10190417A (ja) * 1996-12-26 1998-07-21 Yokogawa Electric Corp スタータブル・オシレータ

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FR1438262A (fr) * 1964-12-16 1966-05-13 Ultra Electronics Ltd Circuit à diodes tunnels
US3967210A (en) * 1974-11-12 1976-06-29 Wisconsin Alumni Research Foundation Multimode and multistate ladder oscillator and frequency recognition device
US4028562A (en) * 1975-06-16 1977-06-07 Mcdonnell Douglas Corporation Negative impedance transistor device

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3303350A (en) * 1959-12-21 1967-02-07 Ibm Semiconductor switching circuits
CH758563A4 (de) * 1960-12-13 1966-03-31
US3209282A (en) * 1962-05-16 1965-09-28 Schnitzler Paul Tunnel diode oscillator
DE1614189A1 (de) * 1966-10-03 1970-08-13 Metrawatt Ag Schaltung mit Tunneldioden-Charakteristik
US3569623A (en) * 1968-11-25 1971-03-09 Ultronic Systems Corp Electronic signal converter
DE2312771A1 (de) * 1972-04-04 1973-11-08 Inst Schienenfahrzeuge Schaltungsanordnung zur erfassung und ueberwachung von spannungen
DE2459531A1 (de) * 1974-12-17 1976-07-01 Daimler Benz Ag Rc-rechteck-generator nach dem ladestromverfahren
DE4207288A1 (de) * 1992-03-07 1993-09-09 Ulrich Dr Barjenbruch Vorrichtung zur messung magnetischer gleich- und wechselfelder
US5339053A (en) * 1993-09-17 1994-08-16 The United States Of America As Represented By The Secretary Of The Army Instant-on microwave oscillators using resonant tunneling diode
EP0746100A1 (de) * 1995-06-01 1996-12-04 Sentron Ag Schaltungsanordnung zum Betrieb eines resistiven, kapazitiven oder induktiven Sensors
JPH10190417A (ja) * 1996-12-26 1998-07-21 Yokogawa Electric Corp スタータブル・オシレータ

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* Cited by examiner, † Cited by third party
Title
Anderson J.P.; Pomerantz M.: *dApparatus for Generation and Detection of Microwave Ultrasound*d, IBM Technical Disclosure Bulletin, Vol. 12, No. 4, September 1969, pages 576 and 577 *
Lutz R.F.: *dA 3000-Mc Lumped-Parameter Oscillator Using an Esaki Negative-Resistance Diode*d, IBM Journal, October 1959, pages 372-374 *
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 12 31 October 1998 (1998-10-31) *
See also references of WO0182481A1 *

Also Published As

Publication number Publication date
AU2000238324A1 (en) 2001-11-07
CA2403167A1 (en) 2001-11-01
JP2003532324A (ja) 2003-10-28
WO2001082481A1 (en) 2001-11-01
CN1452810A (zh) 2003-10-29

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