Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
  • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
  • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
  • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
  • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
  • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
  • G06K19/07718—Constructional details, e.g. mounting of circuits in the carrier the record carrier being manufactured in a continuous process, e.g. using endless rolls
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
  • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
  • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
  • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
  • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
  • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
  • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
  • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
  • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
  • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
  • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
  • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
  • G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/10—Bump connectors; Manufacturing methods related thereto
  • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
  • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/10—Bump connectors; Manufacturing methods related thereto
  • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
  • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
  • H01L2224/161—Disposition
  • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/10—Bump connectors; Manufacturing methods related thereto
  • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
  • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
  • H01L2224/161—Disposition
  • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
  • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01004—Beryllium [Be]
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S174/00—Electricity: conductors and insulators
  • Y10S174/34—PCB in box or housing
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
  • Y10T29/49126—Assembling bases
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
  • Y10T29/49155—Manufacturing circuit on or in base
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
  • Y10T29/49155—Manufacturing circuit on or in base
  • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Definitions

• the present invention relates to a particularly cost-effective production method for a chip card laminated from paper or film.
• Chip cards are now also used for applications that are limited to a certain time or in which the chip card can only be used a few times.
• An example of this is a telephone prepaid card, in the chip of which a certain number of telephone units are stored for consumption. Since the individual chip card does not provide any independent use in such applications and has only a memory content of low value, the chip card itself may only make up a small part of the purchase price, which is to be kept low, for reasons of economy. It is therefore sought for card material, card structure and manufacturing methods with which the chip card can be manufactured as inexpensively as possible.
• W095 / 21423 describes chip cards that can be produced from paper, in which a chip card module is laminated into paper layers.
• the chip card module contains at least one semiconductor chip with an integrated circuit and its electrical connections according to the chip card standard.
• conductor tracks functioning as antennas are attached in the chip card module and are electrically conductively connected to the semiconductor chip.
• the production of the laminate uses the usual techniques of paper production. The different layers are glued and pressed together; Cutouts in the paper are punched or milled to accommodate the chip card module.
• the chip card module, including the connection contacts and a carrier element for the semiconductor chip is produced independently of the paper layer laminate.
• WO 97/18531 describes a chip card in which a plastic layer with an IC chip laminated therein is connected to an insulating layer as a substrate printed on both sides with conductors such that the connections of the IC chip with the conductors facing it on the insulating layer are electrically connected.
• EP 0 706 152 A2 describes a chip card and a production method in which the chip is mounted on conductors which are attached to a film and is built into a core film and on the back without producing a module using flip-chip technology an outer film is laminated. Vias to external contacts are present in the film.
• WO 97/27564 describes a chip card with a laminated chip module, which is produced by means of heatable laminating roller pairs.
• the object of the present invention is to provide a production method with which the inexpensive production of chip cards in large numbers is possible.
• the chip card produced according to the invention is made of at least two layers of a thin carrier material such as. B. laminated paper or foil, one layer each carrying the semiconductor chip provided for a chip card and the second layer having connection contacts and conductor tracks or external connection surfaces which are provided for signal and energy transmission.
• the semiconductor chips are attached in one layer so that their contacts the other Layer facing.
• the layers are connected to one another in such a way that the contacts of the semiconductor chips are electrically conductively connected to the connection contacts of the other layer. In the case of a chip card provided with external connection surfaces, these are for contacting the
• connection contacts and the external connection surfaces arranged on two opposite sides of a layer An electrically conductive connection between them takes place through cutouts or openings in the carrier material of this layer.
• the chip cards can thus be produced without inserting a chip card module, the carrier materials in particular being unwound as strips or webs of rolls and being fed to a device for producing laminates which is known in principle from paper production.
• FIG. 1 schematically shows an arrangement for producing a chip card with external connection areas.
• Figure 2 shows schematically an arrangement for producing a contactless chip card.
• the carrier materials 1, 2 provided for the at least two layers are shown in a side view in an arrangement for producing the chip cards.
• a semiconductor chip 6 is used in the first carrier material 1, which is provided for the first layer of the chip card.
• a multiplicity of chip cards are produced from a strip or a web of the carrier material, which are only separated after the carrier materials 1, 2 have been connected.
• an arrangement with only one semiconductor chip 6 in the first carrier material 1 is drawn in cross section in FIG. This semiconductor chip 6 is to be thought of to the left and right and possibly also into the drawing plane adjacent to further semiconductor chips, which are each provided for further chip cards.
• Each semiconductor chip 6 is arranged in the first carrier material 1, preferably inserted into a recess.
• This cutout can completely break through the thin carrier material 1; or there is only one recess which leaves the rear upper side 11 of the first carrier material 1 intact. Further layers for covering the semiconductor chip from the back can also be applied to this rear upper side 11 or can be applied in a final manufacturing step.
• Connection contacts 3 with which the contacts of the semiconductor chip 6 in the manufacture of the laminate via electrical Conductive connections 7 (eg so-called bumps made of a soft solder such as NiAu) are connected in or on the side of the second carrier material 2 facing the semiconductor chip 6.
• electrical Conductive connections 7 eg so-called bumps made of a soft solder such as NiAu
• connection surfaces 4 which are for external
• connection contacts of a terminal on the outer top 11 facing away from the semiconductor chip 6 of the second carrier material 2.
• connection contacts 5 there is electrically conductive material in openings which are in the second carrier material 2 before the application of the the connection contacts and the connection surfaces 4 provided electrically conductive materials are produced.
• the first carrier material 1 forms a first layer with the semiconductor chips 6 mounted therein and the second carrier material 2 forms the second layer 2 with the connection contacts 3 provided for electrical connections, the electrically conductive connections 5 provided in the openings and the external connection surfaces 4th
• the carrier materials 1, 2 are unwound in the arrangement of rolls 12 shown in FIG. 1, as is also the case with paper and cardboard production with so-called endless roll formats.
• the further transport of the interconnected carrier materials is indicated in FIG. 1 by the rollers 13 shown, which press the laminate consisting of the layers together during transport and which are preferably arranged at different points along the path of the carrier material in the device.
• These rollers can be provided with heating devices which heat the carrier material in such a way that an adhesive layer, for example an adhesive layer, is applied between the carrier materials.
• an adhesive layer for example an adhesive layer
• connection contacts 7 For the production of the electrically conductive connections 7 between the contacts of the semiconductor chip 6 and the connection contacts 3, heating can also take place via a heating part pressed on from the outside, here also preferably a rolling heating roller.
• the chip card produced according to the invention is therefore composed of at least two layers, although modifications with a larger number of layers are within the scope of the invention. It is essential that the semiconductor chip is integrated directly into a layer as an IC chip.
• the electrical conductors for the connection are installed in or on a further layer. Paper or film in continuous roll format is particularly suitable as the carrier material.
• the connection contacts and / or connection surfaces provided on the second layer can preferably be produced in an endless screen printing process, with which, for example, an electrically conductive paste is applied in a thin layer and thereby structured.
• the connection of the contacts of the IC to the connection contacts of the second layer is carried out similarly to the method of flip chip mounting of semiconductor chips known per se.
• a filling compound 8 can be present between the semiconductor chip 6 and the second layer formed by the second carrier material 2, which preferably consists of an anisotropically electrically conductive material is formed.
• the material is aligned in such a way that the greatest conductivity is present in the direction of the intended conductive connections 7, while the conductivity transverse to this direction, that is to say in the plane of the connection of the carrier materials 1, 2, is as low as possible in order to avoid short circuits between the to avoid different contacts.
• Isotropically conductive or insulating fillers 8 can also be used, it being advantageous if these fillers undergo at least a slight shrinkage after the application and connection of the carrier materials 1, 2, so that the electrically conductive connections 7 to the contacts of the semiconductor chip 6 and the connection contacts 3 of the second layer 2 are pressed on and in this way a sufficiently strong ke, non-positive electrically conductive connection 7 is achieved.
• a contactless chip card can be produced according to the invention in a manner analogous to this exemplary embodiment. Then, instead of the connection surfaces 4 applied to the second carrier material 2, a conductor track 10 (see FIG. 2) is applied and structured on the inner surface provided with the connection contacts 3. Such a conductor track 10 can be designed spirally as a coil, which is provided as an antenna for signal transmission and energy transmission.
• the other components and the manufacturing method of this chip card according to FIG. 2 correspond to the chip cards previously shown with reference to FIG. 1.
• the second carrier material 2 is preferably only on the
• the laminate can consist of more than two layers.
• the configurations according to FIGS. 1 and 2 can also be combined with one another, for example if a chip card is desired that is suitable for both external electrical connection and contactless use.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Credit Cards Or The Like (AREA)

Applications Claiming Priority (3)

Publications (1)

Family

ID=7637546

Family Applications (1)

Country Status (8)

Families Citing this family (25)

Family Cites Families (10)

• 2000
  • 2000-04-04 DE DE10016715A patent/DE10016715C1/de not_active Expired - Fee Related
• 2001
  • 2001-04-04 WO PCT/DE2001/001332 patent/WO2001075788A1/de not_active Application Discontinuation
  • 2001-04-04 CN CNB018078133A patent/CN1184595C/zh not_active Expired - Fee Related
  • 2001-04-04 EP EP01931412A patent/EP1269411A1/de not_active Withdrawn
  • 2001-04-04 JP JP2001573390A patent/JP2003529856A/ja not_active Withdrawn
  • 2001-04-04 RU RU2002129296/09A patent/RU2230362C1/ru not_active IP Right Cessation
  • 2001-04-17 TW TW090107980A patent/TW543007B/zh active
• 2002
  • 2002-10-04 US US10/264,873 patent/US7069652B2/en not_active Expired - Fee Related

Non-Patent Citations (1)

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