EP1237160A3 - Leseverstärkersteuerschaltung für Halbleiterspeicheranordnung - Google Patents
Leseverstärkersteuerschaltung für Halbleiterspeicheranordnung Download PDFInfo
- Publication number
- EP1237160A3 EP1237160A3 EP01131050A EP01131050A EP1237160A3 EP 1237160 A3 EP1237160 A3 EP 1237160A3 EP 01131050 A EP01131050 A EP 01131050A EP 01131050 A EP01131050 A EP 01131050A EP 1237160 A3 EP1237160 A3 EP 1237160A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- sense amplifier
- control circuit
- memory device
- semiconductor memory
- amplifier control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/08—Control thereof
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/06—Sense amplifier related aspects
- G11C2207/065—Sense amplifier drivers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001000475A JP2002208277A (ja) | 2001-01-05 | 2001-01-05 | 半導体記憶装置のセンスアンプ制御回路 |
| JP2001000475 | 2001-01-05 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP1237160A2 EP1237160A2 (de) | 2002-09-04 |
| EP1237160A3 true EP1237160A3 (de) | 2004-09-01 |
Family
ID=18869257
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP01131050A Withdrawn EP1237160A3 (de) | 2001-01-05 | 2001-12-31 | Leseverstärkersteuerschaltung für Halbleiterspeicheranordnung |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US6496435B2 (de) |
| EP (1) | EP1237160A3 (de) |
| JP (1) | JP2002208277A (de) |
| KR (1) | KR100412000B1 (de) |
| CN (4) | CN1302551C (de) |
| TW (1) | TW530407B (de) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6071689A (en) * | 1997-12-31 | 2000-06-06 | Xy, Inc. | System for improving yield of sexed embryos in mammals |
| EP1448134B1 (de) * | 2001-11-05 | 2005-06-08 | The Procter & Gamble Company | Streckbares elastisches verbundmaterial und sein herstellungsverfahren |
| DE10310570B3 (de) * | 2003-03-11 | 2004-09-30 | Infineon Technologies Ag | Verfahren und Testschaltung zum Testen einer dynamischen Speicherschaltung |
| JP2005322380A (ja) | 2004-04-09 | 2005-11-17 | Toshiba Corp | 半導体記憶装置 |
| US7448012B1 (en) | 2004-04-21 | 2008-11-04 | Qi-De Qian | Methods and system for improving integrated circuit layout |
| US7664796B2 (en) * | 2004-10-13 | 2010-02-16 | Microsoft Corporation | Electronic labeling for offline management of storage devices |
| FR2879816B1 (fr) * | 2004-12-20 | 2007-06-08 | Atmel Nantes Sa Sa | Circuit electronique comprenant au moins une premiere et une seconde paires differentielles dont les transistors partagent un meme caisson |
| FR2879817B1 (fr) * | 2004-12-20 | 2007-03-30 | Atmel Nantes Sa Sa | Circuit electronique comprenant au moins une premiere paire differentielle dont les transistors partagent une meme source ou un meme drain |
| KR100656470B1 (ko) | 2006-02-07 | 2006-12-11 | 주식회사 하이닉스반도체 | 반도체 메모리의 드라이버 제어장치 및 방법 |
| JP5248019B2 (ja) * | 2007-01-09 | 2013-07-31 | エルピーダメモリ株式会社 | 半導体記憶装置、及びそのセンスアンプ回路 |
| KR100866146B1 (ko) | 2007-10-11 | 2008-10-31 | 주식회사 하이닉스반도체 | 센스 앰프 제어 회로 |
| JP5711033B2 (ja) * | 2011-04-12 | 2015-04-30 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
| US8693236B2 (en) | 2011-12-09 | 2014-04-08 | Gsi Technology, Inc. | Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features |
| US8593860B2 (en) | 2011-12-09 | 2013-11-26 | Gsi Technology, Inc. | Systems and methods of sectioned bit line memory arrays |
| JP2014017386A (ja) * | 2012-07-10 | 2014-01-30 | Ps4 Luxco S A R L | 半導体装置 |
| CN109991806B (zh) * | 2017-12-29 | 2022-03-11 | 长鑫存储技术有限公司 | 掩膜版、存储器及存储器的制造方法 |
| US11495282B2 (en) | 2020-08-12 | 2022-11-08 | Micron Technology, Inc. | Sense amplifier drivers, and related devices, systems, and methods |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5636158A (en) * | 1995-03-13 | 1997-06-03 | Kabushiki Kaisha Toshiba | Irregular pitch layout for a semiconductor memory device |
| US6031779A (en) * | 1997-04-10 | 2000-02-29 | Hitachi, Ltd. | Dynamic memory |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR890004762B1 (ko) * | 1986-11-21 | 1989-11-25 | 삼성전자 주식회사 | 고성능 디램을 위한 센스 증폭기 |
| KR910009551B1 (ko) * | 1988-06-07 | 1991-11-21 | 삼성전자 주식회사 | 메모리장치의 센스앰프 분할 제어회로 |
| JPH0758594B2 (ja) * | 1988-12-27 | 1995-06-21 | シャープ株式会社 | ダイナミック型半導体記憶装置 |
| KR920010346B1 (ko) * | 1990-05-23 | 1992-11-27 | 삼성전자 주식회사 | 반도체 메모리의 센스앰프 구동회로 |
| JP3549602B2 (ja) * | 1995-01-12 | 2004-08-04 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| JP2001077322A (ja) | 1999-09-02 | 2001-03-23 | Toshiba Corp | 半導体集積回路装置 |
-
2001
- 2001-01-05 JP JP2001000475A patent/JP2002208277A/ja active Pending
- 2001-12-27 US US10/035,043 patent/US6496435B2/en not_active Expired - Lifetime
- 2001-12-30 CN CNB2004100460001A patent/CN1302551C/zh not_active Expired - Lifetime
- 2001-12-30 CN CNA2004101003925A patent/CN1624796A/zh active Pending
- 2001-12-30 CN CNA2006101156987A patent/CN1956198A/zh active Pending
- 2001-12-30 CN CN01138188A patent/CN1372268A/zh active Pending
- 2001-12-31 EP EP01131050A patent/EP1237160A3/de not_active Withdrawn
- 2001-12-31 TW TW090133233A patent/TW530407B/zh not_active IP Right Cessation
-
2002
- 2002-01-05 KR KR10-2002-0000616A patent/KR100412000B1/ko active IP Right Grant
- 2002-10-09 US US10/267,949 patent/US6674678B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5636158A (en) * | 1995-03-13 | 1997-06-03 | Kabushiki Kaisha Toshiba | Irregular pitch layout for a semiconductor memory device |
| US6031779A (en) * | 1997-04-10 | 2000-02-29 | Hitachi, Ltd. | Dynamic memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1624796A (zh) | 2005-06-08 |
| KR20020057830A (ko) | 2002-07-12 |
| TW530407B (en) | 2003-05-01 |
| JP2002208277A (ja) | 2002-07-26 |
| CN1956198A (zh) | 2007-05-02 |
| US20020089888A1 (en) | 2002-07-11 |
| CN1302551C (zh) | 2007-02-28 |
| US6674678B2 (en) | 2004-01-06 |
| CN1542972A (zh) | 2004-11-03 |
| US20030031071A1 (en) | 2003-02-13 |
| EP1237160A2 (de) | 2002-09-04 |
| CN1372268A (zh) | 2002-10-02 |
| KR100412000B1 (ko) | 2003-12-24 |
| US6496435B2 (en) | 2002-12-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| 17P | Request for examination filed |
Effective date: 20011231 |
|
| AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR |
|
| AX | Request for extension of the european patent |
Free format text: AL;LT;LV;MK;RO;SI |
|
| RIC1 | Information provided on ipc code assigned before grant |
Ipc: 7G 11C 11/405 B Ipc: 7G 11C 11/4091 B Ipc: 7G 11C 7/06 A |
|
| PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
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| AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR |
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| AX | Request for extension of the european patent |
Extension state: AL LT LV MK RO SI |
|
| AKX | Designation fees paid |
Designated state(s): DE FR GB |
|
| RBV | Designated contracting states (corrected) |
Designated state(s): DE FR GB |
|
| 17Q | First examination report despatched |
Effective date: 20071128 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
| 18D | Application deemed to be withdrawn |
Effective date: 20080409 |