EP1168631B1 - Method and apparatus for improving S/N ratio in digital-to-analog conversion of pulse density modulated (PDM) signal - Google Patents

Method and apparatus for improving S/N ratio in digital-to-analog conversion of pulse density modulated (PDM) signal Download PDF

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Publication number
EP1168631B1
EP1168631B1 EP01114242A EP01114242A EP1168631B1 EP 1168631 B1 EP1168631 B1 EP 1168631B1 EP 01114242 A EP01114242 A EP 01114242A EP 01114242 A EP01114242 A EP 01114242A EP 1168631 B1 EP1168631 B1 EP 1168631B1
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European Patent Office
Prior art keywords
signal
digital
bit
analog
full scale
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EP01114242A
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German (de)
English (en)
French (fr)
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EP1168631A2 (en
EP1168631A3 (en
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Nakao Shigetoshi
Hamasaki Toshihiko
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Texas Instruments Japan Ltd
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Texas Instruments Japan Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/368—Continuously compensating for, or preventing, undesired influence of physical parameters of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step

Definitions

  • the present invention relates to a method and apparatus for improving a signal-to-noise (S/N) ratio in digital-to-analog conversion of a pulse density modulated signal (PDM signal).
  • the invention also relates to a circuit for decoding digital information in either DSD format or SACD format and providing an analog output signal having a low signal-to-noise ratio.
  • a variety of methods have been proposed for converting an analog signal to a digital signal and saving the digital signal on a recording medium. Also, a variety of methods have been proposed for converting a saved digital signal to an analog signal.
  • PCM pulse coded modulation
  • DSD direct stream digital
  • analog-to-digital conversion which is used in known SACD (super-audio CD) schemes
  • SACD super-audio CD
  • the audio signal is stored in the form produced by a delta-sigma ADC (analog-to-digital converter).
  • the DSD signal is oversampled by 64Fs (Fs is the sampling frequency 44.1 kHz).
  • Fs is the sampling frequency 44.1 kHz.
  • the signal frequency of a PCM signal produced by the PCM technique and stored in a conventional CD is just Fs. Therefore, in the PCM technique, the analog-to-digital conversion of the stored PCM signal can be accomplished by various techniques, but if it is accomplished by means of a delta-sigma ADC, then decimation filtering to decimate the 64 Fs to 1 Fs is necessary.
  • an analog signal is oversampled in an encoder at 2.8224 MHZ, which is 64 times higher than the sampling frequency of 44.1 kHz, by a delta-sigma type A/D converter to he converted to a 1-bit modulated digital signal.
  • the 1-bit modulated digital signal is saved on a digital signal recording medium.
  • a sequence of the 1-bit digital signals is averaged by an analog low pass filter or the like as it is converted to an analog signal.
  • a European Patent Application EP 0 999 646 A2 describes an apparatus for transmitting and reproducing a digital audio signal wherein a one-bit digital signal that could develop an overflow (clip) depending on its modulation degree is attenuated at a stage upstream of the input of the converter, and is amplified at a stage downstream of the converter to avert a clipped state between the stages.
  • US 5,706,308 discloses a signal processing apparatus for transmitting a digital data string having sigma-delta modulated one bit data. An effective dynamic range information is transmitted together with the digital data thus allowing an adapted adjustment of a down sampling filter.
  • a signal digitized by a delta-sigma type analog-to-digital converter results in a pulse density modulated signal (PDM signal).
  • PDM signal pulse density modulated signal
  • a full-scale amplitude of a source analog signal is reduced to approximately 50% in the digitized signal.
  • the concept of the SACD technique is using a 1-bit datastream, which has a full-scale swing. This bit stream has just two-level information, "1"s and "0"s.
  • the duty ratio chosen for these two levels generally is 50%/50%, and in that case, the averaged analog signal (i.e., low-pass-filtered analog signal) of full-scalc cannot exceed 50 % of the power supply voltage of the averaging circuitry.
  • the full-scale of the digitized signal i.e., the DSD signal, which is analog-to-digital converted by the oversampling modulator
  • the full-scale of the digitized signal is allowed to be 70% of the full-scale amplitude of a source analog signal at its maximum.
  • a full-scale amplitude of an analog output is also reduced to 50%, resulting in a lower S/N ratio for noise in an analog circuit region of the analog low pass filter.
  • a digital signal recorded in accordance with the conventional PCM scheme ensures a full-scale amplitude of 100%, so that the digital signal can be output with an amplitude approximately 100% of the amplitude of the source analog signal for an effective maximum amplitude of an output analog circuit in a digital-to-analog converter.
  • the DSD scheme is disadvantageous over the PCM scheme and the SACD scheme because of the relatively lower S/N ratio associated with the DSD scheme.
  • DA digital-to-analog
  • SACD discs have a double layer of data storage, wherein a conventional PCM signal is stored in one layer as for conventional CD playback mode and the DSD signal is stored in the other layer as for SACD playback mode. It would be desirable to have a CD/SACD player which can inexpensively utilize a single playback circuit to accomplish the playback of music in either the CD mode or the SACD mode from the same SACD disc, and it would be desirable for the CD/SACD player to have a similar level of S/N ratio for output signal produced in both the CD mode and the SACD mode.
  • One technique tries to cause the signal-to-noise ratio (SNR) of the SACD analog output (ie., playback signal) to appear to be higher than the SNR for conventional CD playback by intentionally degrading the CD SNR and enhancing the SACD SNR, in order to show that the SACD scheme is better than the conventional CD scheme. But, it would be desirable to provide a genuinely improved technique for increasing the SACD SNR.
  • SNR signal-to-noise ratio
  • the DSD scheme is disadvantageous over the PCM scheme and SACD scheme in view of the S/N ratio.
  • the present invention provides a method of improving an S/N ratio in digital-to-analog conversion of a pulse density modulated (PDM) digital signal with the steps of claim 1.
  • PDM pulse density modulated
  • the step of extracting the signal component includes digital low pass filtering.
  • the step of matching the full scale may include digitally multiplying the extracted signal.
  • the present invention also provides an apparatus for improving an S/N ratio in digital-to-analog conversion of a pulse density modulated (PDM) digital signal with the features of claim 7.
  • PDM pulse density modulated
  • the digital filtering means may include a digital low pass filter or decimation filter.
  • the full-scale matching means may include multiplying means for digitally multiplying the filtered output signal to generate a digitally multiplied output signal in a digital form.
  • the PDM modulated signal represents a source signal as the density of a pulse train. Specifically, when such a PDM signal is output as it is in the form of voltage, the PDM signal is represented by a waveform which goes up and down between a ground level and a power supply voltage, as shown in Fig. 1 . The amplitude of this waveform is referred to as a first full-scale amplitude.
  • the second full-scale amplitude is smaller than the first full scale amplitude, and is as small as one half of the fun-scale amplitude of the source analog input signal.
  • Fig. 2 shows a relationship between a full scale of an analog source signal input, a full scale of a PDM signal or a first full scale, a full scale of a source signal component included in the PDM signal or a second full-scale amplitude, and a noise amplitude of an output analog circuit such as a digital-to-analog (A/D) converter, on the assumption that a power supply voltage of a delta-sigma type A/D converter is the same as the power supply voltage of the output analog circuit such as the A/D converter.
  • A/D digital-to-analog
  • a digital-to-analog conversion system based on the basic concept of the present invention comprises a S/N ratio improving section 10 which receives a PDM input, and a digital-to-analog (A/D) conversion section 20 which receives the output of the S/N ratio improving section 10.
  • the S/N ratio improving section 10 includes a signal component extractor 100 and a full-scale matching unit 102.
  • the signal component extractor 100 extracts a digital signal component corresponding to a source signal from a PDM digital signal input, and the full-scale matching unit 102, which receives the extracted digital signal component increases the full-scale amplitude of the extracted digital signal component to a desired full-scale amplitude.
  • the digital-to-analog conversion section 20 receives the resulting output from the full-scale matching unit 102, and digital-to-analog converts the digital signal to generate an analog output.
  • the full-scale amplitude of the extracted digital component must be "gained up" i.e., amplified, to improve the SNR of the analog output signal such that the full-scale amplitude of the gained up signal has the desired level compared to the total equivalent input noise of various analog components in the digital-to-analog converters.
  • Fig. 4 schematically represents a relationship between a signal amplitude and a noise level in the foregoing process.
  • a digital base noise (floor noise) within a desired frequency region included in a PDM digital signal is by nature very much lower than a noise level of an analog output circuit (in this embodiment, the digital-to-analog converter).
  • the digital base noise is also increased together with the source signal in the full-scale matching unit 102 (for example, an increase of the source signal level by a factor of 2.0 results in an increase of the digital base noise by a factor of 2.0 as well), the digital base noise is still lower than the noise level of the analog output circuit, and accordingly, the S/N ratio of the output signal produced by digital-to-analog conversion circuit 20 in an implementation of the intervention by the assignee is improved by 6 dB.
  • the foregoing system is configured of a digital filter capable of gain scaling, and a digital-to-analog (A/D) converter.
  • A/D digital-to-analog
  • the digital filter for achieving the present invention is characterized in that when a PDM signal input thereto is oversampled 64 times in a 1-bit organization, a filtered digital signal remains, for example, oversampled 64 times in a 24-bit organization (as in subsequently described Fig. 5 ). Stated another way, assuming that an input PDM signal is comprised of M bits at P x Fs, an output digital signal of the filter is comprised of N bits at Q x Fs, where N ⁇ M and Q ⁇ P. Also, within this digital filter, the full-scale amplitude of the digital source signal component is amplified.
  • the amplification tactor can be chosen according to a predetermined number which is defined from the DSD signal source and the target SNR of the total system.
  • the amplification factor is 2 if the DSD signal was obtained by a delta sigma analog-to-digital-converter having a gain of 50 percent.
  • Another way for setting the amplification factor is by adding a peak detection function after the digital filter, in which case the full-scale signal of in-band frequency is supplied as a PDM one-bit scheme for the reference, and the amplification factor is defined by knowing the peak level of the filtered PDM signal.
  • the amplification factor can be dynamically set in order to gain up the signal so as to satisfy a required distortion number (such as the total harmonic distortion (THD)) of the full-scale signal of the analog output, which is also a predetermined target of the total system (including an analog output amplifier).
  • a required distortion number such as the total harmonic distortion (THD)
  • TDD total harmonic distortion
  • the third full-scale value is chosen and determined according to the particular application in which the described digital-to-analog conversion circuit/method is utilized.
  • the "matching" described herein means providing the gain factor with a value which causes the extracted signal to be amplified or multiplied so as to have a full-scale value that is approximately equal to the third full-scale value of the analog output signal.
  • the third full-scale value of the analog output is a flexible but predetermined value.
  • a digital interpolation filter (as in subsequently described Fig. 7 ) for use in digital-to-analog conversion of a digital signal which is recorded in accordance with the conventional PCM scheme and the SACD scheme.
  • Q > P is satisfied, and the full-scale amplitude remains unchanged.
  • the amplification of the full-scale amplitude (i.e., the volume control) may be implemented by use of a digital multiplier circuit, or by a method of shifting the position of a data bit train to a higher digit.
  • Fig. 5 illustrates a digital-to-anatog conversion system according to one embodiment of the present invention.
  • the system comprises a digital low pass filter 100a; a gain control circuit 102a, and a multibit digital-to-analog (D/A) converter 20a.
  • the digital low pass filter 100a outputs 24-bit data of weighted binary code at 64 Fs, as it is, in the form of parallel data.
  • the gain control preferably is accomplished by a digital multiplier.
  • the 24-bit parallel data is fed to parallel input terminals of the multibit D/A converter 20a corresponding to the respective bit weights.
  • the graphs in Fig. 5 also conceptually show a process in which the gain control circuit 102a, increases the full-scale amplitude of input data, and rejects out-of-band digital noise in the system of Fig. 5 .
  • the graphs in Figs. 5 and 6 clearly indicate the filtering and gaining functions.
  • the full-scale signal is indicated and its magnitude is increased after the gain control function is performed.
  • Fig. 5 shows the input signal spectrum characteristics of an input signal, the gain vs. frequency characteristic of the digital low pass filter 100a, the frequency spectrum of the gain control circuit 102a, and the frequency spectrum of the output of the D/A converter 20a, respectively (a signal component at 10 KHz is also included as an example).
  • Fig. 6 illustrates a digital-to-analog conversion system which is not an embodiment of the invention which employs a decimation filter in a digital signal processing step.
  • the system comprises a decimation filter 100b, a gain control circuit 102b, and a multibit D/A converter 20b.
  • the graphs shown in Fig. 6 correspond to those shown in Fig. 5 .
  • the system of Fig. 6 decimates data three Limes (i.e., increases the number of bits in the data word and divides the data rate by 2 three consecutive times) in the decimation filter 100b after the data has been low-pass-filtered.
  • the input data is converted to 20-bit binary data at 8 Fs.
  • the clock rate of the digital data train is reduced by a factor of 8, so that the conversion rate of the multibit D/A converter 20b can be reduced.
  • the gain control circuit 102b increases the full-scale amplitude of the extracted digital signal, and, in cooperation with decimation filter 100b, rejects out-of-band digital noise.
  • the decimation of data causes aliasing of noise into the signal band, so the noise level within the band is increased as compared with the embodiment of Fig. 5 , which does not perform decimation.
  • the present invention filters a PDM digital input signal in a digital domain to extract a source signal, amplifies the full-scale amplitude of the extracted source signal, and then digital-to-analog converts the amplified source signal to fully extend the output to an effective amplitude level of an analog output circuit, thereby making it possible to achieve a high S/N ratio to noise involved in the analog output circuit.
  • Figs. 7 and 9 show how a CD system and a DSD system can be configured to provide their respective outputs as inputs to a single shared audio amplifier.
  • the system 1A is shown wherein either/both information encoded by an SACD encoder 12 and written into a recording medium 13A such as a CD disc, and information encoded by a DSD encoder 22 and written into a recording medium 13B, can be decoded and amplified by a decoding system including an CD decoder 14 and a DSD decoder 24A.
  • the system 1A also includes a digital switch circuit 25 which selectively couples a 24 bit output 18A from CD decoder 14 or the 24 bit output 18B of DSD decoder 24A to the input of a digital-to converter 20.
  • the output 28 of digital-to-analog converter 20 drives a speaker 31, as shown in Fig. 9 .
  • the PCM signal stored on a CD generally is a 16 bit signal. In the embodiments of Figs. 7 and 8 , the 16-bit PCM signal is converted to a 24-bit PCM signal by some data processing (not shown) before being applied to the input of the interpolation filter 15.
  • CD decoder 14 thus receives a 1Fs 24-bit PCM signal as its digital input from CD disc 13A, and produces an analog output signal 18A which is applied to one input of digital switch circuit 25 of Fig. 9 .
  • CD decoder 14 includes an 8x digital interpolation filter 15 which digitally filters the digital input received from CD disc 13A to produce an 8Fs 24 bit digital signal on the bus 19 and applies it to the input of an interpolator 33.
  • Interpolator 33 produces a 64Fs 24 bit digital signal on bus 18A to one input of digital switch 25 , which provides the selected signal 18A or 18B to the input of digital-to-analog converter 20.
  • digital-to-analog converter 20 includes a delta sigma modulator 44 having its 24-bit input connected to the output of switch circuit 25.
  • the output of delta sigma modulator 44 is connected to the input of digital-to-analog conversion element circuitry 46, the output of which is filtered by an analog low pass filter 48.
  • the number of bits of the output of delta sigma modulator 44 is selected depending on the topology of the delta sigma modulator, which is designed according to the in-band and out-of-band signal spectrum requirements.
  • the output of analog low pass filter 48 is connected to the input of an amplifier 50, which produces the analog output signal 28 connected to drive the speaker 31.
  • Digital-to-analog conversion element circuit 46 can be selected on the basis of the integrated circuit manufacturing process technology utilized and on the basis of various other factors of hardware implementation. Note that a variety of known digital-to-analog conversion element/techniques can be utilized to accomplish the function of block 46.
  • DSD decoder 24A is essentially the system disclosed in above described Fig. 3 , and can be implemented either as shown in above described Fig. 5 or above described Fig. 6 .
  • DSD decoder 24A includes digital filter I 00a which filters the 64Fs one-bit DSD signal and applies result to digital gain control circuit 102a to produce a 64Fs 24 bit digital signal on the bus 18B, which is applied to the other input of digital switch circuit 25.
  • the amplitudes of two kinds of processed audio digital signals can be matched in the digital domain. Accordingly, the expensive analog components can be shared for each digital signal code playback without any manual control of attenuation in the analog domain. As a result, degradation of the DSD signal S/N ratio at the analog output 28 can be eliminated.
  • the system shown in Fig. 8 is similar to that of Fig. 7 . except that in Fig. 8 the CD decoder includes only the 8x interpolation digital filter 15 and produces the output on bus 18A as an 8Fs 24 bit digital signal, and DSD decoder 24B includes a decimation filter 100b having its output connected to the input of the gain control circuit 102b to produce a 8Fs 24 bit digital signal on bus 18B.
  • the major difference between the systems of Figs. 7 and 8 is the oversampling rate of the digital signal prior to digital-to-analog converter 20, which is chosen based on the switching speed limitations of the selected digital-to-analog conversion element circuit 46.
  • the present invention improves the SNR in digital-to-analog conversion of a digital signal which has a reduced full-scale amplitude compared to the full-scale amplitude of a source analog signal represented by a digital, such as a PDM digital signal recorded in accordance with the DSD scheme.
  • the invention provides improved performance of a DSD digital-to-analog conversion system that is equivalent to the performance of a conventional CD system.
  • the present invention also provides a digital-to-analog conversion system that decodes information in either DSD format or PCM format so as to produce a substantially equivalent analog output signal in either case.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Analogue/Digital Conversion (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
EP01114242A 2000-06-14 2001-06-12 Method and apparatus for improving S/N ratio in digital-to-analog conversion of pulse density modulated (PDM) signal Expired - Lifetime EP1168631B1 (en)

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JP2000178389 2000-06-14
JP2000178389A JP4454109B2 (ja) 2000-06-14 2000-06-14 パルス密度変調信号（ｐｄｍ）のデジタル−アナログ変換処理におけるｓｎ比改善の方法および装置

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EP1168631A2 EP1168631A2 (en) 2002-01-02
EP1168631A3 EP1168631A3 (en) 2004-09-22
EP1168631B1 true EP1168631B1 (en) 2008-07-23

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JP2001358592A (ja) 2001-12-26
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EP1168631A2 (en) 2002-01-02
US20020018013A1 (en) 2002-02-14
US6489909B2 (en) 2002-12-03
EP1168631A3 (en) 2004-09-22

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