EP1166276B1 - Integrierter ferroelektrischer speicher, dessen plattenleitungen vom spaltendecoder selektiert werden - Google Patents

Integrierter ferroelektrischer speicher, dessen plattenleitungen vom spaltendecoder selektiert werden Download PDF

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Publication number
EP1166276B1
EP1166276B1 EP00925064A EP00925064A EP1166276B1 EP 1166276 B1 EP1166276 B1 EP 1166276B1 EP 00925064 A EP00925064 A EP 00925064A EP 00925064 A EP00925064 A EP 00925064A EP 1166276 B1 EP1166276 B1 EP 1166276B1
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EP
European Patent Office
Prior art keywords
lines
plate
column decoder
sense amplifier
assigned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP00925064A
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German (de)
English (en)
French (fr)
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EP1166276A1 (de
Inventor
Tobias Schlager
Heinz Hönigschmid
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
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Infineon Technologies AG
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Publication of EP1166276A1 publication Critical patent/EP1166276A1/de
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements

Definitions

  • the invention relates to an integrated memory, the Memory cells are connected to plate lines.
  • From US 5,592,410 A is a ferroelectric memory in Form of a FRAM or FeRAM (Ferroelectric Random Access Memory) described. Its memory cells have selection transistors and storage capacitors. The storage capacitors have a ferroelectric dielectric that is dependent of a stored logical state different Can assume polarization states. The state of polarization affects the capacitance of the storage capacitor.
  • One electrode of each storage capacitor is over the corresponding one Selection transistor with a bit line of the memory connected.
  • a control terminal of the selection transistor is connected to a word line of the memory.
  • a second Electrode of the storage capacitor is with a plate line connected. During a read access, the selection transistor switched on and the potential of the plate line pulsed from a low to a high potential. The change in potential on that with the memory cell connected bit line is then evaluated. It is a measure of the polarization dependent capacitance of the storage capacitor and is therefore used for a determination of the logical state stored in each case.
  • the word lines run vertically to the bit lines and the plate lines parallel to the Word lines.
  • Each plate line is with the same output connected to a word decoder, with which the associated Word line is connected.
  • By activating one of the word lines is always the corresponding one at the same time Plate line activated. This leads to that-all-about the each activated word line selected memory cells by the pulsed signal on the plate line connected to them influence the potential on the associated bit line.
  • An integrated memory according to DE 41 18 847 is the preamble of claim 1 known.
  • the invention has for its object an integrated Specify memory of the memory cells with storage capacitors has, which are connected to plate lines, and where only the potential when activating a word line on part of the bit lines crossed by the word line through pulsed signals on the plate lines being affected.
  • the plate lines are connected to the storage capacitors of the memory cells are connected in parallel arranged to the bit lines.
  • One of the plate lines at a time and at least one of the bit lines are the same Memory cells connected.
  • a column decoder is used Selection of one of the plate lines depending on an adjacent one Column address.
  • the figure shows an FRAM with memory cells MC of the one-transistor / one-capacitor type.
  • the memory cells MC are in Crossing points of bit lines BL and word lines WL are arranged.
  • the bit lines BL and word lines WL run perpendicular to each other.
  • the store has a variety of Plate lines PL, which are parallel to the bit lines BL are arranged.
  • the bit lines are pairs of bit lines summarized. To simplify matters, the figure only a bit line BL of each bit line pair is shown. In Reality always becomes when one of the bit lines BL is selected a complementary bit line is selected at the same time, a read access to one of the memory cells MC provides the corresponding reference signal.
  • a memory cell MC is shown enlarged in the figure. It has a selection transistor TM and a storage capacitor CM on.
  • the storage capacitor CM has a ferroelectric dielectric. Its an electrode via the selection transistor TM with the associated bit line BL connected. His other electrode is with one of the plate wires PL connected.
  • the gate of the selection transistor TM is connected to one of the word lines WL.
  • the bit lines BL are each via a first n-channel transistor T1 with an associated differential sense amplifier SA connected.
  • the figure shows a total of four sense amplifiers SA, each of which is assigned four bit line pairs BL are.
  • Each sense amplifier SA is via two second transistors T2 connected to a pair of data lines DLi.
  • a write access is data over the data lines DLi to the sense amplifiers SA and from them via the bit lines BL transferred to the memory cells MC. With a read access data is transmitted in the opposite direction, wherein the sense amplifiers for amplifying the Read out setting differential signal on the respective Bit line pair serve.
  • each column CLi Four of the bit line pairs BL are each one column CLi summarized. The figure shows a total of four columns CLi.
  • accessing the memory cells MC is only in each case one of the columns CLi selected so that, for example in the case of a read access, the sense amplifiers SA only for amplification of data supplied by this column CLi.
  • the word lines are with outputs of a row decoder RDEC connected, the row addresses RADR can be fed.
  • the Row decoder selects one of the word lines WL depending on the respective line address RADR.
  • Each of the bit line pairs BL is one of the plate lines PL assigned.
  • the plate lines PL are dashed in the figure shown.
  • the four plate lines PL each Column CLi are electrically connected to each other .. They are via a column selection line CSLi with outputs a column decoder CDEC connected.
  • the column decoder CDEC column addresses can be supplied to CADR. Depending on the feed Column addresses CADR are selected by the CDEC column decoder one of the column selection lines CSLi. On this selected Column line CSLi is generated by the column decoder CDEC those for a read access or write access to the memory cells required pulsed signals for those with the respective column selection line CSLi connected plate lines PL.
  • the pulsed signal can, for example, the in the US 5,592,410 A have shown course.
  • the four plate lines PL of each column CLi are on their end facing away from the column decoder with the control connections the first transistors assigned to the respective column CLi T1 connected.
  • the figure also shows an OR gate OR with four inputs. Each of these inputs is connected to the four plate lines PL connected to each column CLi.
  • the output of the OR gate OR is AND1 with the first input of a first AND gate connected, the output of which is connected to an activation unit AKT each sense amplifier SA is connected.
  • a second entrance of the first AND gate AND1 is with an activation line CSA affiliated.
  • the activation units AKT are used for activation of the respective sense amplifier SA if they have a high Level is supplied. This is the case if both that Activation signal CSA as well as the output of the OR gate OR have a high level.
  • the output of the OR gate OR is also a first Input of a second AND gate AND2 connected, its output with the control connections of the second transistors T2 connected is.
  • a second input of the second AND gate AND2 is connected to a selection line DLS.
  • the second Transistors T2 become conductive via the second AND gate AND2 switched when both the selection signal DLS and the output signal of the OR gate OR have a high level.
  • the plate lines PL are in the unselected state a low level.
  • the column decoder CDEC depending on the column address applied to it CADR the corresponding column selection line CSLi. He transmits the for the via this column selection line CSLi Read out required pulsed signals to the four plate lines PL of the selected column CLi. Pulsed over this On the one hand, signals are assigned to the eight CLi in this column first transistors T1 turned on. simultaneously occur at the output of the OR gate OR also pulsed Signals on.
  • the activation management CSA and the selection management DLS take on a high level.
  • the four sense amplifiers SA through the first AND gate AND1 and their Activation units AKT by the output signal of the OR gate OR activated, for example, with a Supply potential of the integrated circuit connected become.
  • the output signal of the OR gate OR is via the second AND gate AND2 also the control connections of the second Transistors T2 supplied, so that they also pulsed in time Signals are switched on.
  • the column decoder CDEC is used So both the selection of the plate lines PL and the Activation of the first transistors T1 in one of the columns CLi, of the four sense amplifiers SA and the one connected to them eight second transistors T2.
  • the invention can also only one or two of the three mentioned Elements over the plate lines PL with the column decoder CDEC connected.
  • the OR gate OR is necessary because in this embodiment the sense amplifiers SA in the multiplex for amplification of data supplied from the four different columns CLi serve. So they have to be activated every time, if only one of the columns CLi selected by the column decoder CDEC becomes.
  • the figure shows only a section of a larger one Memory, the multiple groups of four sense amplifiers SA with the associated first transistors T1 and second transistors T2 and the connected memory cells MC. All of these groups are through their eight second transistors T2 connected to the same four data line pairs DLi.
  • the CDEC column decoder is only used in each case a column CLi is selected in one of the sense amplifier groups, so that only from this selected column CLi Read access four data bits via the associated sense amplifier SA are transmitted to the data line pairs CLi. So during each column CLi a different column address CADR is assigned the activation line CSA and the selection line DLS common to all sense amplifier groups.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
EP00925064A 1999-04-01 2000-04-03 Integrierter ferroelektrischer speicher, dessen plattenleitungen vom spaltendecoder selektiert werden Expired - Lifetime EP1166276B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19915081A DE19915081C2 (de) 1999-04-01 1999-04-01 Integrierter Speicher, dessen Speicherzellen mit Plattenleitungen verbunden sind
DE19915081 1999-04-01
PCT/DE2000/000997 WO2000060602A1 (de) 1999-04-01 2000-04-03 Integrierter ferroelektrischer speicher, dessen plattenleitungen vom spaltendecoder selektiert werden

Publications (2)

Publication Number Publication Date
EP1166276A1 EP1166276A1 (de) 2002-01-02
EP1166276B1 true EP1166276B1 (de) 2002-12-04

Family

ID=7903387

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00925064A Expired - Lifetime EP1166276B1 (de) 1999-04-01 2000-04-03 Integrierter ferroelektrischer speicher, dessen plattenleitungen vom spaltendecoder selektiert werden

Country Status (7)

Country Link
US (1) US6430080B1 (zh)
EP (1) EP1166276B1 (zh)
JP (1) JP2002541609A (zh)
KR (1) KR100419539B1 (zh)
CN (1) CN1156850C (zh)
DE (2) DE19915081C2 (zh)
WO (1) WO2000060602A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6920059B2 (en) * 2002-11-29 2005-07-19 Infineon Technologies Aktiengesellschaft Reducing effects of noise coupling in integrated circuits with memory arrays
DE102004050037B4 (de) * 2003-10-09 2015-01-08 Samsung Electronics Co., Ltd. Speicherbauelement, Speichersystem und Betriebsmodussetzverfahren
DE602006004396D1 (de) * 2005-05-18 2009-02-05 St Microelectronics Sa EEPROM-Speicherarchitektur
JP4191217B2 (ja) * 2006-09-20 2008-12-03 エルピーダメモリ株式会社 半導体装置
FR2972838B1 (fr) * 2011-03-18 2013-04-12 Soitec Silicon On Insulator Memoire a semi-conducteurs comportant des amplificateurs de lecture decales associes a un decodeur de colonne local

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4873664A (en) * 1987-02-12 1989-10-10 Ramtron Corporation Self restoring ferroelectric memory
US5400275A (en) * 1990-06-08 1995-03-21 Kabushiki Kaisha Toshiba Semiconductor memory device using ferroelectric capacitor and having only one sense amplifier selected
US5592410A (en) * 1995-04-10 1997-01-07 Ramtron International Corporation Circuit and method for reducing a compensation of a ferroelectric capacitor by multiple pulsing of the plate line following a write operation
KR100306823B1 (ko) * 1997-06-02 2001-11-30 윤종용 강유전체메모리셀들을구비한불휘발성메모리장치
JPH11273360A (ja) * 1998-03-17 1999-10-08 Toshiba Corp 強誘電体記憶装置
US5963466A (en) * 1998-04-13 1999-10-05 Radiant Technologies, Inc. Ferroelectric memory having a common plate electrode
US6147895A (en) * 1999-06-04 2000-11-14 Celis Semiconductor Corporation Ferroelectric memory with two ferroelectric capacitors in memory cell and method of operating same
JP3319437B2 (ja) * 1999-06-04 2002-09-03 ソニー株式会社 強誘電体メモリおよびそのアクセス方法

Also Published As

Publication number Publication date
WO2000060602A1 (de) 2000-10-12
CN1156850C (zh) 2004-07-07
JP2002541609A (ja) 2002-12-03
KR100419539B1 (ko) 2004-02-21
DE50000874D1 (de) 2003-01-16
CN1346494A (zh) 2002-04-24
US20020054501A1 (en) 2002-05-09
DE19915081A1 (de) 2000-10-12
US6430080B1 (en) 2002-08-06
EP1166276A1 (de) 2002-01-02
DE19915081C2 (de) 2001-10-18
KR20020012164A (ko) 2002-02-15

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