EP1145296B1 - Procede de fabrication de plaquettes a semiconducteurs - Google Patents

Procede de fabrication de plaquettes a semiconducteurs Download PDF

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Publication number
EP1145296B1
EP1145296B1 EP99970208A EP99970208A EP1145296B1 EP 1145296 B1 EP1145296 B1 EP 1145296B1 EP 99970208 A EP99970208 A EP 99970208A EP 99970208 A EP99970208 A EP 99970208A EP 1145296 B1 EP1145296 B1 EP 1145296B1
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EP
European Patent Office
Prior art keywords
wafer
grinding
polishing
finish
deformation
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Expired - Lifetime
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EP99970208A
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German (de)
English (en)
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EP1145296A1 (fr
Inventor
Tomohiro Hashii
Kazunori Onizaki
Sumihisa Masuda
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Sumco Corp
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Sumco Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B1/00—Processes of grinding or polishing; Use of auxiliary equipment in connection with such processes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
    • B24B37/08—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
    • B24B7/10—Single-purpose machines or devices
    • B24B7/16—Single-purpose machines or devices for grinding end-faces, e.g. of gauges, rollers, nuts, piston rings
    • B24B7/17—Single-purpose machines or devices for grinding end-faces, e.g. of gauges, rollers, nuts, piston rings for simultaneously grinding opposite and parallel end faces, e.g. double disc grinders
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B9/00—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor
    • B24B9/02—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground
    • B24B9/06—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain
    • B24B9/065—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain of thin, brittle parts, e.g. semiconductors, wafers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/928—Front and rear surface processing

Definitions

  • the present invention relates to a manufacturing method which produces a semiconductor wafer of high flatness, and low process deformation from a single crystal ingot.
  • this manufacturing method comprises a process, wherein a wafer is sliced from a single crystal ingot, then subjected to surface grinding and finish grinding on both sides at the same time, undergoes low-deformation chamfering using a fixed abrasive, polished on both sides simultaneously, and is subjected to edge-rounded polishing, after which it is finish polished again on one side.
  • the present invention relates to a manufacturing method which performs low deformation grinding and polishing of a chamfered portion between surface grinding and polishing, and produces a high-precision semiconductor wafer, with high flatness, and low process deformation required by large-diameter quality wafers, making it possible to enhance yields in the device process.
  • a semiconductor wafer manufacturing method comprises the following processes.
  • Japanese Patent Laid-open No. 8-316180 a method, which after slicing, subjects a wafer to chamfering, two-sided surface grinding, and then uses chemical polishing to finish the wafer.
  • Japanese Patent Laid-open No. 9-248740 a method, which after slicing, subjects a wafer to two-sided surface grinding, performs etching as needed to remove residual deformation, and then uses chemical polishing to finish both sides of the wafer.
  • Japanese Patent Laid-open No. 9-260314 Japanese Patent Laid-open No. 9-270396
  • a method which after slicing, subjects a wafer to edge chamfering and one-sided surface grinding, performs etching as needed to remove residual deformation, washes the wafer, and then uses chemical polishing to finish both sides of the wafer.
  • Japanese Patent Laid-open No. 9-260314 a method, which after slicing, subjects a wafer to chamfering, one-sided surface grinding, lapping, then after performing dry etching, uses chemical polishing to finish both sides of the wafer.
  • the Document EP 0 764 976 A1 describes a method for processing a wafer obtained by slicing an ingot.
  • the peripheral portion of the wafer is rounded by grinding to reduce the danger of peripheral parts being chipped off during further processing.
  • one or both surfaces of the wafer are lapped to compensate variations in wafer thickness and parallel orientation of the surfaces.
  • a preferably alkaline surface etching is performed to remove surface portions that are cracked and roughened or contaminated by grains of abrasive. Both surfaces of the wafer are then polished simultaneously to improve flatness of the wafer, although this step is described as not being essential following an acid etching.
  • the entirety of the peripheral wafer portion is then honed to compensate a deformation of the sectional shape of the chamfered peripheral portion of the wafer, caused in a preceding step, i.e. to improve smoothness and the sectional shape which were damaged by the preceding lapping, etching and both-sided polishing. Thereafter, the entire chamfered peripheral portion is polished to remove residual strain of the surface layer caused by the honing, and to prevent a generation of chips or fine particles in subsequent use of the wafer for manufacturing a semiconductor device. Finally, the front surface of the wafer is polished.
  • the steps of honing and then polishing the peripheral wafer portion are replaced by again rounding the peripheral portion of the wafer by grinding to compensate the plan and sectional shapes of the chamfered portion which were damaged by preceding lapping and etching steps, and to improve the smoothness, and then polishing the peripheral portion of the wafer to remove working damage caused by the preceding grinding step, and to prevent formation of chips and fine particles in subsequent device manufacturing.
  • the Document US 4,588,473 A describes a process for producing semiconductor wafers by transversely slicing a single-crystal semiconductor rod to obtain wafers, lapping each wafer, bevel machining the edge part of each wafer, chemically machining the entire surface of the wafer, i.e. etching all surfaces of the wafer to remove imperfections such as cutting marks and to make these surfaces smooth, and then mirror polishing the opposite faces and the bevelled edge part in a single process step.
  • the polishing of the bevelled edge part is performed to prevent a formation of dust particles and a growth of easily pulverized dendrite crystals on the bevelled surface when during production of a semiconductor device an oxide film is formed on the wafer followed by a deposition of silicon nitride.
  • an objective of the present invention to attempt to increase the precision of a wafer by incorporating a low-deformation grinding process into the wafer manufacturing process. Further, an objective of the present invention is to provide a novel high-precision semiconductor wafer manufacturing method, which is capable of reducing total materials costs, and especially which enables the realization of the high degree of flatness and low process deformation required by large-diameter wafers, and enhances yields in the device process.
  • the inventors undertook a variety of studies concerning grinding and polishing processes, having as an objective the realization of a high degree of flatness and low process deformation in a semiconductor wafer, and enhanced yields in the device process. As a result, the inventors learned that it is possible to achieve the above-mentioned objective in a semiconductor wafer manufacturing method.
  • a wafer is sliced from a single crystal ingot, mirror polished on a required side by performing a surface grinding process of various processes, followed by applying a mirror finish process of various processes for making the chamfered portion of a wafer a mirror finish with low deformation. Then finally the wafer is finish polished on a required main side of a chamfered wafer.
  • the inventors learned that various processes can be applied, such as, 2-stage processes to each of the above-mentioned surface grinding process, a chamfered portion mirror finish process, and a process for mirror finish polishing a required main surface, which are employed in the process of the present invention. Furthermore, the inventors brought the present invention to completion based on the knowledge that it is possible to achieve the above-mentioned object more efficiently by interposing a chamfered portion grinding and polishing process between the surface grinding process and the process for mirror finish polishing a required main surface.
  • Fig. 1 is a graph comparing wafer flatness in accordance with a conventional method and the method of the present invention.
  • Fig. 2 is a graph comparing wafer surface roughness in accordance with a conventional method and the method of the present invention.
  • the present invention is a semiconductor wafer manufacturing method, in which a wafer is sliced from a single crystal ingot and a required surface is finished to a mirror finish.
  • this method is characterized in that it introduces a chamfered portion mirror finishing process, which mirror finishes with low deformation to the chamfered portion of a wafer.
  • chamfered portion mirror finishing process comprising a chamfering process (c-1) which performs grinding with low deformation, and a chamfered portion polishing process (c-2) which performs finish polishing, or; (d) comprising a mirror finish polishing of a single or plurality of stages.
  • a process comprising a two-sided primary polishing process (e), which performs primary polishing of both sides of a wafer, and a one-sided finish polishing process (f), which finish polishes one side of a wafer that has been primary polished on both sides.
  • e two-sided primary polishing process
  • f one-sided finish polishing process
  • a grinding process which performs double-sided grinding of both sides of a wafer
  • a chamfering process which performs low-deformation grinding of the chamfered portion of a wafer.
  • a two-sided primary polishing process (e) is carried out which performs primary polishing on both sides of a wafer, a chamfered portion polishing process (c-2), which finish polishes the chamfered portion of a wafer.
  • a one-sided finish polishing process (f), which finish polishes one side of a wafer is performed.
  • simultaneously grinding or polishing a plurality of wafers, and making the thickness of all the wafers fall within a required range prior to carrying out chamfering processing makes it possible to improve processing precision by making the bevel width uniform, and to reduce the generation of particles in the device process, thus enabling improved yields.
  • performing chamfering after carrying out double-sided grinding and/or two-sided polishing, during which it is possible for the wafer peripheral portion to come in contact either with other wafers or a carrier or other kind of apparatus prevents damage to the chamfered portion, making it possible to reduce particle generation in the device process, and enabling improved yields.
  • the slicing process either produces a thin disc-shaped wafer by slicing a single crystal ingot using the inner diameter of a cutting blade, or produces a wafer using an apparatus called a wire saw by bringing a moving thin wire in contact with and slicing a single crystal ingot while applying a grinding slurry. To lessen the load on the grinding process, it is desirable that a wafer be sliced with extremely high flatness, and good surface roughness.
  • double-sided grinding is performed with an objective of finishing with good thickness precision and flatness for a wafer produced by a slicing process. That is removing the waviness on a wafer produced by slicing, and removing the process deformed layer produced by slicing.
  • double-sided grinding can make the depth of the process deformed layer of the surface of a wafer less than 10 ⁇ m. It is also capable of removing the waviness on a wafer produced by slicing, by performing grinding on both sides of a wafer simultaneously with a fixed abrasive without using a free abrasive.
  • a grinding wheel with a particle size of around #325 ⁇ #3000 can be utilized, and as the diamond bonding agent for making a fixed abrasive, a metal, vitrified, or resin bonding agent can be utilized as the abrasive bond.
  • the double-sided grinding process makes use of a vertical double-sided grinding apparatus, which disposes between an upper grinding wheel and a lower grinding wheel a carrier capable of holding one or a plurality of wafers.
  • the upper and lower grinding wheels are rotated at high speed by separate and independent drive mechanisms, enabling double-sided grinding to be performed on sliced wafers (not yet chamfered), which are held in a carrier that rotates at low speed.
  • a single wafer-type apparatus which performs double-sided grinding on a single wafer that is not held in a carrier, can also be used.
  • the finish grinding process it is possible to make the depth of the process deformed layer of the surface of a wafer around 2 ⁇ 3 ⁇ m, and it is also possible to make the total thickness variation (TTV) less than 1 ⁇ m by using a fine fixed abrasive. Therefore the etching process, which is effective at removing the process deformed layer, can be omitted. This enables the prevention of wafer precision deterioration resulting from etching.
  • a grinding wheel with particle size of around #2000 ⁇ #8000 can be used, and a metal, vitrified, or resin bonding agent can be utilized as the abrasive bond.
  • finish grinding process enables the provision of a high precision wafer to the subsequent two-sided primary polishing process and the one-sided finish polishing process, production costs can be greatly reduced. Also, omitting the lapping process and the etching process also enables industrial wastes to be reduced.
  • a constitution wherein single wafer grinding is performed in accordance with a highly rigid vertical surface grinding apparatus.
  • a structure in which there is disposed a rotating table, which is rotated at high speed by a drive mechanism can be used.
  • grinding wheels can be utilized, which are rotated at high speed by a drive mechanism, they are disposed above and below the above-mentioned table so as to be able to move close to and away from.
  • a constitution wherein a ceramic plate is provided on a rotating table, and grinding is performed by vacuum clamping a wafer using a vacuum chuck.
  • the two-sided primary polishing process is performed for the purpose of removing the process deformed layer generated by the above-mentioned grinding process; while maintaining the flatness of the wafer which was planarized in the above-mentioned grinding process.
  • Pressurized polishing is performed by supplying a polishing slurry, and using a polishing cloth comprising urethane foam.
  • the particle size of the polishing slurry is not especially limited, e.g., and a colloidal silica, with a particle size of between 10 ⁇ 270nm can be utilized.
  • An example of an apparatus that can be used in the two-side primary polishing process constitutes, for example, upper and lower plates having polishing pads and being disposed opposite one another.
  • the lower plate being equipped with a sun gear in the center, an internal gear on the outer side, and a geared carrier being held between these gears.
  • the carrier holding a plurality of wafers and sandwiched between the polishing pads of the upper and lower plates, is autorotated and made to revolve. Hence, this enables the two-sided polishing of the wafers by the application of pressure from the upper plate.
  • the one-sided finish polishing process can make use of a constitution, wherein single-wafer polishing is performed using the same constitution as the above-mentioned highly rigid vertical polishing apparatus.
  • a constitution wherein an upper plate having a polishing pad is rotated at high speed, and is capable of applying pressure to the upper surface of a rotating table, which is also rotated at high speed.
  • the rotating table is equipped with a ceramic plate, and polishing is performed by vacuum clamping a wafer in a vacuum chuck. It is possible to use the same polishing pad and polishing slurry as that utilized in the two-sided primary polishing process.
  • the low-deformation chamfering process can make use of a constitution which enables the vacuum clamping of a wafer by a vacuum chuck. Also at the peripheral portion of a rotating table which is rotated at high speed, a grinding wheel for peripheral grinding and a grinding wheel for notch grinding, which are rotated at high speed, make it possible to perform soft grinding.
  • a grinding wheel particle size of around #325 ⁇ #6000 can be used, and a metal, vitrified, or resin bonding agent can be utilized as the abrasive bond.
  • the diametric depth of the process deformed layer can be made 2 ⁇ 3 ⁇ m. Therefore the roughness of the edge can be finished favorably, and an extremely smooth edge can be achieved using a subsequent edge finish polishing process alone.
  • the edge finish polishing process in a constitution that is the same as the above-mentioned edge polishing apparatus, for example, can make use of a constitution which disposes at the peripheral portion a low speed rotating table and a high speed polishing cloth-equipped buff. This makes it possible to achieve a smooth edge.
  • polishing In low-deformation chamfering and chamfered portion polishing, it is possible to use a method in which polishing is carried out at a prescribed pressure while supplying a polishing slurry to a polishing cloth-equipped buff.
  • a colloidal silica with a particle size of between 20 ⁇ 300nm, for example, can be utilized as the polishing slurry.
  • a wafer manufacturing method was implemented using the following conditions. That is, in the slicing process (A), a single-crystal silicon ingot pulled using a single-crystal pulling apparatus was sliced in a certain fixed direction, and finished to a thin disc-shaped wafer.
  • double-sided grinding is performed using a double-sided grinding process (B), which grinds up to 50 ⁇ m from both sides of the wafer.
  • B double-sided grinding process
  • a low-deformation chamfering process (C) was performed on the wafer that had undergone this double-sided grinding.
  • horizontal grinding wheels were utilized in the peripheral grinding wheel, and the notch grinding wheel. Furthermore grinding was carried out at a prescribed cutting speed while supplying a grinding agent to the peripheral grinding wheel and the notch grinding wheel. It was ascertained that an abrasive of between #325 ⁇ #6000 can be utilized.
  • a wafer subjected to this double-sided grinding and low-deformation chamfering was further planarized via a finish grinding process (D).
  • D finish grinding process
  • a diamond cup wheel with a particle size #2000 ⁇ #8000 was utilized. Grinding was performed at a prescribed cutting speed while supplying a grinding agent.
  • the above-mentioned wafer which was planarized by finish grinding, was subjected to a subsequent two-sided primary polishing process (E). This removed the process-deformed layer of the surface of a wafer while maintaining flatness.
  • a polishing cloth comprising a urethane foam was mounted to the upper and lower plates, and polishing was performed under a prescribed pressure while supplying a polishing slurry having a colloidal silica particle size of between 10 ⁇ 270nm to the upper and lower plates.
  • One-sided finish polishing utilized a method, in which a polishing cloth comprising a urethane foam and a nonwoven fabric was mounted to a plate. Then polishing was performed under a prescribed pressure while supplying to the plate a polishing slurry based on a colloidal silica with a 10 ⁇ 270nm particle size.
  • the first example comprises (A) a slicing process, (B) a double-sided grinding process, (C) a low-deformation chamfering process, (D) a finish grinding process, (E) a two-sided primary polishing process, (F) a low-deformation chamfering process, (G) a chamfered portion polishing process, and (H) a one-sided finish polishing process.
  • a wafer was manufactured having as a conventional process 1) a slicing process, 2) a chamfering process, 3) a lapping process, 4) an etching process, 5) a chamfered portion polishing process, 6) a one-side polishing process, and 7) a finish polishing process.
  • the lapping process utilized a method in which a wafer was loaded into a carrier and sandwiched between an upper and a lower plate. Then processing was performed under a fixed pressure while supplying a free-abrasive slurry.
  • the etching process utilized a method in which a wafer was immersed in an acidic solution, such as hydrofluoric acid, nitric acid, or acetic acid, to remove a damaged layer resulting from the lapping process.
  • Fig. 1 and Fig. 2 The flatness and surface roughness of the resulting wafers were measured, and the results thereof are shown in Fig. 1 and Fig. 2 .
  • flatness achieved with the conventional method was a TTV average (AVE) of 0.69 ⁇ m
  • LTV local thickness variation
  • that achieved with the method of the present invention was a TTV AVE of 0.48 ⁇ m
  • an LTV AVE of 0.21 ⁇ m Further, compared to a surface roughness achieved with the conventional method of Ra MAX 0.79 ⁇ m, Ra MIN 0.54 ⁇ m, and Ra AVE 0.69 ⁇ m, that achieved with the method of the present invention was Ra MAX 0.58 ⁇ m, Ra MIN 0.32 ⁇ m, and Ra AVE 0.46 ⁇ m.
  • a wafer was manufactured using a process, which omitted the (F) low-deformation chamfering process in the first example, but kept all the other conditions the same.
  • This second example confirmed that it is possible to achieve a wafer having the same levels of flatness and surface roughness as those of the first example.
  • a wafer was manufactured using a process, which reversed the order of the (C) low-deformation chamfering process and (D) finish grinding process in the second example to (D), (C), but kept all the other conditions the same as those in the first example.
  • This third example confirmed that it is possible to achieve a wafer having the same levels of flatness and surface roughness as those of the second example.
  • a wafer was manufactured using a process, which omitted the (D) finish grinding process and the (F) low-deformation chamfering process in the first example, but kept all the other conditions the same.
  • This fourth example confirmed that it is not possible to achieve the same levels of flatness and surface roughness as those of the first example, but is possible to achieve a wafer of higher precision than that of the conventional first comparative example.
  • the present invention comprises a process of a chamfered portion mirror finishing process, which results in low deformation on a wafer, which has undergone a slicing process. As well as a surface grinding process, and a mirror finish polishing process, which mirror finish polishes a required main side of a chamfered wafer. It is possible to manufacture a wafer with a high degree of flatness, which enables improved yields in the semiconductor wafer manufacturing process.
  • the wafer is subjected to a slicing process; a grinding process in which double-sided grinding is performed on a sliced wafer; a finish grinding process in which high-precision and low-deformation finish grinding is performed on the above-mentioned wafer; a chamfering process in which low-deformation grinding is performed on the chamfered portion of the above-mentioned wafer; a two-sided primary polishing process in which primary polishing is performed on both sides of a chamfered wafer; a one-sided finish polishing process in which finish polishing is performed on one side of a wafer that has been primary polished on both sides; and a process in which finish polishing is performed on the chamfered portion of the above-mentioned wafer.

Abstract

La présente invention concerne un nouveau procédé de fabrication haute précision de plaquettes à semi-conducteurs qui tente d'obtenir une plaquette haute précision en incorporant un traitement à meulage à faible déformation. Il permet une réduction des coûts matière totaux, et réalise le haut degré de planéité et la faible déformation du traitement requis, dans le cas des plaquettes de grand diamètre notamment. De la sorte, il devient possible d'améliorer le rendement dans le traitement du dispositif. La présente invention rend possible l'obtention d'un haut degré de planéité et une faible déformation du traitement. L'invention contribue à l'amélioration des rendements dans le traitement du dispositif en exécutant un traitement à meulage de surface, d'une variété de traitements sur une plaquette à semi-conducteurs découpée en tranche. Ensuite, application d'un traitement de poli optique d'une partie à arondissement des bords, d'une variété de traitements destiné au poli optique avec faible déformation. Finalement, l'invention met en oeuvre un traitement qui polit avec poli optique un côté principal requis d'une plaquette à bords arrondis.

Claims (6)

  1. Procédé de fabrication de plaquettes de semi-conducteurs dans lequel une surface requise de la plaquette est finie avec un fini miroir sans étape d'attaque chimique, comprenant, dans l'ordre indiqué :
    une opération de découpe qui découpe la plaquette dans un lingot de cristal unique ;
    une opération de meulage qui meule simultanément les deux faces de la plaquette découpée ;
    une opération de chanfreinage qui meule avec une faible déformation une partie périphérique de la plaquette dont les deux faces ont été meulées simultanément ;
    une opération de polissage primaire des deux faces qui réalise un polissage primaire des deux faces de la plaquette chanfreinée ;
    une opération de polissage de la partie chanfreinée qui réalise un polissage de finition de la partie chanfreinée de la plaquette ; et
    une opération de polissage de finition d'une face qui réalise un polissage de finition d'une face de la plaquette.
  2. Procédé selon la revendication 1, comprenant en outre l'étape de :
    meulage de finition d'une face ou des deux de la plaquette avec une précision élevée et une faible déformation entre l'étape de meulage simultané des deux faces de la plaquette et l'étape de chanfreinage de la partie de bord de la plaquette meulée.
  3. Procédé selon la revendication 1, comprenant en outre l'étape de :
    meulage de finition d'une face ou des deux de la plaquette avec une précision élevée et une faible déformation entre l'étape de chanfreinage de la partie de bord de la plaquette meulée et l'étape de polissage primaire des deux faces.
  4. Procédé selon la revendication 1, comprenant :
    une opération de meulage de finition qui réalise un meulage de finition avec une précision élevée et une faible déformation sur une face ou les deux faces de la plaquette après le processus de chanfreinage, et un second processus de chanfreinage qui meule une partie chanfreinée de la plaquette avec une faible déformation après le processus de polissage primaire des deux faces.
  5. Procédé selon la revendication 2 ou 3, dans lequel, après l'exécution du meulage de finition à faible déformation d'une surface de la plaquette, la couche déformée par le processus sur toute la surface de la plaquette est de 2-3 µm.
  6. Procédé selon la revendication 1, dans lequel le meulage simultané des deux faces de la plaquette découpée est poursuivi jusqu'à ce que les ondulations de la plaquette et une couche déformée par le processus produite par la découpe soient éliminées.
EP99970208A 1998-10-01 1999-09-29 Procede de fabrication de plaquettes a semiconducteurs Expired - Lifetime EP1145296B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP27966798 1998-10-01
JP10279667A JP2000114216A (ja) 1998-10-01 1998-10-01 半導体ウェーハの製造方法
PCT/JP1999/005311 WO2000021122A1 (fr) 1998-10-01 1999-09-29 Procede de fabrication de plaquettes a semiconducteurs

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EP1145296A1 EP1145296A1 (fr) 2001-10-17
EP1145296B1 true EP1145296B1 (fr) 2008-10-29

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US (1) US6465328B1 (fr)
EP (1) EP1145296B1 (fr)
JP (1) JP2000114216A (fr)
DE (1) DE69939842D1 (fr)
MY (1) MY123286A (fr)
WO (1) WO2000021122A1 (fr)

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DE69939842D1 (de) 2008-12-11
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JP2000114216A (ja) 2000-04-21
WO2000021122A1 (fr) 2000-04-13
EP1145296A1 (fr) 2001-10-17

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