WO2000047369A1 - Procede de polissage de plaquettes semi-conductrices - Google Patents

Procede de polissage de plaquettes semi-conductrices Download PDF

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Publication number
WO2000047369A1
WO2000047369A1 PCT/US2000/002636 US0002636W WO0047369A1 WO 2000047369 A1 WO2000047369 A1 WO 2000047369A1 US 0002636 W US0002636 W US 0002636W WO 0047369 A1 WO0047369 A1 WO 0047369A1
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WO
WIPO (PCT)
Prior art keywords
wafer
polishing
back surfaces
rough
finish
Prior art date
Application number
PCT/US2000/002636
Other languages
English (en)
Inventor
Jonas Bankaitis
Tamra K. Holtkamp
Original Assignee
Memc Electronic Materials, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Memc Electronic Materials, Inc. filed Critical Memc Electronic Materials, Inc.
Publication of WO2000047369A1 publication Critical patent/WO2000047369A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02024—Mirror polishing
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
    • B24B37/08—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/27—Work carriers
    • B24B37/28—Work carriers for double side lapping of plane surfaces

Definitions

  • the present invention relates generally to methods of processing semiconductor wafers prepared from a monocrystallme silicon ingot, and more particularly to a method of polishing such semiconductor wafers.
  • Semiconductor wafers are generally prepared from a monocrystallme ingot, such as a silicon ingot, which is trimmed and ground to have one or more flats for proper orientation of the wafer in subsequent procedures.
  • the ingot is then sliced into individual wafers which are each subjected to a number of wafer shaping or processing operations to reduce the thickness of the wafer, remove damage caused by the slicing operation, and to create a highly reflective surface.
  • each wafer is first rounded, such as by an edge grinding operation, to reduce the risk of wafer damage during further processing.
  • a substantial amount of material is removed from the front and back surface of each wafer to remove surface damage induced by the slicing operation and to make the opposing front and back surfaces flat and parallel.
  • This stock removal of material is accomplished by subjecting the front and back surfaces of the wafers to a conventional lapping operation (which uses a lapping slurry including abrasive particles), or a conventional grinding operation (which uses a disc with abrasive particles embedded therein), or even a combination of both lapping and grinding operations.
  • the wafers are then etched by fully immersing each wafer in a chemical etchant to further reduce the thickness of the wafer and remove mechanical damage produced by the lapping and/or grinding operation.
  • At least one surface of each wafer is polished with a colloidal silica slurry and a chemical etchant to remove damage induced by the etching operation and produce a highly reflective, damage-free surface.
  • the damage-free surface is desirable for printing circuits onto the wafer by, for example, an electron beam-lithographic or photolithographic process.
  • the amount of damage present on the surface of the wafer directly impacts device line width capability, process latitude, yield and throughput.
  • the wafers are then cleaned and inspected prior to being packaged and delivered to customers for subsequent dicing of the wafer into semiconductor chips.
  • the flatness of the wafer is a critical parameter to customers since wafer flatness has a direct impact on the subsequent use and quality of semiconductor chips diced from the wafer.
  • the flatness may be determined by a number of measuring methods. For example, “Taper” is a measurement of the lack of parallelism between the unpolished back surface and a selected focal plane of the wafer. "TIR,” or Total Indicated Reading, is the difference between the highest point above the selected focal plane and the lowest point below the focal plane, and is always a positive number. "FPD-3pt,” or Three point Focal Plane Deviation, is the highest point above, or the lowest point below, a chosen 3 point focal plane, and may be positive or negative.
  • TIR and FPD are as defined above (for TIR and FPD-3pt) but measured over a particular small area of the wafer, such as 1mm x 1mm.
  • TTV Total Thickness Variation, is the difference between the highest and lowest elevation of the polished front surface of the wafer.
  • the conventional method of processing has a number of disadvantages. Processing steps which reduce surface damage tend to adversely affect the flatness of the wafer. For example, immersion of the entire wafer in the chemical etchant deteriorates the flatness produced by the lapping or grinding operation. In addition, polishing the wafer in a standard single-side polishing apparatus tends to further deteriorate the wafer flatness, with the flatness deterioration generally increasing as the amount of silicon removal increases. More particularly, the standard single-side polishing apparatus has a tendency to taper (e.g., reduce the thickness of) the surfaces of the wafer towards the peripheral edge of the wafer, thereby resulting in a wafer having slightly convex front and back surfaces.
  • taper e.g., reduce the thickness of
  • the front side of the wafer is then subjected to a finish polishing operation using a finish polishing slurry such that the front surface of the wafer becomes highly reflective.
  • the concavity of the front and back surfaces is substantially reduced as a result of finish polishing.
  • Fig. 1 is a flow diagram showing a method of processing a semiconductor wafer
  • Fig. 2 is a fragmentary top view of a portion of a double-side polishing machine
  • Fig. 3 is a table showing the results of an experiment in which semiconductor wafers were polished according to a method of the present invention for polishing a semiconductor;
  • Fig. 4 is a plot of Focal Plane Deviation-3pt values recorded in the table of Fig. 3; and Fig. 5 is a plot of Total Thickness Variation values recorded in the table of Fig.
  • Corresponding reference characters indicate corresponding parts throughout the several views of the drawings.
  • the several objects of the invention can be obtained by subjecting semiconductor wafers to a three-step polishing operation in which the wafers are first rough polished on a double-side polishing machine to form a concave, or dish-shaped, surface on both the front and back sides of each wafer, and subjecting the rough polished wafers to an intermediate polishing operation and finish polishing operation on a single-side polishing machine. While the method of the present invention is illustrated and described herein with reference to semiconductor wafers constructed of silicon, it is understood that the method is applicable to processed wafers, discs or the like made of other materials without departing from the scope of this invention.
  • Fig. 1 illustrates a method of processing a semiconductor wafer in which the wafer is initially sliced from a monocrystallme ingot, such as by using a conventional inner diameter saw or conventional wire saw, to have a predetermined initial thickness.
  • the sliced wafer is generally disc-shaped and has a peripheral edge and opposing front and back surfaces.
  • the initial thickness of each wafer is substantially greater than the desired end thickness to allow subsequent processing operations to reduce the thickness of the wafer without the risk of damaging or fracturing the wafer.
  • the wafer may be subjected to ultrasonic cleaning to remove particulate matter deposited on the wafer from the slicing operation.
  • the peripheral edge of the wafer is profiled (e.g., rounded) by a conventional edge grinder to reduce the risk of damage to the wafer during subsequent processing.
  • the wafer is placed in a conventional lapping machine for stock removal of material from the front and back sides of the wafer using a lapping slurry containing abrasive particles.
  • the lapping operation is performed to substantially reduce the thickness of the wafer, thereby removing damage caused by the wafer slicing operation, and to flatten and parallel its front and back surfaces.
  • a conventional grinding operation in which the front and back sides of the wafer are ground using an abrading disc having abrasive particles embedded therein, may be performed in place of or in conjunction with the lapping operation.
  • the wafer is then fully immersed in a chemical etchant, such as a conventional caustic etch solution comprising 45% (by weight) KOH, thereby removing additional material from the front and back sides of the wafer to reduce surface damage caused by lapping and/or grinding.
  • a chemical etchant such as a conventional caustic etch solution comprising 45% (by weight) KOH
  • a chemical etchant such as a conventional caustic etch solution comprising 45% (by weight) KOH
  • the polishing method of the present invention comprises a rough polishing operation in which the wafer is placed in a conventional double-side polishing machine (a fragmented portion of which is shown in Fig. 2) for concurrent polishing of the front and back surfaces of the wafer.
  • a conventional double-side polishing machine is manufactured by Peter Wolters of Rendsburg, Germany under the model designation AC 1400. Construction and operation of a conventional double-side polishing machine for polishing semiconductor wafers is well known to those skilled in the art and will not be described herein except to the extent necessary to describe the method of the present invention. With reference to Fig.
  • the conventional double-side polishing machine has a lower platen (not shown) rotatable about a central rotation axis X by a suitable drive motor (not shown).
  • a polishing surface defined by a polishing pad 21 is secured on the platen for conjoint rotation therewith.
  • a wafer carrier 23 capable of holding one or more wafers is seated on the polishing pad for rotation relative to the lower platen and polishing pad about a central rotation axis Y of the carrier and for orbital movement about the central rotation axis X of the platen.
  • the wafers are held in the carrier with the front surface of the wafer engaging the polishing pad covering the lower platen.
  • the peripheral edge of the wafer carrier is notched for interengagement with an inner drive ring and an outer drive ring.
  • the inner drive ring is disposed adjacent an inner peripheral edge of the platen and is rotatable about the central rotation axis X of the platen by another drive motor (not shown). Pins extend upward from the inner drive ring for driving engagement with the notched peripheral edge of the carrier.
  • the outer drive ring is positioned adjacent the outer peripheral edge of the platen and is also rotatable about the central rotation axis of the platen. Pins extend upward from the outer drive ring for driving engagement with the notched peripheral edge of the wafer carrier. Rotation of the inner and outer drive rings causes the carrier to rotate about its own central rotation axis and, depending on the direction of rotation of the inner and outer drive rings and the speed differential between the rings, to orbit about the central rotation axis of the lower platen.
  • An upper platen (not shown) is mounted on a vertically movable spindle (not shown) above the wafer carrier so that a polishing pad (not shown but similar to polishing pad 21) secured to the upper platen is in opposing relationship with the polishing pad 21 of the lower platen.
  • the upper platen and its associated polishing pad are conjointly rotatable relative to the lower platen and the wafer carrier about the rotation axis of the spindle which, in a conventional double-side polishing machine, is co-axial with the central rotation axis X of the lower platen.
  • the spindle is capable of being moved up and down along the spindle rotation axis for moving the upper platen and polishing pad into polishing engagement with the back surface of the wafers held by the wafer carrier to sandwich the wafers between the upper and lower polishing pads.
  • the force exerted against the wafers by the polishing pads is generally a function of the downward force exerted by the vertically movable upper platen and polishing pad.
  • a conventional polishing slurry containing abrasive particles and a chemical etchant, such as KOH solution is applied between the polishing pads and the wafers.
  • polishing slurry is manufactured by DuPont of Wilmington, Delaware under the tradename Syton HT50.
  • the polishing pads work the slurry against the surfaces of the wafers held by the wafer carrier to concurrently and uniformly remove material from both sides of the wafers, leaving rough polished front and back surfaces.
  • the double-side polishing operation may remove between 24-30 microns (12-15 microns per side) of thickness from the wafer.
  • the wafer now having rough polished front and back surfaces, is preferably subjected to an intermediate polishing operation in which the front surface of the wafer, but not the back surface, is polished to further smooth the front surface.
  • the wafer is placed in a conventional single-side polishing machine (not shown).
  • a conventional single-side polishing machine is manufactured by R. Howard Strasbaugh, Inc. of San Luis Obispo, California under the model designation 6DZ.
  • the wafer is mounted on a ceramic block in a conventional manner by applying a wax layer to the surface of the block and adhering the wafer to the block, leaving the front surface of the wafer exposed.
  • the block is placed on a turntable of the machine with the front surface of the wafer contacting the polishing surface of a polishing pad.
  • a polisher head is mounted on the machine and is capable of vertical movement along an axis extending through the ceramic block. While the turntable rotates, the polisher head is moved against the ceramic block to urge the block toward the turntable, thereby pressing the front surface of the wafer into polishing engagement with the polishing surface of the polishing pad.
  • the polishing pad works the slurry against the surface of the wafer to remove material from the front surface of the wafer, resulting in a surface of improved smoothness.
  • the intermediate polishing operation preferably removes less than about 1 micron of material from the front side of the wafer.
  • the wafer is subjected to a finish polishing operation in which the front surface of the wafer is finish polished to remove scratches induced by wafer handling during the prior processing operations and to produce a highly reflective, damage-free front surface of the wafer.
  • the wafer is preferably finish polished in the same single- side polishing machine used to intermediate polish the wafer as described above. However, it is understood that a separate single-side polishing machine may be used for the finish polishing operation without departing from the scope of this invention.
  • a finish polishing slurry having an ammonia base and a reduced concentration of colloidal silica is injected between the polishing pad and the wafer.
  • a particularly preferred finish polishing slurry is manufactured by Rodel of Newark, Delaware under the tradename Advansil 1595.
  • the polishing pad works the finish polishing slurry against the front surface of the wafer to remove any remaining scratches and haze so that the front surface of the wafer is generally highly-reflective and damage free.
  • Fig. 1 The method of the present invention (Fig. 1) for polishing semiconductor wafers intentionally shapes the wafer during double-side rough polishing to take advantage of the subsequent shaping that occurs during intermediate and finish polishing operations, thus producing a finished wafer with improved flatness characteristics. More particularly, as shown in Fig. 1 and described in further detail below, the wafers are subjected to a double-side rough polishing operation in which the wafers are rough polished in a manner that produces rough polished wafers having generally symmetric, concave (e.g., dish-shaped) front and back surfaces.
  • a double-side rough polishing operation in which the wafers are rough polished in a manner that produces rough polished wafers having generally symmetric, concave (e.g., dish-shaped) front and back surfaces.
  • the first group of wafers (referred to in the experiment as Block 1 wafers) were double- side rough polished to have convex (e.g., dome-shaped) front and back surfaces with an FPD-3pt of about 0.50 microns.
  • the second group of wafers (referred to in the experiment as Block 2 wafers) were double-side rough polished to have concave (e.g., dish-shaped) front and back surfaces with an FPD-3pt of about -0.50 microns.
  • the wafers were then subjected to an intermediate polishing operation in which the wafers were polished in a single-side polishing machine according to the conventional intermediate polishing operation discussed above.
  • Table 1 sets forth the conditions under which the wafers were intermediate polished during the experiment. Polishing pressure, polishing time and etchant (e.g., KOH) flow rate were varied for each wafer processed. Following each intermediate polishing operation, the TTV value, maximum STIR and TTV degradation were measured and recorded as in Table I. TTV degradation was calculated as the increase (e.g. flatness deterioration) or decrease (e.g., flatness improvement) in TTV value of the wafer with respect to the TTV value of the wafer as measured prior to the intermediate polishing operation.
  • Polishing pressure, polishing time and etchant e.g., KOH
  • the Block 2 wafers typically had, a lower TTV value than the Block 1 wafers after intermediate polishing, irrespective of the variation in polishing parameters.
  • the positive wafer flatness characteristics achieved through double-side rough polishing of the wafers were best preserved where the wafers were shaped during double-side rough polishing to have concave front and back surfaces prior to the intermediate polishing operation.
  • the thickness of the wafer carrier can be used as a secondary or supplemental means for shaping the wafer to have concave front and back surfaces.
  • the polishing pads engage the wafer carrier to inhibit further material removal from the wafer.
  • the polishing pads are somewhat flexible, the polishing pads continue to remove material from the center of the wafer while being inhibited from removing wafer material radially outward from the wafer center toward the wafer carrier, thereby producing a concave shaped surface of the wafer.
  • the wafer carrier thickness is preferably about 2 microns greater than the desired end thickness of the wafer after rough polishing.
  • step 1 represents a conventional preparatory step in which the polishing pad is cleansed with deionized water and the flow of polishing slurry and etchant (e.g., KOH) is initiated.
  • Step 2 is a removal step during which the etchant aids in the removal of material from the front surface of the wafer to further reduce damage present on the front surface.
  • Step 3 is a smoothing step in which the front surface is polished without etchant to further smooth the front surface prior to finish polishing.
  • the wafer is then conventionally cleaned and coated with a protective coating to prevent further oxidation of the front surface of the wafer.
  • a protective coating is a solution containing a product sold by Union Carbide Corporation-Specialty Chemicals of Danbury, Connecticut under the tradename Polyox.
  • the finish polishing operation set forth in Table IN includes a conventional preparatory step (step 1) in which the polishing pads are cleansed with deionized water.
  • Steps 2-5 illustrate the polishing steps of the final polishing operation and steps 6-8 are conventional post-polishing steps during which the wafer is again cleaned and coated with a protective coating to prevent further oxidation of the front surface of the wafer.
  • 35 wafers each having a diameter of 200mm, were polished according to the method of the present invention.
  • the average wafer thickness of each wafer was measured prior to double-side rough polishing and the wafers were each subjected to the rough polishing operation described above.
  • the average wafer thickness after rough polishing was measured and recorded along with the average FPD-3pt, average TTV and average maximum STIR.
  • the negative FPD-3pt value measured for each of the wafers after the double-side rough polishing operation is indicative of the desired concave front and back surface contours of the wafer.
  • the relatively low TTV values indicate the positive flatness characteristics achieved by subjecting the wafers to double-side polishing.
  • the wafers were then intermediate and finish polished as described above with respect to Tables III and IV and again the average FPD-3pt, TTV and maximum STIR were measured for each wafer.
  • the TTV degradation of each wafer was calculated with respect to the TTV of the wafer prior to intermediate and finish polishing.
  • the FPD-3pt values measured after intermediate and finish polishing indicates that the wafer became more planar as desired.
  • the TTV values of the wafers were substantially decreased (i.e., flatness characteristics improved) as a result of intermediate and finish polishing as indicated in Fig. 5 and by the negative TTV degradation values recorded in Fig. 3.
  • the double-side rough polishing provides a wafer having good flatness characteristics. Shaping the wafer during rough polishing to have concave front and back surfaces takes advantage of the wafer shaping characteristics associated with subsequent intermediate and finish polishing operations.
  • shaping the wafer to have concave surfaces prior to subjecting the wafer to the intermediate and finish polishing operations preserves and in most cases improves the flatness characteristics of the wafers achieved by subjecting the wafers to double-side rough polishing.
  • the method of the present invention can be performed using conventional, already existing wafer processing machines.

Abstract

La présente invention concerne un procédé de polissage d'une plaquette semi-conductrice destiné à prévenir la dégradation de la planéité de la plaquette par le polissage, ledit procédé consistant à polir une première fois les surfaces avant et arrière de la plaquette à l'aide d'une pâte de polissage tout en régulant les paramètres de polissage de manière que les surfaces avant et arrière de la plaquette perdent de leur planéité pour devenir de manière générale concaves. La partie avant de la plaquette subit ensuite une opération de polissage final à l'aide d'une pâte de polissage final de façon que la surface avant de la plaquette devienne hautement réfléchissante. La concavité des surfaces avant et arrière est sensiblement atténuée par le polissage final.
PCT/US2000/002636 1999-02-12 2000-02-02 Procede de polissage de plaquettes semi-conductrices WO2000047369A1 (fr)

Applications Claiming Priority (2)

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US24894099A 1999-02-12 1999-02-12
US09/248,940 1999-02-12

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WO2000047369A1 true WO2000047369A1 (fr) 2000-08-17

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10210023A1 (de) * 2002-03-07 2003-05-28 Wacker Siltronic Halbleitermat Siliciumscheibe und Verfahren zu ihrer Herstellung
JP2008078660A (ja) * 2006-09-20 2008-04-03 Siltronic Ag 半導体ウェハを研磨する方法及びその方法に従って製作可能な研磨された半導体ウェハ
DE102009025243A1 (de) * 2009-06-17 2010-12-30 Siltronic Ag Verfahren zur Herstellung und Verfahren zur Bearbeitung einer Halbleiterscheibe
DE102010005904A1 (de) * 2010-01-27 2011-07-28 Siltronic AG, 81737 Verfahren zur Herstellung einer Halbleiterscheibe
DE102013204839A1 (de) 2013-03-19 2014-09-25 Siltronic Ag Verfahren zum Polieren einer Scheibe aus Halbleitermaterial
WO2021257254A1 (fr) * 2020-06-17 2021-12-23 Globalwafers Co., Ltd. Polissage de substrat semi-conducteur avec régulation de température de tampon de polissage

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008045534B4 (de) * 2008-09-03 2011-12-01 Siltronic Ag Verfahren zum Polieren einer Halbleiterscheibe

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Publication number Priority date Publication date Assignee Title
EP0588055A2 (fr) * 1992-09-18 1994-03-23 Mitsubishi Materials Corporation Procédé pour la fabrication de disques de semiconducteur
US5422316A (en) * 1994-03-18 1995-06-06 Memc Electronic Materials, Inc. Semiconductor wafer polisher and method
US5441442A (en) * 1992-06-05 1995-08-15 U.S. Philips Corporation Method of manufacturing a plate having a plane main surface, method of manufacturing a plate having parallel main surfaces, and device suitable for implementing said methods

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5441442A (en) * 1992-06-05 1995-08-15 U.S. Philips Corporation Method of manufacturing a plate having a plane main surface, method of manufacturing a plate having parallel main surfaces, and device suitable for implementing said methods
EP0588055A2 (fr) * 1992-09-18 1994-03-23 Mitsubishi Materials Corporation Procédé pour la fabrication de disques de semiconducteur
US5422316A (en) * 1994-03-18 1995-06-06 Memc Electronic Materials, Inc. Semiconductor wafer polisher and method

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10210023A1 (de) * 2002-03-07 2003-05-28 Wacker Siltronic Halbleitermat Siliciumscheibe und Verfahren zu ihrer Herstellung
DE102006044367B4 (de) * 2006-09-20 2011-07-14 Siltronic AG, 81737 Verfahren zum Polieren einer Halbleiterscheibe und eine nach dem Verfahren herstellbare polierte Halbleiterscheibe
JP2008078660A (ja) * 2006-09-20 2008-04-03 Siltronic Ag 半導体ウェハを研磨する方法及びその方法に従って製作可能な研磨された半導体ウェハ
DE102006044367A1 (de) * 2006-09-20 2008-04-03 Siltronic Ag Verfahren zum Polieren einer Halbleiterscheibe und eine nach dem Verfahren herstellbare polierte Halbleiterscheibe
US8398878B2 (en) 2009-06-17 2013-03-19 Siltronic Ag Methods for producing and processing semiconductor wafers
DE102009025243B4 (de) * 2009-06-17 2011-11-17 Siltronic Ag Verfahren zur Herstellung und Verfahren zur Bearbeitung einer Halbleiterscheibe aus Silicium
DE102009025243A1 (de) * 2009-06-17 2010-12-30 Siltronic Ag Verfahren zur Herstellung und Verfahren zur Bearbeitung einer Halbleiterscheibe
DE102010005904A1 (de) * 2010-01-27 2011-07-28 Siltronic AG, 81737 Verfahren zur Herstellung einer Halbleiterscheibe
JP2011155265A (ja) * 2010-01-27 2011-08-11 Siltronic Ag 半導体ウェハの製造方法
DE102010005904B4 (de) * 2010-01-27 2012-11-22 Siltronic Ag Verfahren zur Herstellung einer Halbleiterscheibe
US8529315B2 (en) 2010-01-27 2013-09-10 Siltronic Ag Method for producing a semiconductor wafer
DE102013204839A1 (de) 2013-03-19 2014-09-25 Siltronic Ag Verfahren zum Polieren einer Scheibe aus Halbleitermaterial
US9193026B2 (en) 2013-03-19 2015-11-24 Siltronic Ag Method for polishing a semiconductor material wafer
WO2021257254A1 (fr) * 2020-06-17 2021-12-23 Globalwafers Co., Ltd. Polissage de substrat semi-conducteur avec régulation de température de tampon de polissage

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