EP1142457A1 - Procede de fabrication d'une carte de circuits imprimes multicouche - Google Patents

Procede de fabrication d'une carte de circuits imprimes multicouche

Info

Publication number
EP1142457A1
EP1142457A1 EP99959169A EP99959169A EP1142457A1 EP 1142457 A1 EP1142457 A1 EP 1142457A1 EP 99959169 A EP99959169 A EP 99959169A EP 99959169 A EP99959169 A EP 99959169A EP 1142457 A1 EP1142457 A1 EP 1142457A1
Authority
EP
European Patent Office
Prior art keywords
layers
layer
conductor
laminate
plated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99959169A
Other languages
German (de)
English (en)
Inventor
Thomas Widmer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PPC Electronic AG
Original Assignee
PPC Electronic AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PPC Electronic AG filed Critical PPC Electronic AG
Publication of EP1142457A1 publication Critical patent/EP1142457A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0038—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material combined with laser drilling through a metal layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0207—Partly drilling through substrate until a controlled depth, e.g. with end-point detection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0353—Making conductive layer thin, e.g. by etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/107—Using laser light
    • H05K2203/108—Using a plurality of lasers or laser light with a plurality of wavelengths
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern

Definitions

  • the present invention relates to the field of printed circuit board technology. It relates to a method for producing a multilayer printed circuit board which comprises a plurality of conductor layers which are arranged one above the other and are separated from one another by insulating layers, the conductor layers being conductively connected to one another by via openings arranged one above the other in an axis in the respective insulating layers.
  • Such a method is e.g. known from US-A-5,662,987 or US-A-4,258,468.
  • the object is achieved by the entirety of the features of claim 1.
  • the essence of the invention is to open the plated-through holes of a laminate layer by means of a laser beam through the respective conductor layer and the insulating layer underneath. As a result, very fine openings with a diameter of less than 100 ⁇ m can be produced quickly, cleanly and precisely one above the other, which ensure reliable through-plating during the subsequent metallization.
  • a first preferred embodiment of the method according to the invention is characterized in that the laminate core comprises a third insulating layer provided on both sides with first conductor layers, and in that first and second laminate layers are applied to both sides of the laminate core and in each case through-contacted.
  • the number of conductor layers and levels can be significantly increased while maintaining a laminate core.
  • a further increase in the number of conductor levels is of course possible if more than two laminate layers are applied one above the other on one or both sides.
  • a second preferred embodiment of the method according to the invention is characterized in that the through-openings are introduced into the respective insulating layers by means of the laser beams in two steps, in a first step with a first laser beam of a first power, the conductor layer lying over the insulating layer and a Part of the underlying insulating layer of the respective laminate layer is removed, and in one second step with a second laser beam of a second, compared to the first, reduced power, the remaining part of the insulating layer is removed.
  • a relatively high beam power or intensity of the laser beam is required for the removal of the metallic (Cu) conductor layer in the area of the via openings to be produced.
  • the ratio of the first power to the reduced second power is preferably about 3: 1.
  • a further preferred embodiment of the method according to the invention is characterized in that the conductor layers applied with the laminate layers are each reduced in thickness before the through-hole openings are introduced, and are reinforced again after the through-hole openings have been introduced by the metallizations used for the through-hole connection.
  • the reduction in thickness of the conductor layers enables a total reduction in the laser beam power used or a higher processing power with the same laser beam intensity. As a result, greater precision in machining and thus an overall reduced diameter of the openings can be achieved.
  • the conductor layers of the laminate layers preferably initially have a thickness of 10-20 ⁇ m, in particular 12 or 18 ⁇ m, and they are removed down to a thickness of approximately 6-7 ⁇ m for the laser drilling of the plated-through holes.
  • the plated-through holes also have a diameter of 50-150 ⁇ m.
  • Cu films are preferably used as the laminate layers as conductor layers with an epoxy resin layer as the insulating layer, the laminate layers each having an initial thickness of approximately 70-100 ⁇ m.
  • FIGS. 1-14 The exemplary embodiment for the method according to the invention shown in FIGS. 1-14 is based on a flat laminate core 10 according to FIG. 1, which comprises a central insulating layer 11, each provided with a conductor layer 12 and 13 on the top and bottom is.
  • the thicknesses of the individual layers are not drawn to scale in FIG. 1 for reasons of better visibility.
  • the thickness of the laminate core is, for example, 1.2 mm.
  • the insulating layer 11 is made of a conventional epoxy resin.
  • the conductor layers 12 and 13 are usually made of Cu and have a thickness which is adapted to the respective requirements and e.g. is a few 1/10 mm.
  • the two conductor layers 12 and 13 are structured according to FIG. 2 by means of conventional lithographic and etching methods in accordance with an existing circuit board layout, by structures 14 and 15 in the Conductor layers 12, 13 are etched free.
  • two identical first laminate layers 20 and 30 are then applied to the laminate core 10 from both sides by lamination or pressing.
  • Each of the laminate layers 20, 30 consists of a conductor layer 18 or 19 in the form of a copper foil, which is provided on the underside with an insulating layer 16 or 17 made of an epoxy resin.
  • the thickness of the laminate layers 20, 30 is preferably between 70 and 100 ⁇ m, and the initial thickness d1 of the conductor layers 18, 19 is preferably 12 or 18 ⁇ m.
  • the first via openings are then introduced into the laminate structure according to FIG. 3.
  • the thickness of the conductor layers 18, 19 reduced from the original value d1 (12 or 18 ⁇ m) to a value d2 of approximately 6-7 ⁇ m.
  • a laminate structure according to FIG. 4 then results.
  • FIG. 5 in a laser processing center with a laser beam 39 (indicated by the arrow bundle in FIG.
  • Through openings 21 and 22, respectively, are introduced by locally removing (evaporating) both the (reduced-thickness) conductor layer 18 and 19 and part of the underlying insulation layer 16 and 17 to a certain depth.
  • the plated-through holes 21, 22 are preferably produced in succession in the same laser processing center with the same laser beam 39.
  • the plated-through holes 21, 22 are preferably produced with a diameter D1 of 50-150 ⁇ m.
  • the laser beam 39 has only a diameter of approximately 25 ⁇ m and is moved across the laminate structure on a predetermined travel line across the laminate structure in order to lift the larger through-hole 21, 22.
  • the laser operates in a first mode with increased beam power or beam intensity.
  • the laser is operated in a second mode with a beam power attenuated to approximately 1/3 (indicated in FIG. 6 by a smaller number of arrows in the laser beam 23).
  • the insulating layers 16, 17 can thus be cleared out precisely and completely within the plated-through holes 21, 22 without the underlying conductor layers 12, 13 being damaged.
  • next step by applying a metallization 24 or 25, conductive connections are made between the areas of the conductor layers 12, 13 exposed in the via openings 21, 22 and the areas of the conductor layers 18, 19 bordering the via openings 21, 22. Since the metallization takes place over the entire area, the conductor layers 18, 19, which were previously reduced in thickness, are again reinforced overall by the metallization and can subsequently be structured in the usual way, i.e. can be provided with structures 26, 27 (FIG. 8).
  • laminate structure according to FIG. 8 is now ready for the lamination (pressing with) of the next following laminate layers 40 and 50 (FIG. 9), which in turn each consist of a conductor layer 31 or 32 (Cu foil) with an insulating layer 28, 29 underneath (made of epoxy resin) and the laminate layers 20, 30 same.
  • laminate layers 40, 50 the same steps for producing the plated-through holes are carried out according to FIGS. 10-14 as those shown in FIGS. 4-8 for the laminate layers 20, 30 and have already been explained. This includes reducing the thickness of the conductor layers 31, 32 (step from FIG. 9 to FIG. 10), clearing the conductor layers 31, 32 in the plated-through holes 33, 34 with a laser beam 35 of increased power (FIG.
  • the plated-through holes 33, 34 are made directly through the previously created plated-through holes 21, 22 by suitable adjustment of the laminate structure in the laser processing center and corresponding control of the laser beam. Due to the 2-stage laser processing, an island 36, 37 made of insulating material remains within the lower plated-through holes 21, 22 (FIG. 12), which is subsequently covered by the metallization 41 and 42, respectively. In this way it is possible to limit the metallization to only the depth of one laminate layer.
  • the method according to the invention makes it easy and safe to produce a multilayer plated-through circuit board which is characterized by space-saving and precisely arranged plated-through holes.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Cette invention concerne un procédé de fabrication d'une carte de circuits imprimés multicouche. Selon ce procédé de fabrication, des couches de matériau stratifié (20, 30, 40 50), formé d'une couche de matériau conducteur (24, 25, 31, 32) et d'une couche de matériau isolant (16, 17; 28, 29), sont pressées autour d'un coeur (10). A l'aide d'un faisceau laser, on réalise des trous (33, 34) entre les couches conductrices (25, 31 ou 24, 32), à travers les couches de matériau stratifié (40, 50). Ces trous sont ensuite métallisés.
EP99959169A 1999-01-05 1999-12-24 Procede de fabrication d'une carte de circuits imprimes multicouche Withdrawn EP1142457A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CH799 1999-01-05
CH9999 1999-01-05
PCT/CH1999/000625 WO2000041447A1 (fr) 1999-01-05 1999-12-24 Procede de fabrication d'une carte de circuits imprimes multicouche

Publications (1)

Publication Number Publication Date
EP1142457A1 true EP1142457A1 (fr) 2001-10-10

Family

ID=4177302

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99959169A Withdrawn EP1142457A1 (fr) 1999-01-05 1999-12-24 Procede de fabrication d'une carte de circuits imprimes multicouche

Country Status (3)

Country Link
EP (1) EP1142457A1 (fr)
AU (1) AU1646500A (fr)
WO (1) WO2000041447A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030188889A1 (en) * 2002-04-09 2003-10-09 Ppc Electronic Ag Printed circuit board and method for producing it
US11999014B2 (en) * 2019-11-22 2024-06-04 Medtronic, Inc. Laser cutting system

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1220370A (en) * 1968-08-13 1971-01-27 Litton Industries Inc Electrical circuit boards
US4258468A (en) * 1978-12-14 1981-03-31 Western Electric Company, Inc. Forming vias through multilayer circuit boards
DE68923904T2 (de) * 1988-05-20 1996-03-14 Mitsubishi Gas Chemical Co Verfahren zur Herstellung eines mit einer dünnen Kupferfolie kaschierten Substrats für Schaltungsplatten.
US5063280A (en) * 1989-07-24 1991-11-05 Canon Kabushiki Kaisha Method and apparatus for forming holes into printed circuit board
JP3290041B2 (ja) * 1995-02-17 2002-06-10 インターナショナル・ビジネス・マシーンズ・コーポレーション 多層プリント基板、多層プリント基板の製造方法
JP2778569B2 (ja) * 1996-01-22 1998-07-23 日立エーアイシー株式会社 多層印刷配線板およびその製造方法
JP2720865B2 (ja) * 1996-01-22 1998-03-04 日立エーアイシー株式会社 多層印刷配線板およびその製造方法
KR100222752B1 (ko) * 1996-06-27 1999-10-01 이형도 레이저를 이용한 다층 인쇄회로기판의 제조방법
JPH10224040A (ja) * 1997-01-31 1998-08-21 Nippon Carbide Ind Co Inc 多層配線板の製造方法
JPH10335829A (ja) * 1997-05-28 1998-12-18 Nippon Carbide Ind Co Inc 多層配線板およびその製造方法
JPH10335828A (ja) * 1997-05-28 1998-12-18 Nippon Carbide Ind Co Inc 多層配線板およびその製造方法
JPH10335824A (ja) * 1997-05-28 1998-12-18 Nippon Carbide Ind Co Inc 多層配線板およびその製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0041447A1 *

Also Published As

Publication number Publication date
WO2000041447A1 (fr) 2000-07-13
AU1646500A (en) 2000-07-24

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