EP1115895B1 - Procede de traitement, par nitruration, d'un substrat de silicium pour la formation d'une couche isolante mince - Google Patents
Procede de traitement, par nitruration, d'un substrat de silicium pour la formation d'une couche isolante mince Download PDFInfo
- Publication number
- EP1115895B1 EP1115895B1 EP99943005A EP99943005A EP1115895B1 EP 1115895 B1 EP1115895 B1 EP 1115895B1 EP 99943005 A EP99943005 A EP 99943005A EP 99943005 A EP99943005 A EP 99943005A EP 1115895 B1 EP1115895 B1 EP 1115895B1
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- EP
- European Patent Office
- Prior art keywords
- layer
- substrate
- silicon
- insulating material
- electric insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
- C23C28/04—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings of inorganic non-metallic material
- C23C28/044—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings of inorganic non-metallic material coatings specially adapted for cutting tools or wear applications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C8/00—Solid state diffusion of only non-metal elements into metallic material surfaces; Chemical surface treatment of metallic material by reaction of the surface with a reactive gas, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals
- C23C8/06—Solid state diffusion of only non-metal elements into metallic material surfaces; Chemical surface treatment of metallic material by reaction of the surface with a reactive gas, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals using gases
- C23C8/28—Solid state diffusion of only non-metal elements into metallic material surfaces; Chemical surface treatment of metallic material by reaction of the surface with a reactive gas, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals using gases more than one element being applied in one step
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24926—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer
Definitions
- the present invention relates to a method of treatment of a silicon substrate for the formation on at least one of its faces, of a layer of an electrical insulating material such as, for example example, a layer of silicon nitride.
- the invention finds applications in the realization of electronic devices with components comprising an electrical insulating layer thin and especially for the production of memories of DRAM (dynamic direct access memory) or EPROM type (programmable / erasable read-only memory).
- DRAM dynamic direct access memory
- EPROM type programmable / erasable read-only memory
- insulated gate transistors such as transistors MOS or other components such as capabilities.
- the grid layer for the components made on a silicon substrate, is usually a layer of silicon oxide.
- Diffusion problems of doping impurities can be solved, at least in part, by incorporating into the gate oxide components a appropriate dose of nitrogen, including using a nitriding treatment.
- the layer oxide can be combined or possibly replaced by a layer of silicon nitride.
- Document [1] shows in particular that it is not possible to form a nitride layer homogeneous and continuous with a thickness of less than 5 nm on a native oxide layer on the surface of a substrate.
- Document [2] proposes to solve the problems of continuity or inhomogeneity of the thin nitride layers ( ⁇ 3 nm) by subjecting them to rapid annealing under an NH 3 atmosphere at temperatures of the order of 950 ° C.
- a rapid annealing under an NH 3 atmosphere at temperatures of the order of 950 ° C.
- annealing because of its high temperature, is capable of altering electronic components previously formed in the substrate.
- Documents [3] and [4] describe techniques according to which a native oxide layer, initially present on the surface of a substrate of silicon, is removed before the formation of a layer nitride, by chemical vapor deposition, on the exposed silicon surface. Deoxidation of substrate can take place by annealing under hydrogen or chemically with hydrofluoric acid.
- document (5) proposes to form on the substrate a layer of silicon oxynitride, prior to the layer of silicon nitride.
- the oxynitride layer is formed under an atmosphere of NO.
- the silicon nitride layer is formed from SiH 4 and NH 3 gases in a single-plate type reactor.
- the enrichment of the silane treatment gases (SiH 4 ) promotes the nucleation of the silicon nitride but alters its stoichiometric quality.
- the use of a single-plate reactor is also not very compatible with an industrial production of components, at low production costs.
- the document (7) whose complete reference is also specified at the end of the description, further describes a method of forming a layer of insulating material. This process implements several heat treatments at a temperature above 900 ° C.
- Document (8) describes a process for forming a dielectric layer at a temperature comprised preferably between 700 ° C and 850 ° C.
- the object of the invention is to propose a method for preparing a substrate allowing the formation of a thin layer of electrical insulation having no not the difficulties mentioned above.
- One goal is in particular to propose such a process for forming a nitride layer fine, continuous and homogeneous, on a substrate of silicon.
- An object of the invention is also to propose a process using thermal budgets and reduced temperatures.
- NO-based atmosphere means a atmosphere of pure NO or NO diluted with an inert gas such as nitrogen or argon.
- Heat treatment makes it possible to form surface of the deoxidized part of the substrate a layer very fine silicon oxynitride whose thickness may be less than a nanometer. This layer allows then form a thin, homogeneous insulating layer and carry on.
- the oxynitride layer makes it possible to avoid the formation on the substrate of parasitic deposits of metal oxides such as Ta 2 O 5 which may appear during oxidative treatments.
- the heat treatment of the process is implemented works at temperatures below 750 ° C, for example at a temperature of the order of 550 ° C.
- the process can thus be applied to substrates with relatively electronic components heat sensitive, pre-formed.
- the heat treatment can be implemented with sufficient duration to obtain an oxynitride layer having a thickness between 0.5 and 1.5 nm.
- the heat treatment can be carried out at a temperature of the order of 550 ° C., a pressure of the order of 10 3 Pa (10 mBar), for a duration of the order of 30 seconds for obtain a 0.7 nm layer of oxynitride.
- the silicon substrate used may have undergone prior treatments in order to form components or parts of electronic components.
- the layer of electrical insulating material formed on the substrate can be a layer of silicon nitride (Si 3 N 4 ) or a layer of Ta 2 O 5 , chosen for their high permittivity.
- this can preferably be formed by a process of the LPCVD type (chemical vapor deposition at low pressure) in the presence of a dichlorisilane-based atmosphere ( SiH 2 Cl 2 ) and / or ammonia NH 3 .
- the deposition is carried out at a temperature less than or equal to 750 ° C., for example, 700 ° C.
- the invention also relates to a substrate, obtainable according to the method described above and comprising, in order, a layer of silicon with at least one area devoid of native oxide, a layer of silicon oxynitride having a thickness between 0.5 and 1.5 nm in contact with said range, and a layer of an electrical insulating material, having a thickness between 2 and 5 nm, in contact with said layer of silicon oxynitride.
- the electrical insulating material can be chosen from Si 3 N 4 and Ta 2 O 5 , for example.
- Figure 1 is a schematic section of a part of silicon substrate, before processing of the process for preparing the invention.
- FIGs 2 and 3 are schematic sections successive of the substrate part of Figure 1 after deoxidation and treatment steps of the invention.
- Figure 4 is a schematic section of a part of the substrate of Figure 3 on which we have formed a thin insulating layer.
- Figure 1 shows part of a substrate silicon 10, monocrystalline or polycrystalline, with a free face marked with the reference 12.
- the face 12 is covered, before the treatment, of an oxide layer 14.
- the oxide layer 14 can be a layer of native oxide which is formed naturally by contact of silicon with air, or an oxide layer obtained by heat treatment.
- the silicon substrate may include components or parts of components, such as transistor channels or memory structures by example. These components or parts of components do not are not described in detail here, nor shown in the figures, since they can vary according to the intended application.
- a first step in the process is a step of deoxidation which aims to remove the oxide layer 14.
- Deoxidation can be carried out by chemical by immersing the substrate 10 in a solution HF (hydrofluoric acid) diluted in water.
- HF hydrofluoric acid
- the acid concentration is around 1% or even weaker.
- the substrate is then placed in an enclosure 20 in which establishes a gaseous atmosphere of NO.
- the pressure of the gas in the enclosure 20 is of the order of 5.10 3 Pa (50 mBar), or less.
- the substrate undergoes a heat treatment, at a temperature below 750 ° C, and preferably less than 700 ° C when the components produced are DRAM, to form a layer 22 of silicon oxynitride, of formula SixNyOz, on side 12.
- the parameters x, y and z are stoichiometric parameters).
- Table I indicates the proportions of Si, O and N of the layer 22 of oxynitride for heat treatments carried out at 550 ° C and 700 ° C, at a pressure of 10 3 Pa and for 30 seconds. The table also indicates the thicknesses of the layers of silicon oxynitride obtained. Composition Yes % O% NOT % Thickness 700 ° C. 35 49 16 0.92 nm 550 ° C 37 45 17 0.65 nm
- Table I reveals that the composition of the silicon oxynitride layer changes little with the processing temperature. However the thickness of the layer is influenced.
- the substrate thus prepared can accommodate a layer of electrical insulation.
- the formation of the silicon nitride can take place in an oven 30 in which an atmosphere is established comprising an NH 3 / DCS (ammonia / dichlorosilane) mixture.
- an atmosphere comprising an NH 3 / DCS (ammonia / dichlorosilane) mixture.
- Nitride formation takes place by deposition chemical vapor phase (LPCVD) at a temperature less than 750 ° C, for example between 700 ° C and 750 ° C.
- LPCVD deposition chemical vapor phase
- nitride nucleating properties of silicon on substrate 10 are greatly improved by the presence of the silicon oxynitride layer 22, which eliminates the delay in nucleation.
- nucleation properties in particular the properties nucleation kinetics including time incubation and / or density of nucleation sites trained after a while.
- the oxynitride layer prevents oxidation between Si and Ta 2 O 5 .
- Table II indicates the thickness of layers 22 of silicon oxynitride and layers 24 of silicon nitride, for three samples processed differently.
- a first reference sample has not undergone a preparation process according to the invention, but has on its surface a layer of silicon oxide.
- Two other samples are prepared in accordance with the invention in an atmosphere of NO at 10 3 Pa for 30 seconds.
- the samples then receive an LPCVD deposit of silicon nitride under equivalent conditions, at 700 ° C., with an NH 3 / DCS ratio equal to 9, and for a period of the order of 10 to 20 minutes.
- Table II shows a modification of the delay nucleation. Indeed, the existence of the layer of silicon oxynitride 22, allows under the conditions identical LPCVD filing, get more training fast nitride.
- nitride layers 24 are homogeneous and continuous, despite their thinness.
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- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Engineering & Computer Science (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Inorganic Chemistry (AREA)
- Formation Of Insulating Films (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Description
- une étape de désoxydation d'au moins une partie du substrat de silicium, puis
- une étape de traitement thermique du substrat à une température inférieure ou égale à 750°C, le traitement thermique étant effectué dans une atmosphère à base de NO, à une pression inférieure ou égale à 5.103 Pa (50 mBar), et de préférence inférieure à 103Pa (10mBar), afin de former sur le substrat une couche d'oxynitrure de silicium, et
- une étape de formation, au moins sur ladite partie du substrat, d'une couche de matériau isolant électrique.
Composition | Si % | O % | N % | Epaisseur |
700°C | 35 | 49 | 16 | 0,92 nm |
550°C | 37 | 45 | 17 | 0,65 nm |
Conditions de nitruration / NO | Epaisseur de la couche d'oxynitrure 22 | Epaisseur de la couche de nitrure 24 | Différence | |
Echantillon 1 (référence) | sans | 0,9 nm (couche d'oxyde) | 3,5 nm | 2,55 nm |
Echantillon 2 | 550°C/30" | 0,7 nm | 4,44 nm | 3,74 nm |
Echantillon 3 | 700°C/30" | 0,92 nm | 4,5 nm | 3,58 nm |
FR-98 01963
L.F.Tz Kwakman, E.J. Lindow, E.H.A. Granneman, F. Martin, J.C. Veler, and JP Joly
Applied Surface Science 70/71, p. 629-633 (1993)
S. Saida, T. Sato, I. Mizushima, Y. Ozawa, Y. Tsunashima,
Extended Abstract of the IEDM, p. 265 ( 1997).
K. Kobayashi, Y. Inaba, T. Ogata, T. Katayama, H. Watanabe, Y. Matsui, M. Hirayama,
Journal of the Electrochemical Society, vol. 143, Nr 4, p. 1459 (1996)
B.Y. Kim, H.F. Luan, D.L. Kwong
Extended Abstract of the IEDM, p. 463 (1997).
F. Martin, F. Bertin, H. Sprey, E. Granneman Semicond. Sci. Technol. 6, p. 1100 (1991)
US-A-5 407 870
EP-A-0 798 769
Claims (10)
- Procédé de traitement d'un substrat de silicium comportant :une étape de désoxydation d'au moins une partie du substrat de silicium (10), puisune étape de traitement thermique du substrat à une température inférieure ou égale à 750°C, le traitement thermique étant effectué dans une atmosphère à base de NO à une pression inférieure ou égale à 5.103 Pa (50 mBar), etune étape de formation, au moins sur ladite partie du substrat, d'une couche de matériau isolant électrique.
- Procédé selon la revendication 1, dans lequel on effectue la désoxydation par voie chimique et par immersion du substrat dans une solution d'acide fluorhydrique dilué.
- Procédé selon la revendication 1, dans lequel l'étape de traitement thermique est mise en oeuvre pendant une durée suffisante pour obtenir une couche d'oxynitrure de silicium (22) présentant une épaisseur comprise entre 0,5 et 1,5 nm.
- Procédé selon la revendication 1, dans lequel le traitement thermique est effectué à une température de l'ordre de 550°C, une pression de l'ordre de 103 Pa (10 mBar) pendant une durée de l'ordre de 30 secondes.
- Procédé selon la revendication 1, dans lequel on forme la couche de matériau isolant électrique (24) selon un procédé de dépôt chimique en phase vapeur (LPVCD).
- Procédé selon la revendication 1, dans lequel on forme la couche de matériau isolant électrique (24) à une température inférieure ou égale à 750°C.
- Procédé selon la revendication 1, dans lequel le matériau isolant électrique est choisi parmi Si3N4 et Ta2O5.
- Procédé selon la revendication 1, dans lequel on forme une couche de matériau isolant électrique (24) présentant une épaisseur comprise entre 2 et 5 nm.
- Procédé selon la revendication 1, dans lequel on forme une couche de matériau isolant électrique en Si3N4, selon un procédé de dépôt chimique en phase vapeur (LPCVD), en présence de Si2H2Cl2.
- Substrat comportant dans l'ordre une couche de silicium (10) avec au moins une plage (12) dépourvue d'oxyde natif, une couche (22) d'oxynitrure de silicium présentant une épaisseur comprise entre 0,5 et 1,5 nm en contact avec ladite plage (12) et une couche en un matériau isolant électrique, présentant une épaisseur comprise entre 2 et 5 nm, en contact avec ladite couche d'oxynitrure de silicium, le matériau isolant électrique étant choisi parmi Si3N4 et Ta2O5.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9811746A FR2783530B1 (fr) | 1998-09-21 | 1998-09-21 | Procede de preparation, par nitruration, d'un substrat de silicium pour la formation d'une couche isolante mince |
FR9811746 | 1998-09-21 | ||
PCT/FR1999/002228 WO2000017412A1 (fr) | 1998-09-21 | 1999-09-20 | Procede de traitement, par nitruration, d'un substrat de silicium pour la formation d'une couche isolante mince |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1115895A1 EP1115895A1 (fr) | 2001-07-18 |
EP1115895B1 true EP1115895B1 (fr) | 2002-11-20 |
Family
ID=9530648
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP99943005A Expired - Lifetime EP1115895B1 (fr) | 1998-09-21 | 1999-09-20 | Procede de traitement, par nitruration, d'un substrat de silicium pour la formation d'une couche isolante mince |
Country Status (5)
Country | Link |
---|---|
US (1) | US6551698B1 (fr) |
EP (1) | EP1115895B1 (fr) |
DE (1) | DE69904069T2 (fr) |
FR (1) | FR2783530B1 (fr) |
WO (1) | WO2000017412A1 (fr) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101415882B (zh) * | 2006-02-28 | 2011-12-28 | 赢创德固赛公司 | 有色纸和具有增强的印刷性能的经涂布的基底 |
BRPI0717292A2 (pt) * | 2006-09-26 | 2013-01-22 | Evonik Degussa Corp | papel multifuncional para desempenho de impressço aumentada |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4438157A (en) * | 1980-12-05 | 1984-03-20 | Ncr Corporation | Process for forming MNOS dual dielectric structure |
CA1317034C (fr) * | 1988-09-30 | 1993-04-27 | Alliedsignal Inc. | Fabrication de microstructures d'oxynitride |
JPH03160720A (ja) * | 1989-11-20 | 1991-07-10 | Oki Electric Ind Co Ltd | 絶縁膜形成方法 |
KR930002661B1 (ko) * | 1990-05-10 | 1993-04-07 | 금성일렉트론 주식회사 | 수직 lpcvd법을 이용한 질산화막 실리콘 제조장치 및 방법 |
US5407870A (en) * | 1993-06-07 | 1995-04-18 | Motorola Inc. | Process for fabricating a semiconductor device having a high reliability dielectric material |
KR970009863B1 (ko) * | 1994-01-22 | 1997-06-18 | 금성일렉트론 주식회사 | 반도체 소자의 실리콘절연막형성방법 |
US5674788A (en) * | 1995-06-06 | 1997-10-07 | Advanced Micro Devices, Inc. | Method of forming high pressure silicon oxynitride gate dielectrics |
US5861190A (en) * | 1996-03-25 | 1999-01-19 | Hewlett-Packard Co. | Arrangement for growing a thin dielectric layer on a semiconductor wafer at low temperatures |
CA2213034C (fr) * | 1996-09-02 | 2002-12-17 | Murata Manufacturing Co., Ltd. | Dispositif semiconducteur comportant un film de passivation |
WO1998027580A1 (fr) * | 1996-12-03 | 1998-06-25 | Scott Specialty Gases, Inc. | Procede de formation de couches ultra-minces d'oxynitrure et de dispositifs a couches minces renfermant des couches ultra-minces d'oxynitrure |
US5843817A (en) * | 1997-09-19 | 1998-12-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Process for integrating stacked capacitor DRAM devices with MOSFET devices used for high performance logic circuits |
FR2775120B1 (fr) | 1998-02-18 | 2000-04-07 | France Telecom | Procede de nitruration de la couche d'oxyde de grille d'un dispositif semiconducteur et dispositif obtenu |
-
1998
- 1998-09-21 FR FR9811746A patent/FR2783530B1/fr not_active Expired - Fee Related
-
1999
- 1999-09-20 DE DE69904069T patent/DE69904069T2/de not_active Expired - Lifetime
- 1999-09-20 US US09/763,532 patent/US6551698B1/en not_active Expired - Fee Related
- 1999-09-20 WO PCT/FR1999/002228 patent/WO2000017412A1/fr active IP Right Grant
- 1999-09-20 EP EP99943005A patent/EP1115895B1/fr not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69904069T2 (de) | 2003-07-17 |
DE69904069D1 (de) | 2003-01-02 |
FR2783530A1 (fr) | 2000-03-24 |
EP1115895A1 (fr) | 2001-07-18 |
WO2000017412A1 (fr) | 2000-03-30 |
FR2783530B1 (fr) | 2001-08-31 |
US6551698B1 (en) | 2003-04-22 |
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