EP1115895B1 - Verfahren zum nitrieren eines silizium-substrates zur erzeugung einer isolationsbeschichtung - Google Patents

Verfahren zum nitrieren eines silizium-substrates zur erzeugung einer isolationsbeschichtung Download PDF

Info

Publication number
EP1115895B1
EP1115895B1 EP99943005A EP99943005A EP1115895B1 EP 1115895 B1 EP1115895 B1 EP 1115895B1 EP 99943005 A EP99943005 A EP 99943005A EP 99943005 A EP99943005 A EP 99943005A EP 1115895 B1 EP1115895 B1 EP 1115895B1
Authority
EP
European Patent Office
Prior art keywords
layer
substrate
silicon
insulating material
electric insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP99943005A
Other languages
English (en)
French (fr)
Other versions
EP1115895A1 (de
Inventor
François Martin
Daniel Bensahel
Caroline Hernandez
Laurent Vallier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Orange SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
France Telecom SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, France Telecom SA filed Critical Commissariat a lEnergie Atomique CEA
Publication of EP1115895A1 publication Critical patent/EP1115895A1/de
Application granted granted Critical
Publication of EP1115895B1 publication Critical patent/EP1115895B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/04—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings of inorganic non-metallic material
    • C23C28/044—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings of inorganic non-metallic material coatings specially adapted for cutting tools or wear applications
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C8/00—Solid state diffusion of only non-metal elements into metallic material surfaces; Chemical surface treatment of metallic material by reaction of the surface with a reactive gas, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals
    • C23C8/06—Solid state diffusion of only non-metal elements into metallic material surfaces; Chemical surface treatment of metallic material by reaction of the surface with a reactive gas, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals using gases
    • C23C8/28—Solid state diffusion of only non-metal elements into metallic material surfaces; Chemical surface treatment of metallic material by reaction of the surface with a reactive gas, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals using gases more than one element being applied in one step
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24926—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer

Definitions

  • the present invention relates to a method of treatment of a silicon substrate for the formation on at least one of its faces, of a layer of an electrical insulating material such as, for example example, a layer of silicon nitride.
  • the invention finds applications in the realization of electronic devices with components comprising an electrical insulating layer thin and especially for the production of memories of DRAM (dynamic direct access memory) or EPROM type (programmable / erasable read-only memory).
  • DRAM dynamic direct access memory
  • EPROM type programmable / erasable read-only memory
  • insulated gate transistors such as transistors MOS or other components such as capabilities.
  • the grid layer for the components made on a silicon substrate, is usually a layer of silicon oxide.
  • Diffusion problems of doping impurities can be solved, at least in part, by incorporating into the gate oxide components a appropriate dose of nitrogen, including using a nitriding treatment.
  • the layer oxide can be combined or possibly replaced by a layer of silicon nitride.
  • Document [1] shows in particular that it is not possible to form a nitride layer homogeneous and continuous with a thickness of less than 5 nm on a native oxide layer on the surface of a substrate.
  • Document [2] proposes to solve the problems of continuity or inhomogeneity of the thin nitride layers ( ⁇ 3 nm) by subjecting them to rapid annealing under an NH 3 atmosphere at temperatures of the order of 950 ° C.
  • a rapid annealing under an NH 3 atmosphere at temperatures of the order of 950 ° C.
  • annealing because of its high temperature, is capable of altering electronic components previously formed in the substrate.
  • Documents [3] and [4] describe techniques according to which a native oxide layer, initially present on the surface of a substrate of silicon, is removed before the formation of a layer nitride, by chemical vapor deposition, on the exposed silicon surface. Deoxidation of substrate can take place by annealing under hydrogen or chemically with hydrofluoric acid.
  • document (5) proposes to form on the substrate a layer of silicon oxynitride, prior to the layer of silicon nitride.
  • the oxynitride layer is formed under an atmosphere of NO.
  • the silicon nitride layer is formed from SiH 4 and NH 3 gases in a single-plate type reactor.
  • the enrichment of the silane treatment gases (SiH 4 ) promotes the nucleation of the silicon nitride but alters its stoichiometric quality.
  • the use of a single-plate reactor is also not very compatible with an industrial production of components, at low production costs.
  • the document (7) whose complete reference is also specified at the end of the description, further describes a method of forming a layer of insulating material. This process implements several heat treatments at a temperature above 900 ° C.
  • Document (8) describes a process for forming a dielectric layer at a temperature comprised preferably between 700 ° C and 850 ° C.
  • the object of the invention is to propose a method for preparing a substrate allowing the formation of a thin layer of electrical insulation having no not the difficulties mentioned above.
  • One goal is in particular to propose such a process for forming a nitride layer fine, continuous and homogeneous, on a substrate of silicon.
  • An object of the invention is also to propose a process using thermal budgets and reduced temperatures.
  • NO-based atmosphere means a atmosphere of pure NO or NO diluted with an inert gas such as nitrogen or argon.
  • Heat treatment makes it possible to form surface of the deoxidized part of the substrate a layer very fine silicon oxynitride whose thickness may be less than a nanometer. This layer allows then form a thin, homogeneous insulating layer and carry on.
  • the oxynitride layer makes it possible to avoid the formation on the substrate of parasitic deposits of metal oxides such as Ta 2 O 5 which may appear during oxidative treatments.
  • the heat treatment of the process is implemented works at temperatures below 750 ° C, for example at a temperature of the order of 550 ° C.
  • the process can thus be applied to substrates with relatively electronic components heat sensitive, pre-formed.
  • the heat treatment can be implemented with sufficient duration to obtain an oxynitride layer having a thickness between 0.5 and 1.5 nm.
  • the heat treatment can be carried out at a temperature of the order of 550 ° C., a pressure of the order of 10 3 Pa (10 mBar), for a duration of the order of 30 seconds for obtain a 0.7 nm layer of oxynitride.
  • the silicon substrate used may have undergone prior treatments in order to form components or parts of electronic components.
  • the layer of electrical insulating material formed on the substrate can be a layer of silicon nitride (Si 3 N 4 ) or a layer of Ta 2 O 5 , chosen for their high permittivity.
  • this can preferably be formed by a process of the LPCVD type (chemical vapor deposition at low pressure) in the presence of a dichlorisilane-based atmosphere ( SiH 2 Cl 2 ) and / or ammonia NH 3 .
  • the deposition is carried out at a temperature less than or equal to 750 ° C., for example, 700 ° C.
  • the invention also relates to a substrate, obtainable according to the method described above and comprising, in order, a layer of silicon with at least one area devoid of native oxide, a layer of silicon oxynitride having a thickness between 0.5 and 1.5 nm in contact with said range, and a layer of an electrical insulating material, having a thickness between 2 and 5 nm, in contact with said layer of silicon oxynitride.
  • the electrical insulating material can be chosen from Si 3 N 4 and Ta 2 O 5 , for example.
  • Figure 1 is a schematic section of a part of silicon substrate, before processing of the process for preparing the invention.
  • FIGs 2 and 3 are schematic sections successive of the substrate part of Figure 1 after deoxidation and treatment steps of the invention.
  • Figure 4 is a schematic section of a part of the substrate of Figure 3 on which we have formed a thin insulating layer.
  • Figure 1 shows part of a substrate silicon 10, monocrystalline or polycrystalline, with a free face marked with the reference 12.
  • the face 12 is covered, before the treatment, of an oxide layer 14.
  • the oxide layer 14 can be a layer of native oxide which is formed naturally by contact of silicon with air, or an oxide layer obtained by heat treatment.
  • the silicon substrate may include components or parts of components, such as transistor channels or memory structures by example. These components or parts of components do not are not described in detail here, nor shown in the figures, since they can vary according to the intended application.
  • a first step in the process is a step of deoxidation which aims to remove the oxide layer 14.
  • Deoxidation can be carried out by chemical by immersing the substrate 10 in a solution HF (hydrofluoric acid) diluted in water.
  • HF hydrofluoric acid
  • the acid concentration is around 1% or even weaker.
  • the substrate is then placed in an enclosure 20 in which establishes a gaseous atmosphere of NO.
  • the pressure of the gas in the enclosure 20 is of the order of 5.10 3 Pa (50 mBar), or less.
  • the substrate undergoes a heat treatment, at a temperature below 750 ° C, and preferably less than 700 ° C when the components produced are DRAM, to form a layer 22 of silicon oxynitride, of formula SixNyOz, on side 12.
  • the parameters x, y and z are stoichiometric parameters).
  • Table I indicates the proportions of Si, O and N of the layer 22 of oxynitride for heat treatments carried out at 550 ° C and 700 ° C, at a pressure of 10 3 Pa and for 30 seconds. The table also indicates the thicknesses of the layers of silicon oxynitride obtained. Composition Yes % O% NOT % Thickness 700 ° C. 35 49 16 0.92 nm 550 ° C 37 45 17 0.65 nm
  • Table I reveals that the composition of the silicon oxynitride layer changes little with the processing temperature. However the thickness of the layer is influenced.
  • the substrate thus prepared can accommodate a layer of electrical insulation.
  • the formation of the silicon nitride can take place in an oven 30 in which an atmosphere is established comprising an NH 3 / DCS (ammonia / dichlorosilane) mixture.
  • an atmosphere comprising an NH 3 / DCS (ammonia / dichlorosilane) mixture.
  • Nitride formation takes place by deposition chemical vapor phase (LPCVD) at a temperature less than 750 ° C, for example between 700 ° C and 750 ° C.
  • LPCVD deposition chemical vapor phase
  • nitride nucleating properties of silicon on substrate 10 are greatly improved by the presence of the silicon oxynitride layer 22, which eliminates the delay in nucleation.
  • nucleation properties in particular the properties nucleation kinetics including time incubation and / or density of nucleation sites trained after a while.
  • the oxynitride layer prevents oxidation between Si and Ta 2 O 5 .
  • Table II indicates the thickness of layers 22 of silicon oxynitride and layers 24 of silicon nitride, for three samples processed differently.
  • a first reference sample has not undergone a preparation process according to the invention, but has on its surface a layer of silicon oxide.
  • Two other samples are prepared in accordance with the invention in an atmosphere of NO at 10 3 Pa for 30 seconds.
  • the samples then receive an LPCVD deposit of silicon nitride under equivalent conditions, at 700 ° C., with an NH 3 / DCS ratio equal to 9, and for a period of the order of 10 to 20 minutes.
  • Table II shows a modification of the delay nucleation. Indeed, the existence of the layer of silicon oxynitride 22, allows under the conditions identical LPCVD filing, get more training fast nitride.
  • nitride layers 24 are homogeneous and continuous, despite their thinness.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Formation Of Insulating Films (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Claims (10)

  1. Verfahren zur Behandlung eines Siliciumsubstrats, umfassend:
    einen Schritt zur Desoxidierung wenigstens eines Teils des Siliciumsubstrats (10), sodann
    einen Schritt zur thermischen Behandlung des Substrats bei einer Temperatur unter oder gleich 750°C, wobei die thermische Behandlung in einer Atmosphäre auf NO-Basis bei einem Druck unter oder gleich 5.103 Pa (50 mBar) stattfindet, und
    einen Schritt zur Ausbildung einer Schicht aus elektrisch isolierendem Material, wenigstens auf dem genannten Teil des Substrats.
  2. Verfahren nach Anspruch 1, bei dem die Desoxidierung auf chemischem Wege und durch Eintauchen des Substrats in eine Lösung aus verdünnter Fluorwasserstoffsäure erfolgt.
  3. Verfahren nach Anspruch 1, bei dem der Schritt zur thermischen Behandlung ausreichend lange dauert, um eine Schicht aus Siliciumoxinitrid (22) zu erhalten, die eine zwischen 0,5 und 1,5 nm enthaltene Dicke aufweist.
  4. Verfahren nach Anspruch 1, bei dem die thermische Behandlung bei einer Temperatur in der Größenordnung von 550°C und einem Druck in der Größenordnung von 103 Pa (10 mBar) während einer Dauer von ungefähr 30 Sekunden erfolgt.
  5. Verfahren nach Anspruch 1, bei dem man die Schicht aus elektrisch isolierendem Material (24) nach einem chemischen Gasphasenabscheidungsverfahren (LPCVD) erzeugt.
  6. Verfahren nach Anspruch 1, bei dem man die Schicht aus elektrisch isolierendem Material (24) bei einer Temperatur unter oder gleich 750°C erzeugt.
  7. Verfahren nach Anspruch 1, bei dem das elektrisch isolierende Material ausgewählt wird zwischen Si3N4 und Ta2O5.
  8. Verfahren nach Anspruch 1, bei dem man eine Schicht aus elektrisch isolierendem Material (24) mit einer zwischen 2 und 5 nm enthaltenen Dicke erzeugt.
  9. Verfahren nach Anspruch 1, bei dem man eine elektrisch isolierende Materialschicht aus Si3N4 nach einem Gasphasenabscheidungsverfahren (LPCVD) unter Präsenz von Si2H2Cl2 erzeugt.
  10. Substrat, in dieser Reihenfolge eine Schicht (10) mit wenigstens einem Bereich (12) ohne gediegenes Oxid, eine Schicht (22) aus Siliciumoxinitrid mit einer zwischen 0,5 und 1,5 nm enthaltenen Dicke, in Kontakt mit dem genannten Bereich (12), und eine Schicht aus einem elektrisch isolierenden Material mit einer Dicke zwischen 2 und 5 nm umfassend, in Kontakt mit der genannten Schicht aus Siliciumoxinitrid, wobei das elektrisch isolierende Material ausgewählt wird zwischen Si3N4 und Ta2O5.
EP99943005A 1998-09-21 1999-09-20 Verfahren zum nitrieren eines silizium-substrates zur erzeugung einer isolationsbeschichtung Expired - Lifetime EP1115895B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9811746A FR2783530B1 (fr) 1998-09-21 1998-09-21 Procede de preparation, par nitruration, d'un substrat de silicium pour la formation d'une couche isolante mince
FR9811746 1998-09-21
PCT/FR1999/002228 WO2000017412A1 (fr) 1998-09-21 1999-09-20 Procede de traitement, par nitruration, d'un substrat de silicium pour la formation d'une couche isolante mince

Publications (2)

Publication Number Publication Date
EP1115895A1 EP1115895A1 (de) 2001-07-18
EP1115895B1 true EP1115895B1 (de) 2002-11-20

Family

ID=9530648

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99943005A Expired - Lifetime EP1115895B1 (de) 1998-09-21 1999-09-20 Verfahren zum nitrieren eines silizium-substrates zur erzeugung einer isolationsbeschichtung

Country Status (5)

Country Link
US (1) US6551698B1 (de)
EP (1) EP1115895B1 (de)
DE (1) DE69904069T2 (de)
FR (1) FR2783530B1 (de)
WO (1) WO2000017412A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1989356A2 (de) * 2006-02-28 2008-11-12 Evonik Degussa Corporation Farbpapier und beschichtete substrate zur verbesserten druckleistung
EP2066840A1 (de) * 2006-09-26 2009-06-10 Evonik Degussa Corporation Multifunktionspapier für erhöhte druckleistung

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4438157A (en) * 1980-12-05 1984-03-20 Ncr Corporation Process for forming MNOS dual dielectric structure
CA1317034C (en) * 1988-09-30 1993-04-27 Alliedsignal Inc. Fabrication of oxynitride frontside microstructures
JPH03160720A (ja) * 1989-11-20 1991-07-10 Oki Electric Ind Co Ltd 絶縁膜形成方法
KR930002661B1 (ko) * 1990-05-10 1993-04-07 금성일렉트론 주식회사 수직 lpcvd법을 이용한 질산화막 실리콘 제조장치 및 방법
US5407870A (en) * 1993-06-07 1995-04-18 Motorola Inc. Process for fabricating a semiconductor device having a high reliability dielectric material
KR970009863B1 (ko) * 1994-01-22 1997-06-18 금성일렉트론 주식회사 반도체 소자의 실리콘절연막형성방법
US5674788A (en) * 1995-06-06 1997-10-07 Advanced Micro Devices, Inc. Method of forming high pressure silicon oxynitride gate dielectrics
US5861190A (en) * 1996-03-25 1999-01-19 Hewlett-Packard Co. Arrangement for growing a thin dielectric layer on a semiconductor wafer at low temperatures
CA2213034C (en) * 1996-09-02 2002-12-17 Murata Manufacturing Co., Ltd. A semiconductor device with a passivation film
WO1998027580A1 (en) * 1996-12-03 1998-06-25 Scott Specialty Gases, Inc. Process for forming ultrathin oxynitride layers and thin layer devices containing ultrathin oxynitride layers
US5843817A (en) * 1997-09-19 1998-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Process for integrating stacked capacitor DRAM devices with MOSFET devices used for high performance logic circuits
FR2775120B1 (fr) 1998-02-18 2000-04-07 France Telecom Procede de nitruration de la couche d'oxyde de grille d'un dispositif semiconducteur et dispositif obtenu

Also Published As

Publication number Publication date
EP1115895A1 (de) 2001-07-18
FR2783530A1 (fr) 2000-03-24
US6551698B1 (en) 2003-04-22
DE69904069D1 (de) 2003-01-02
WO2000017412A1 (fr) 2000-03-30
FR2783530B1 (fr) 2001-08-31
DE69904069T2 (de) 2003-07-17

Similar Documents

Publication Publication Date Title
EP0780889B1 (de) Verfahren zur selektiven Abscheidung von Siliciden hochschmelzender Metalle auf Silizium
EP0887843B1 (de) Verfahren zur Herstellung eines Transistors mit einem Silizium-Germanium-Gatter
US7658973B2 (en) Tailoring nitrogen profile in silicon oxynitride using rapid thermal annealing with ammonia under ultra-low pressure
KR100266519B1 (ko) 다중레벨구조의절연체를가진반도체장치및그제조방법
JPH09116104A (ja) 半導体素子のキャパシタ製造方法
JP4003846B2 (ja) 半導体装置のキャパシタ製造方法
EP0976149B1 (de) Verfahren zur verminderung der interdiffusion in einem halbleiterbauelement mit si/sige verbindungs-gatter
US4879253A (en) Method for fabricating a semiconductor device using a BPSG layer containing high concentrations of phosphorus and boron
US7192887B2 (en) Semiconductor device with nitrogen in oxide film on semiconductor substrate and method of manufacturing the same
US7326988B2 (en) Semiconductor device and method for fabricating the same
EP0976148B1 (de) Verfahren zur nitridierung der gatter-oxydschicht von einem halbleiterbauelement
EP1115895B1 (de) Verfahren zum nitrieren eines silizium-substrates zur erzeugung einer isolationsbeschichtung
EP1900014A2 (de) Zum grossteil aus siliciumcarbid hergestelltes und mit einer dünnen stöchiometrischen folie aus siliciumnitrid beschichtetes substrat zur erzeugung elektronischer komponenten und verfahren zur gewinnung einer solchen folie
FR2731841A1 (fr) Transistors a effet de champ du type a grille isolee et son procede de fabrication
US6579614B2 (en) Structure having refractory metal film on a substrate
US20070131985A1 (en) Semiconductor device and method for manufacturing the same
US20040005788A1 (en) Method of forming a silicon nitride dielectric layer
JPH09260372A (ja) 半導体装置の絶縁膜の形成方法
KR0138125B1 (ko) 트랜지스터의 게이트 유전막 형성 방법
US5908321A (en) Semiconductor structure with stable pre-reacted particle and method for making
KR20000003915A (ko) 반도체 소자의 게이트 절연막 형성방법
CN115668466A (zh) SiC半导体元件的制造方法及SiC半导体元件
KR100457754B1 (ko) 반도체소자의메탈콘택형성방법
WO2001024249A1 (fr) Procede pour empêcher la diffusion de bore dans le silicium par implantation ionique de carbone
KR20020090571A (ko) 반도체소자의 게이트절연막 제조방법

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20010222

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

17Q First examination report despatched

Effective date: 20010719

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE GB IT

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

Free format text: NOT ENGLISH

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

Free format text: FRENCH

REF Corresponds to:

Ref document number: 69904069

Country of ref document: DE

Date of ref document: 20030102

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 20030403

REG Reference to a national code

Ref country code: IE

Ref legal event code: FD4D

Ref document number: 1115895E

Country of ref document: IE

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20030821

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: IT

Payment date: 20100924

Year of fee payment: 12

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20110923

Year of fee payment: 13

Ref country code: GB

Payment date: 20110920

Year of fee payment: 13

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20120920

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120920

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20130403

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120920

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 69904069

Country of ref document: DE

Effective date: 20130403