EP1111686A4 - Halbleiter gegenstand und verfahren zum herstellen - Google Patents

Halbleiter gegenstand und verfahren zum herstellen

Info

Publication number
EP1111686A4
EP1111686A4 EP00937291A EP00937291A EP1111686A4 EP 1111686 A4 EP1111686 A4 EP 1111686A4 EP 00937291 A EP00937291 A EP 00937291A EP 00937291 A EP00937291 A EP 00937291A EP 1111686 A4 EP1111686 A4 EP 1111686A4
Authority
EP
European Patent Office
Prior art keywords
manufacturing
same
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP00937291A
Other languages
English (en)
French (fr)
Other versions
EP1111686A1 (de
Inventor
Teruo Takizawa
Hiroyuki Shimada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of EP1111686A1 publication Critical patent/EP1111686A1/de
Publication of EP1111686A4 publication Critical patent/EP1111686A4/de
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01314—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of Ge, C or of compounds of Si, Ge or C contacting the insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
EP00937291A 1999-06-23 2000-06-16 Halbleiter gegenstand und verfahren zum herstellen Ceased EP1111686A4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP17707899 1999-06-23
JP17707899 1999-06-23
PCT/JP2000/003968 WO2000079601A1 (fr) 1999-06-23 2000-06-16 Dispositif a semi-conducteur et procede de fabrication dudit dispositif

Publications (2)

Publication Number Publication Date
EP1111686A1 EP1111686A1 (de) 2001-06-27
EP1111686A4 true EP1111686A4 (de) 2005-05-11

Family

ID=16024751

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00937291A Ceased EP1111686A4 (de) 1999-06-23 2000-06-16 Halbleiter gegenstand und verfahren zum herstellen

Country Status (4)

Country Link
US (1) US6787805B1 (de)
EP (1) EP1111686A4 (de)
KR (1) KR100695047B1 (de)
WO (1) WO2000079601A1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6423632B1 (en) * 2000-07-21 2002-07-23 Motorola, Inc. Semiconductor device and a process for forming the same
EP1540720A4 (de) * 2002-06-26 2007-09-26 Semequip Inc Halbleiterbauelement und verfahren zur herstellung eines halbleiterbauelements
US6905976B2 (en) * 2003-05-06 2005-06-14 International Business Machines Corporation Structure and method of forming a notched gate field effect transistor
WO2006012544A2 (en) * 2004-07-22 2006-02-02 The Board Of Trustees Of The Leland Stanford Junior University Germanium substrate-type materials and approach therefor
DE102004052581B4 (de) * 2004-10-29 2008-11-20 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer CMOS-Gatestruktur mit einem vordotierten Halbleitergatematerial
JP2006278873A (ja) * 2005-03-30 2006-10-12 Seiko Epson Corp 半導体装置およびその製造方法
KR100652426B1 (ko) * 2005-08-16 2006-12-01 삼성전자주식회사 도펀트 침투를 방지한 반도체 소자의 커패시터 및 그제조방법
DE102006013721B4 (de) * 2006-03-24 2011-12-08 Infineon Technologies Ag Halbleiterschaltungsanordnung und zugehöriges Verfahren zur Temperaturerfassung
WO2021065578A1 (ja) * 2019-10-04 2021-04-08 国立大学法人東京工業大学 光変調素子
US20230209795A1 (en) * 2021-12-23 2023-06-29 Globalfoundries U.S. Inc. Sram bit cells

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5101247A (en) * 1990-04-27 1992-03-31 North Carolina State University Germanium silicon dioxide gate MOSFET
JPH1027854A (ja) * 1996-07-10 1998-01-27 Sony Corp 半導体装置及びその製造方法
EP0887843A1 (de) * 1997-06-25 1998-12-30 France Telecom Verfahren zur Herstellung eines Transistors mit einem Silizium-Germanium-Gatter
US5861336A (en) * 1993-07-12 1999-01-19 Peregrine Semiconductor Corporation High-frequency wireless communication system on a single ultrathin silicon on sapphire chip

Family Cites Families (16)

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Publication number Priority date Publication date Assignee Title
JPS4822022B1 (de) 1969-11-21 1973-07-03
JPS63198373A (ja) 1987-02-13 1988-08-17 Nec Corp 半導体装置およびその製造方法
JP2518334B2 (ja) 1988-01-20 1996-07-24 日立電線株式会社 耐捩じれ変形自己融着性エナメル線
JPH01117182A (ja) 1988-06-14 1989-05-10 Kunimune Kogyosho:Kk 糸止め付き糸ボビン
US5801444A (en) * 1989-09-29 1998-09-01 International Business Machines Corporation Multilevel electronic structures containing copper layer and copper-semiconductor layers
JP3061406B2 (ja) * 1990-09-28 2000-07-10 株式会社東芝 半導体装置
JP2876866B2 (ja) 1992-02-19 1999-03-31 日本電気株式会社 半導体装置
US5227333A (en) * 1992-02-27 1993-07-13 International Business Machines Corporation Local interconnection having a germanium layer
SG43836A1 (en) 1992-12-11 1997-11-14 Intel Corp A mos transistor having a composite gate electrode and method of fabrication
JPH07202178A (ja) 1993-12-28 1995-08-04 Toshiba Corp 半導体装置およびその製造方法
JPH07288323A (ja) 1994-04-19 1995-10-31 Sony Corp 絶縁ゲート型電界効果トランジスタとその製法
US5608249A (en) * 1995-11-16 1997-03-04 Micron Technology, Inc. Reduced area storage node junction
KR100212693B1 (ko) * 1996-12-14 1999-08-02 권혁준 규소/규소게르마늄 모스 전계 트랜지스터 및 그 제조방법
JPH113999A (ja) 1997-06-13 1999-01-06 Sony Corp 半導体装置の製造方法
JPH1117182A (ja) 1997-06-26 1999-01-22 Sony Corp 半導体装置およびその製造方法
JP3039493B2 (ja) 1997-11-28 2000-05-08 日本電気株式会社 基板の洗浄方法及び洗浄溶液

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5101247A (en) * 1990-04-27 1992-03-31 North Carolina State University Germanium silicon dioxide gate MOSFET
US5861336A (en) * 1993-07-12 1999-01-19 Peregrine Semiconductor Corporation High-frequency wireless communication system on a single ultrathin silicon on sapphire chip
JPH1027854A (ja) * 1996-07-10 1998-01-27 Sony Corp 半導体装置及びその製造方法
EP0887843A1 (de) * 1997-06-25 1998-12-30 France Telecom Verfahren zur Herstellung eines Transistors mit einem Silizium-Germanium-Gatter
US5998289A (en) * 1997-06-25 1999-12-07 France Telecom Process for obtaining a transistor having a silicon-germanium gate

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
ALIEU J ET AL: "Pure Ge mid-gap gate within an industrial high performance and low standby current 0.18 /spl mu/m CMOS process", VLSI TECHNOLOGY, 1998. DIGEST OF TECHNICAL PAPERS. 1998 SYMPOSIUM ON HONOLULU, HI, USA 9-11 JUNE 1998, NEW YORK, NY, USA,IEEE, US, 9 June 1998 (1998-06-09), pages 192 - 193, XP010291204, ISBN: 0-7803-4770-6 *
BENSAHEL D ET AL: "SINGLE-WAFER PROCESSING OF IN SITU-DOPED POLYCRYSTALLINE SI AND SI1-XGEX", SOLID STATE TECHNOLOGY, COWAN PUBL.CORP. WASHINGTON, US, vol. 41, no. 3, March 1998 (1998-03-01), pages S05 - S06,S08,S1, XP000735101, ISSN: 0038-111X *
OEZTUERK M C ET AL: "RAPID THERMAL CHEMICAL VAPOR DEPOSITION OF GERMANIUM AND GERMANIUM/SILICON ALLOYS ON SILICON: NEW APPLICATIONS IN THE FABRICATION OF MOS TRANSISTORS", MATERIALS RESEARCH SOCIETY SYMPOSIUM PROCEEDINGS, MATERIALS RESEARCH SOCIETY, PITTSBURG, PA, US, vol. 224, 30 April 1991 (1991-04-30), pages 223 - 234, XP000198032, ISSN: 0272-9172 *
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 05 30 April 1998 (1998-04-30) *
PONOMAREV Y V ET AL: "Gate-workfunction engineering using poly-(Si,Ge) for high-performance 0.18 /spl mu/m CMOS technology", ELECTRON DEVICES MEETING, 1997. TECHNICAL DIGEST., INTERNATIONAL WASHINGTON, DC, USA 7-10 DEC. 1997, NEW YORK, NY, USA,IEEE, US, 7 December 1997 (1997-12-07), pages 829 - 832, XP010265631, ISBN: 0-7803-4100-7 *

Also Published As

Publication number Publication date
WO2000079601A1 (fr) 2000-12-28
EP1111686A1 (de) 2001-06-27
KR20010072870A (ko) 2001-07-31
KR100695047B1 (ko) 2007-03-14
US6787805B1 (en) 2004-09-07

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