Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/0008—Arrangements for reducing power consumption
  • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply

Definitions

• the invention relates to a circuit arrangement with circuit parts consisting of transistors of low threshold voltage (NV transistors).
• NV transistors low threshold voltage
• a low current consumption of microelectronic circuit arrangements is desirable, since the service life is correspondingly prolonged for a given battery or accumulator capacity.
• the current consumption is reduced, for example, by reducing the supply voltage, which, however, leads to reduced switching speeds in the case of MOS transistors.
• the threshold voltage of the transistors must be reduced in addition to the supply voltage.
• a supply voltage of, for example, 1 volt threshold voltages of the transistors of typically 0.3 to 0.2 volt (corresponding to a value of a quarter of the supply voltage) are required, compared with 0.6 to approximately 0.4 volt threshold voltage at a supply voltage of 3 , 3 volts.
• Such low operating voltages lead to greatly increased leakage currents with closed, i.e. uncontrolled transistors, which leads to a load on the battery or the accumulator, particularly in the case of long idle phases ("standby") of the circuit arrangements.
• these transistors are activated (the gate voltages of VDD and VSS are at the NMOS or PMOS transistor), the local supply lines VDDL and VSSL are thus at VDD or VSS.
• the transistors are closed (there are gate voltages from VSS and VDD at the NMOS or PMOS transistor), and the current consumption is then reduced to the low leakage currents due to the high threshold voltages of the switching transistors.
• circuit parts that store the data retain their information. If the high-voltage switching transistors are closed, the high leakage currents of the NV transistors (transistors of low threshold voltage) of the circuit arrangement lead to an equalization of all voltages within the circuit arrangement after some time, as a result of which the information of the storing elements in the circuit parts is lost.
• One way to prevent the loss of information is to use transistors with a high threshold voltage in the storing circuit parts. However, this basically requires new circuit designs because of the adaptation of the storing circuit parts.
• the disadvantage of this measure is that two additional voltages are required and that regardless of the duration of the standby If the circuit parts are only to be deactivated, only the threshold voltages of the transistors in the wells can be influenced (in the case of n-well processes, these are the PMOS transistors), and the substrate potential is the same for all circuit parts.
• the invention has for its object to provide a microelectronic circuit arrangement, in particular for portable applications with a low current consumption, in which, in addition to a low current consumption, a high switching speed of the transistors is guaranteed at the same time, and in which the leakage currents when the transistor is closed are not 4 controlled transistors of the circuit parts and thus the
• Load on the battery or accumulator capacity can in particular be reduced during long periods of rest of the circuit arrangement.
• the circuit part is coupled to a supply voltage (VDD, VSS) by interposing a switching transistor with a high threshold voltage (HV transistor), an NV control transistor being connected in parallel with the HV switching transistor.
• VDD supply voltage
• VSS supply voltage
• HV transistor high threshold voltage
• the invention enables the leakage current of circuits and circuit parts consisting of transistors with low threshold voltages (LV transistors) to be reduced, the solution according to the invention having the following advantages over the previously known measures:
• Figure 1A shows a circuit arrangement according to the invention according to a first embodiment
• FIG. 1B shows a schematic curve over time of the supply voltage VDDL of the circuit arrangement according to the first exemplary embodiment
• Figure 2A shows a circuit arrangement according to the invention according to a second embodiment
• FIG. 2B shows a schematic course of the curve over time
• Figure 3A shows a circuit arrangement according to the invention according to a third embodiment
• FIG. 3B shows a schematic course of the curve over time
• FIG. 4A shows a circuit arrangement according to the invention in accordance with a fourth exemplary embodiment
• FIG. 4B shows a schematic course of the curve over time
• FIG. 5A shows a circuit arrangement according to the invention in accordance with a fifth exemplary embodiment
• FIG. 5B shows a schematic course of the curve over time
• FIG. 6 shows a schematic diagram of the PMOS leakage current versus the supply voltage Vds.
• HV transistors high Vth transistors
• NV transistors enieder- Vth transistors
• the exemplary embodiments shown represent schematic example circuits which have been checked on the basis of simulations, the storage circuit parts and the combinatorial circuit parts each being referred to collectively as block circuits which are connected to local supply voltage lines VDDL and / or VSSL.
• All the transistors in these storing and combinatorial circuit parts combined to form the block mentioned have a low threshold voltage of IowVthn, IowVthp ⁇ 0.25 volts for MOS or PMOS transistors.
• HV transistors with the threshold voltages highVthn, highVthp ⁇ 0.5 volts are used for the switching transistors.
• the active phase extends to 0.5 ⁇ s, after which a stand-by phase begins, which lasts up to 65 ⁇ s. This is followed by another active phase. 7
• the following connections are uniformly designated as follows:
• circuit block 2 storing circuit part
• a V-NMOS transistor MNH1 is connected in parallel to the HV-PMOS switching transistor gate MPl, the gate 19 of which is driven by the global supply voltage VDD.
• the NV transistor MNH1 thus represents a diode connected in parallel with the HV switching transistor MPl, consisting of an NV transistor MNH1 of opposite polarity.
• the transistor MP1 When the circuit arrangement is active, the transistor MP1 is conductive, the local supply voltage line VDDL is at the supply voltage VDD. If the transistor MPl is closed, the potential of VDDL drops in FIG. 1 due to the higher leakage currents of the NV transistors of the circuit parts 2 and 3 (FIG. IB).
• VDDL If the potential of VDDL reaches the value VDD - IowVthn *, the transistor MNH1 begins To conduct electricity. As a result, the potential VDDL is kept at this value, as a result of which the storing circuit parts 2 can hold their data.
• the value IowVthn * is the threshold voltage of the low voltage transistors which is increased by the substrate control effect, since the substrate is at a lower potential than the source node of the transistor M ⁇ H1.
• the transistors MPl and M ⁇ 1 are conductive, the potential lines VDDL and VSSL are at the potentials VDD and VSS. If the transistor MP1 is closed, the potential of VDDL drops due to the higher leakage current of the NV transistors of block 1 (FIG. 2B). If the potential of VDDL reaches the value VDD - IowVthn *, the transistor M ⁇ H1 begins to conduct current.
• the values IowVthn * and IowVthp * are the threshold voltages of the NV transistors which are increased due to the substrate control effect (well and substrate are at a higher or lower potential than the respective source nodes).
• the drain-source voltage for the closed transistors in the circuit parts 2 and 3 is reduced to significantly below VDD, which results in a lower leakage current.
• the effective threshold voltage of the NV transistors in block 1 is increased, since the substrate potential and the well potential remain at VSS and VDD, respectively. This corresponds, however, without an additional voltage source, a pretensioning of the substrate (back-biasing) and trough.
• the thereby increased threshold voltage leads to a further reduction in the leakage currents of the circuit parts 2 and 3, which is supplied by the voltage supply VDD. Using simulations, the leakage current was reduced to 1/15 compared to 1 volt.
• FIG. 3A shows a modified, third exemplary embodiment, in which only one (number word) HV switching transistor M ⁇ 1 with an NV transistor MPH1 connected in parallel as a diode is used in comparison with the second exemplary embodiment explained above.
• the advantage here is that the area requirement is halved due to the switching transistor M ⁇ 1 and the "diode transistor" MPH1 compared to the aforementioned embodiments.
• the threshold voltage increase due to the substrate control effect.
• the leakage currents are only reduced by the lower drain-source voltage. Using simulations, the leakage current was reduced to 1/10 compared to 1 volt.
• 3B shows the 10 course of VDDL and VSSL during a standby phase
• NV transistors of opposite polarity compared to the HV switching transistors connected as diodes are used. This leads to the lowering or raising of the potential of VDDL or VSSL by IowVthp * or IowVthn *, the higher threshold voltages of the NV transistors due to the substrate control effect.
• the potential of VDDL and VSSL is shifted by IowVthp and IowVthn, i.e. the operating voltages of the NV transistors with substrate and well potential of VSS or VDD (no substrate control effect with M ⁇ H1 and MPHl).
• 4B shows the course of VDDL and VSSL during a standby phase.
• the fifth exemplary embodiment according to FIG. 5A offers the following solution: This is achieved by connecting NV transistors connected in series as diodes (with the same polarity as the HV transistors) Potential of VDDL and VSSL shifted by the corresponding multiple of IowVthp and IowVthn, respectively.
• two ⁇ V transistors MPH1, MPH2 or M ⁇ H1 and M ⁇ H2 are connected in parallel to the switching transistors MPl and MN1.
• 5B again shows the course of VDDL and VSSL during a standby phase.

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• Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Computing Systems (AREA)
• General Engineering & Computer Science (AREA)
• Mathematical Physics (AREA)
• Logic Circuits (AREA)
• Semiconductor Integrated Circuits (AREA)
• Control Of Electrical Variables (AREA)
• Electronic Switches (AREA)

Applications Claiming Priority (3)

Publications (1)

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Family Applications (1)

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Citations (3)

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• 1998
  • 1998-03-16 DE DE19811353A patent/DE19811353C1/de not_active Expired - Fee Related
• 1999
  • 1999-03-11 KR KR1020007010235A patent/KR20010041927A/ko not_active Application Discontinuation
  • 1999-03-11 EP EP99919067A patent/EP1064726A1/de not_active Withdrawn
  • 1999-03-11 JP JP2000537311A patent/JP2002507852A/ja not_active Withdrawn
  • 1999-03-11 RU RU2000125907/09A patent/RU2000125907A/ru not_active Application Discontinuation
  • 1999-03-11 BR BR9909652-8A patent/BR9909652A/pt not_active IP Right Cessation
  • 1999-03-11 CN CN99806255A patent/CN1301430A/zh active Pending
  • 1999-03-11 WO PCT/DE1999/000677 patent/WO1999048208A1/de not_active Application Discontinuation

Patent Citations (3)

Non-Patent Citations (1)

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