WO2004075406A1

WO2004075406A1 - Leakage power control

Info

Publication number: WO2004075406A1
Application number: PCT/IB2004/050076
Authority: WO
Inventors: Hendricus J. M. Veendrick; Atul Katoch; Rinze I. M. P. Meijer
Original assignee: Koninklijke Philips Electronics, N.V.
Priority date: 2003-02-19
Filing date: 2004-02-05
Publication date: 2004-09-02

Abstract

An integrated circuit (200) comprising a core circuit (10) and a control circuit (28) coupled to the core circuit (10). The control circuit (28) is provided to control leakage currents produced by the core circuit (10) when it is an idle or standby mode for the purposes of conserving power, while ensuring that the logic state of the flip-flops or memory cells in the core circuit (10) maintain their state. The internal ground connection (24) is connected to an associated external ground connection (26) via two different paths (30, 32) depending upon the two different modes of the core circuit (10), i.e. normal or standby. The first path (30), which is operative only during normal mode, connects the internal and external rails (24, 26) with little or no voltage drop. The second path (32), which is operative only during standby mode, provides the same connection with a significant voltage drop. The internal bulk connection Vbb (14) of the core circuit (10) is connected directly to the external supply rail (26) at all times, so the switch from the first path (30) to the second path (32) causes a drop in the source-to-bulk voltage (Vsb) of the transistor(s) in the core circuit(10), which decreases the threshold voltage thereof and therefore decreases the leakage current.

Description

Leakage power control

This invention relates generally to leakage power control in electronic circuits and, more particularly, to the reduction of leakage currents during an idle or inactive state of an integrated circuit for the purpose of conserving power.

Many electronic circuits in many different fields employ Complementary Metal Oxide Semiconductor (CMOS) processes, in which both enhancement-mode n-channel MOS (NMOS) and enhancement-mode p- ode MOS (PMOS) transistors are used. It is very well known that the junction current which flows in such devices under reverse-bias conditions is generally called the "leakage current" and occurs when the device is in an idle or inactive state (i.e. when no switching activity occurs and no DC bias current is present).

Over the years, sub-micron CMOS processes have been developed and, as the sub-micron features become finer (i.e. the line widths and process features become smaller), so the transistor voltages are reduced accordingly. Particularly in battery-powered applications, such as in portable devices including mobile telephones, personal digital assistants, electronic games, etc., the CMOS process features are scaled down and the power supply levels are collapsed to lower and lower voltages, so that the batteries last longer. For lower supply voltages, the threshold voltages of the transistors are also reduced (as stated above) to make the process faster. However, for every lOOmV reduction in the threshold voltage, the leakage current of each respective device increases by a factor of around 10 - 15. These leakage currents are cumulative, thereby resulting in very high cumulative leakage current in, for example, a very large scale integrated (VLSI) circuit when it is an idle or inactive state.

As stated above, as the threshold voltage is lowered, the leakage current increases such that the power consumed by the electronic circuit incorporating the transistor increases. It will be appreciated, therefore, that the level of leakage current in a circuit which is in idle or "standby" mode is a critical, if not the most critical, factor in determining battery life, and it is highly desirable to minimize such leakage currents to the greatest extent possible. Several different methods have been proposed in the past for reducing leakage current when an integrated circuit or part of an integrated circuit goes into standby mode. For example, referring to Figure 1 of the drawings, the circuit 100 comprising the logic or memory core of the device includes a number of transistors having a relatively low threshold voltage, such that, when the core is enabled (i.e. in active mode), the required running speed can be achieved. It will be appreciated that the leakage current is of little consequence when the core is active. A decoupling capacitor 102 is provided to supply charge during peak currents. Both the core 100 and the capacitor 102 are connected between the upper supply rail Vdd 101 and and internal lower supply rail IV_SS 103. It will be appreciated that, on its own, the low threshold voltage transistors in the circuit 100 would produce a relatively very large subthreshold leakage current during standby mode. Thus, a high threshold transistor 104 is provided, between the internal lower supply rail 103 and an external lower supply rail EVss 105, which transistor 104 is on when the circuit 100 is in active mode and is required to pull the internal ground IVss down to the external ground EVss with little voltage drop. This transistor 104 is switched off when the circuit 100 enters the standby mode. Thus, the internal lower supply (or ground) IVss is maintained at a level above the external ground EVss by roughly the threshold voltage Vt of the transistor 104, thereby increasing the source-to-bulk voltage Vsb of the transistors in the circuit 100 and increasing the threshold voltage thereof accordingly (as explained below), such that the leakage current produced thereby is significantly reduced.

There are three main disadvantages associated with this technique. The first is the requirement for at least two low threshold voltage transistors in the core circuit 100 to achieve the required result, which transistors require significantly high fabrication technology. The second is that, in order to ensure that the high threshold voltage transistor 104 has a suitably low voltage drop across it when the core is active, it must be relatively large in size, which is obviously disadvantageous in an application where minimization of size is of importance. The third disadvantage is that all flip-flops in the logic core 100 (or memory cells in a memory core 100) lose their state when the circuit enters standby mode, which is not acceptable in many applications. US Patent No. 6166985 describes an integrated circuit including a core circuit and a control circuit coupled to the core circuit. The control circuit reduces leakage current in the core circuit when the core circuit is in a Sleep mode, and maintains a logic state of the core circuit when the core circuit is in a Drowsy mode. During Sleep mode, the control circuit acts to bring the core circuit to its lowest possible state of leakage current. The circuit is actively biased at the upper supply rail voltage Vdd, as opposed to bringing the Vdd power supply to ground potential externally. During Drowsy mode, the control circuit acts to provide enough current to ensure that the memory elements of the core circuit retain their stored logical state, without consuming the power otherwise consumed during "Idle" or "Active" operation. To overcome the effect of the high amount of leakage power dissipated from the core circuit when it is not in its Idle or Active state, the source-to-bulk voltage V^ is adjusted to a voltage value that causes the threshold voltage V, of the OFF MOSFET of the core circuit to significantly increase. This is achieved by reverse-biasing the bulk-to-source junction. An increase in V_Sb also causes an increase in V_< because V< varies with the square root of (2φ₄- + _sb) where φ₄. is the Fermi level. An increase in V_< effects a decrease of the leakage current, as explained earlier, such that in the Sleep mode, the leakage current is decreased.

However, a significant disadvantage of this technique is that it is required to generate an additional reverse-bias (or "backbias") voltage, which must be switched on and off when going from active in to Sleep (or Drowsy) mode, and vice versa. Furthermore, it is necessary to actively switch the operation of the circuit from Idle to Sleep or Drowsy mode as required - it does not occur automatically.

We have now devised an arrangement which overcomes the problems outlined above.

In accordance with the present invention, there is provided an integrated circuit comprising a core circuit including at least one transistor, said core circuit being operative in one of at least an active and a standby mode, a control circuit coupled to the core circuit for controlling leakage current produced by said core circuit when it is in said standby mode, at least one internal supply rail and corresponding external supply rail, said core circuit being connected to said internal supply rail, a first connection path between said internal and external supply rails, said first connection path being arranged to be operative only when said core circuit is in said active mode to provide little or no voltage drop between said internal and external supply rails, a second connection path between said internal and external supply rails, said second connection path being connected in parallel with said first connection path and being arranged to be operative only when said core circuit is in said standby mode, and a bulk bias connection providing a third connection path between said core circuit and said external supply rail which is arranged to be operative irrespective of which mode said core circuit is in; characterized in that said second connection path is arranged, when said core circuit enters said standby mode, to automatically provide and maintain a voltage drop between said internal and external supply rails, which voltage drop results in a drain-to- source voltage in the transistor of said core circuit which is lower than that during said active mode but which is sufficient to retain the logic state of said core circuit during said standby mode.

Also in accordance with the present invention, there is provided a method of controlling leakage current produced by a core circuit of an integrated circuit when it is in a standby mode, said core circuit including at least one transistor, the method comprising the steps of providing a control circuit coupled to said core circuit, connecting said control circuit to an internal supply rail, providing a first connection path between said internal supply rail and a corresponding external supply rail, said first connection path being arranged to be operative only when said core circuit is in an active mode to provide little or no voltage drop between said internal and external supply rails, providing a second connection path between said internal and external supply rails, said second connection path being connected in parallel with said first connection path and being arranged to be operative only when said core circuit is in said standby mode, and providing a bulk bias connection comprising a third connection path between said core circuit and said external supply rail which is arranged to be operative irrespective of which mode said core circuit is in; characterized in that said second connection path is arranged, when said core circuit enters said standby mode, to automatically provide and maintain a voltage drop between said internal and external supply rails, which voltage drop results in a drain-to-source voltage in the transistor of said core circuit which is lower than that during said active mode but which is sufficient to retain the logic state of said core circuit during said standby mode. Thus, in operation, because the bulk bias connection is always connected in the same configuration to the external supply rail, the backbias voltage supplied to the core circuit is substantially the same, irrespective of the mode in which the core circuit is operating. When the core circuit is in active mode, the first connection path is operative to connect the internal supply rail to the external supply rail, with little or no voltage drop. When the core circuit enters the standby mode, the second connection path automatically becomes operative (and the first connection path becomes inoperative) to provide a relatively significant voltage drop between the internal and external supply rails, thereby increasing the source to bulk voltage supplied to the transistor(s) in the core circuit and increasing the respective threshold voltage(s), which results in a corresponding decrease in leakage current. This voltage drop is provided automatically when the core circuit enters the standby mode because the first connection path becomes inoperative and the second connection path becomes operative automatically when the core circuit enters the standby mode, so as to reduce the leakage current to an acceptable level while maintaining the logic state of the core circuit throughout the time the core circuit is in the standby mode, without the need to generate an additional backbias current, as is required in the arrangement of US Patent No. 6,166,985.

The internal and external supply rails may comprise internal and external lower supply rails and/or internal and external upper supply rails respectively. The first communication path preferably comprises switching means, beneficially in the form of one or more transistors (beneficially an n-channel MOS transistor, preferably having a relatively low threshold voltage), for switching said communication path between the operative and inoperative state. The second communication path beneficially includes at least two transistors (beneficially p-channel MOS transistors, again, preferably having a relatively low threshold voltage) connected in series with each other. The one or more of the transistors of the second communication path are preferably diode-connected.

The circuit may also include a decoupling capacitor or the like to supply charge during peak currents.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment described hereinafter.

An embodiment of the present invention will now be described by way of example only and with reference to the accompanying drawings, in which: Figure 1 is a schematic circuit diagram illustrating a method of leakage power control in accordance with the prior art; and

Figure 2 is a schematic circuit diagram illustrating an apparatus for, and method of, leakage power control in accordance with an exemplary embodiment of the present invention.

Referring to Figure 2 of the drawings, an integrated circuit 200 according to an exemplary embodiment of the present invention comprises an upper supply rail (Vdd) 22. The circuit 200 further comprises a lower supply rail comprising an Internal ground (IVss) 24 and an external ground (EVss) 26.

A logic memory core 10 including a low threshold voltage (low-Vt) transistor is connected between the upper supply rail Vdd and the internal ground IVss. A decoupling capacitor 12 is connected in parallel to the logic memory core 10 between the upper supply rail Vdd and the internal ground IVss. An internal bulk connection (Vbb) 14 is provided between the logic memory core transistor and the external ground EVss.

In order to provide the leakage power control required, a low-Vt nMOS (enable) transistor 16 is connected between the internal ground IVss and the external ground EVss. A plurality of low-Vt pMOS transistors 18, 20 (in this exemplary embodiment, two) are connected together in series and the series arrangement is connected in parallel to the low-Vt nMOS transistor 16 between the internal ground IVss and the external ground. As shown in Figure 2, the low-Vt pMOS transistors 18, 20 are both connected or configured as diodes. In operation, when the logic memory core 10 is active, the nMOS transistor 16 is on, thereby providing the connection path between the internal ground IVss and the external ground EVss. The transistor 16 has a large aspect ratio (W/L) and should be made relatively wide since it is required to maintain its drain-source voltage drop as low as possible during normal operation (thereby pulling down the internal Vss without too much voltage drop). It will be appreciated by a person skilled in the art that the leakage current through transistor 16 is negligible during normal (active) operation. As in the above-described prior art, the decoupling capacitor 14 is used to supply charge during peak currents.

During standby mode, i.e. when no switching activity occurs and no DC bias current is present, the transistor 16 is switched off, such that the series connected transistors 18, 20 provide the connection path between IVss and EVss. Accordingly, the voltage drop across the transistors 18, 20 (which is approximately equal to the cumulative threshold voltages of the transistors 18, 20) represents the level at which IVss is kept thereby above EVss. Thus, in this case, the series connection of the pMOS transistors 18, 20 keeps the internal Vss roughly at 2Vt above ground (EVss). This has the effect of increasing the source voltage Vs of the transistor in the logic memory core 10 during standby mode compared to that during the active mode.

Since the internal bulk connection Vbb (also known as substrate or backbias voltage) is connected directly to EVss there is little or no change in this voltage between active and standby mode of the logic memory core 10. Thus, the overall effect of the transistors 18, 20 in standby mode is to automatically effect an increase in Vsb of the transistor in the logic memory core, thereby causing an increase in its threshold voltage Vt (as explained above) and a resultant decrease in leakage current. In other words, the diode- connected transistors 18, 20 act so as to automatically increase the backbias of the transistor(s) in the memory logic core 10 when the core 10 enters standby mode (and transistor 16 is switched off), thereby reducing leakage current.

It will be appreciated that the level of leakage current reduction is dependent on the number of series transistors 18, 20 employed. It will further be appreciated that such transistors can be relatively small because they are only required to carry the leakage current of the core during standby.

In summary, the embodiment described above acts to switch the internal ground connection of an integrated circuit to an external ground connection via two different paths depending upon the two different modes of operation (normal and standby) of operation of the integrated circuit. During normal operation, the internal ground connection is connected to the external ground connection via a first transistor which pulls the internal ground connection down to external ground with little voltage drop. During standby, the first transistor is switched off and the internal ground is connected to the external ground via a set of diode connected, series transistors which act to maintain the internal ground at some level above external ground. Because the internal backbias voltage remains substantially the same in both modes (because the internal bulk connection is connected directly to the external ground), this has the effect of raising Vsb of the transistor of the logic memory core 10, thereby increasing its threshold voltage Vt and decreasing the leakage current. When normal operation is resumed, the first transistor is switched on and again provides the path between the internal ground connection of the integrated circuit and the external ground connection. There are several advantages of the above-described embodiment of the present invention compared to conventional techniques, including:

1) no backbias generator is required to generate an additional substrate (or well) voltage;

2) in standby mode, the flip-flops in the core will not lose their state (the level of leakage current reduction can be controlled by the number of diode-connected transistors connected in series, as explained above, according to the level of current required to maintain this state);

3) since the supply is not completely switched off, the intrinsic core capacitance between Vdd and internal Vss, as well as a possible added decoupling capacitance in the core, are not completely discharged, meaning that the current peaks, when going from active to standby mode and back are much less than would be the case where Vss is switched off;

4) Faster switching is enabled between standby and active mode; - 5) No requirement for high Vt transistor fabrication.

An embodiment of the present invention has been described above by way of example only with reference to the accompanying drawings, and it will be appreciated by a person skilled in the art that modifications and variations could be made to the described embodiment without departing from the scope of the invention as defined in the appended claims.

For example, the above-described technique could also be employed to implement complementary switching between internal and external upper supply rails (IVdd/Evdd), either instead of or as well as the complementary switching described above between internal and external ground. It will be further appreciated that the terai "comprising" does not exclude other elements or steps, that "a" or "an" does not preclude a plurality, and that a single element or unit may be used to fulfil the functions of several means or elements recited in the description or claims.

Claims

CLAIMS:

1. An integrated circuit comprising a core circuit including at least one transistor, said core circuit being operative in one of at least an active and a standby mode, a control circuit coupled to the core circuit for controlling leakage current produced by said core circuit when it is in said standby mode, at least one internal supply rail and corresponding external supply rail, said core circuit being connected to said internal supply rail, a first connection path between said internal and external supply rails, said first connection path being arranged to be operative only when said core circuit is in said active mode to provide little or no voltage drop between said internal and external supply rails, a second connection path between said internal and external supply rails, said second connection path being connected in parallel with said first connection path and being arranged to be operative only when said core circuit is in said standby mode and a bulk bias connection providing a third connection path between said core circuit and said external supply rail which is arranged to be operative irrespective of which mode said core circuit is in; characterized in that said second connection path is arranged, when said core circuit enters said standby mode, to automatically provide and maintain a voltage drop between said internal and external supply rails, which voltage drop results in a drain-to-source voltage in the transistor of said core circuit which is lower than that during said active mode but which is sufficient to retain the logic state of said core circuit during said standby mode.

2. An integrated circuit according to claim 1, wherein said internal and external supply rails may comprise internal and external lower supply rails and/or internal and external upper supply rails respectively.

3. An integrated circuit according to claim 1 or claim 2, wherein the first communication path comprises switching means for switching said communication path between the operative and inoperative state.

4. An integrated circuit according to claim 3, wherein said switching means comprises one or more transistors (16).

5. An integrated circuit according to claim 4, wherein said one or more transistors have a relatively low threshold voltage.

6. An integrated circuit according to claim 4 or claim 5, wherein said one or more transistors comprise n-channel MOS transistors.

7. An integrated circuit according to any one of the preceding claims, wherein the second communication path includes at least two transistors connected in series with each other.

8. An integrated circuit according to claim 7, wherein one or more of the transistors of the second communication path are diode-connected.

9. An integrated circuit according to claim 7 or claim 8, wherein one or more of the transistors of the second communication path are p-channel MOS transistors.

10. An integrated circuit according to any one of claims 7 to 10, wherein one or more of the transistors of the second communication path have a relatively low threshold voltage.

11. An integrated circuit according to any one of the preceding claims, including means to supply charge during peak currents.

12. An integrated circuit according to claim 11, wherein said means to supply charge during peak currents comprises a decoupling capacitor.

13. A method of controlling leakage current produced by a core circuit of an integrated circuit when it is in a standby mode, said core circuit including at least one transistor, the method comprising the steps of providing a control circuit coupled to said core circuit, connecting said control circuit to an internal supply rail, providing a first connection path between said internal supply rail and a corresponding external supply rail, said first connection path being arranged to be operative only when said core circuit is in an active mode to provide little or no voltage drop between said internal and external supply rails, providing a second connection path between said internal and external supply rails, said second connection path being connected in parallel with said first connection path and being arranged to be operative only when said core circuit is in said standby mode and providing a bulk bias connection comprising a third connection path between said core circuit and said external supply rail which is arranged to be operative irrespective of which mode said core circuit is in; characterized in that said second connection path is arranged, when said core circuit enters said standby mode, to automatically provide and maintain a voltage drop between said internal and external supply rails, which voltage drop results in a drain-to- source voltage in the transistor of said core circuit which is lower than that during said active mode but which is sufficient to retain the logic state of said core circuit during said standby mode.