WO2003009300A1

WO2003009300A1 - Integrated circuit and battery powered device

Info

Publication number: WO2003009300A1
Application number: PCT/IB2002/002605
Authority: WO
Inventors: Hendricus J. M. Veendrick; Jean Wieling; Martinus J. Coenen; Rinze I. M. P. Meijer; Kiran B. R. Rao
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2001-07-16
Filing date: 2002-06-26
Publication date: 2003-01-30

Abstract

The integrated circuit (100) has at least a single circuit portion (120), to which the power supply can be controlled by control circuitry (180). The control circuitry can be used for gradual on/off switching of the circuit portion (120), which prevents the occurrence of potentially damaging high peak currents on circuit start-up. The first step of the gradual on/off switching involves the enabling/disabling of a first high threshold-voltage transistor (140a), which couples external power line (110) to internal power line (112), by means of a control signal provided by control circuitry (180), which switches on/off a first part of the power to circuit portion (120). This control signal is also fed to a delay element (182). After a certain delay, delay element (182) enables/disables a second high threshold-voltage transistor (140b), arranged in parallel with the first high threshold-voltage transistor (140a), in a second step. This switches on/off a second part of the power to circuit portion (120). Alternatively, the control circuitry (180) can be used to control the power supply to the circuit portion (120) during active mode.

Description

Integrated circuit and battery powered device

The invention relates to an integrated circuit comprising: an external power for providing a supply current to the integrated circuit; an internal power line; a further power line; a circuit portion coupled to the internal power line and the further power line; control circuitry for generating a first control signal; coupling means coupled to the control circuitry for coupling the external power line to the internal power line.

The invention further relates to a battery-powered device comprising such an integrated circuit.

In the art of IC design, the ongoing downscaling of transistor dimensions allows for an increase of the transistor density on an IC, which enables the development of increasingly complex ICs. However, the increase in transistor density also introduces significant complications. Apart from the increase of noise, cross talk and numerous design technology pitfalls, to name but a few problems, these very large-scale integrated (VLSI) circuits also consume large amounts of power during operation. In addition, with the reduction of transistor dimensions and supply voltage, the threshold- voltage of these transistors is usually lowered as well, to enable high-frequency switching of the transistors. This causes an increase in the leakage currents for these transistors, which adds to the total power consumption of the circuit and to the standby current in particular. This especially causes problems in terms of battery lifetime for battery-powered devices that include such circuitry, like hand-held devices, lap top computers, mobile phones, portable CD players and so on. Therefore, low-power consumption is an important issue in the design of the ICs, particularly when these ICs are being used in such devices.

IEEE Journal of Solid State Circuits, Vol. 32 (1); p. 52-61, 1997 discloses a complementary metal oxide semiconductor (CMOS) circuit, which has a low-power design by the presence of coupling means coupled to the control circuitry for coupling the external power line to the internal power line, in which the coupling means consists of a high threshold-voltage (high-Nτ) pMOS transistor between the external supply line (Ndd, ext) and the internal supply line (Ndd, i_nt) of the circuit. The high-Nτ transistor is controlled by an enable/disable control signal from control circuitry, thus enabling/disabling the current supply to the circuit portion. By switching off large parts of an IC, for instance during standby mode of an e.g. battery-powered device, a significant saving of consumed power is achieved, resulting in increased battery lifetime. For such applications, the use of ahigh-Nχ transistor is of the essence, because it reduces the leakage currents from the circuit portion in stand-by mode by one or two decades. However, the internal charges of the circuit portion in stand-by mode still leak away, and need to be restored when switching the portion on again. A complicating matter is that switching on the circuit portion can induce a large peak current surge, especially when the circuit portion is large. This is an unwanted effect, not only because the power supply might have insufficient capacity to deal with this power flux, which can lead to voltage drops over the external power lines threatening the modus operandi of the IC, but also because such surges can introduce large thermal effects in and around the power lines. When large enough, the latter effect can cause irreversible damage to the IC. In addition, large power surges cause supply noise and large electromagnetic fluxes, again threatening the modus operandi of the circuit. Unfortunately, the occurrence of such effects is a realistic prospect, because the current design methods are more and more based on the reuse of large, predesigned functional blocks like the so-called intellectual property (IP), memory, digital signal processing (DSP) cores and so on, which have become large enough to introduce such problems when being switched on.

It is a disadvantage of the known CMOS IC that such high currents can occur, thus jeopardizing the integrity of the circuit.

It is a first object of the present invention to provide an IC of the kind described in the opening paragraph that avoids the occurrence of large current peaks when powering up the circuit portion. It is a second object of the present invention to provide a battery-powered device of the kind described in the opening paragraph with an extended battery lifetime and safe power-up of parts of the battery powered device.

Now, the first object of the invention is realized in that the control circuitry is arranged to generate a further control signal; and said coupling means comprise: first means for providing a first portion of the supply current to the internal power line in response to the first control signal; and second means for providing a second portion of the supply current to the internal power line in response to the second control signal. By using a plurality of coupling elements instead of the single high-Nr transistor of the prior art, a larger flexibility in the power control of the circuit portion is obtained. For instance, the circuit portion can be powered-up in a stepwise fashion, causing the start-up or switch-off of the circuit portion to be distributed over longer time intervals. As a result, the power flux to the circuit portion is drastically reduced, causing the demands on the capacity of the power supply to become much more modest, and the thermal effects in the IC substrate to become a lesser threat to the circuit integrity.

In an embodiment of the present invention, the control circuitry comprises a delay element for generating the second control signal a selected time delay after the control signal has been generated. The introduction of the time delay between the generation of the control signal and the second control signal by means of a delay element has the advantage that the power-up and power-down speed of the circuit portion can be tuned by choosing an appropriate time delay to be implemented by the delay element.

It is an advantage if the circuit further comprises a decoupling capacitor coupled to the internal power line and the further power line. The presence of a decoupling capacitor further minimizes transient voltage drops caused by the power-up of the circuit portion by providing additional capacity during power-up, thus contributing to an enhanced stability of the circuit.

It is another advantage if the delay element comprises a flip flop responsive to a clock signal. This embodiment facilitates synchronously delayed on/off switching of a circuit portion. A flip flop is a commonly used logic cell in IC design to introduce controlled delay in a circuit. The flip flop can pass the control signal on to the next means that switches on/off a next portion of the supply current, like e.g. a high-Nr transistor, when triggered by a clock pulse, which results in a clock-controlled delay of a positive number of clock ticks between each portion of the supply current being switched on/off. It is yet another advantage if the delay element comprises a delay chain comprising a plurality of inverters. Inverter chains are well-known delay elements in IC design capable of introducing an asynchronous delay. In the context of the circuit of the present invention, the application of an inverter chain is useful when the interval between two clock pulses largely extends the required delay time. In addition, inverter chains are very small and no additional control circuitry like clock lines etcetera is required, making it a cheap alternative for the aforementioned flip flop.

Favorably, said first means and said second means are pMOS transistors, the external power line is an external supply voltage line, the internal power line is an internal supply voltage line and the further power line is a ground voltage line. Nowadays, many ICs are CMOS devices, which may or may not operate under so-called dual-Nr conditions, in which the supply voltage differs from the voltage applied internally. In such circuits, the external voltage is transformed to the internal voltage one way or another. An attractive solution to on/off switch a circuit portion of an IC is to disconnect it from the external supply power grid. Therefore, in CMOS technology, the pMOS transistors are placed between the external and internal supply voltage line, and switching on the transistors one-by-one powers up the circuit portion they are attached to in a stepwise fashion by the gradual reduction of the overall resistance of the parallelly arranged transistors.

Alternatively, said first means and said second means are nMOS transistors, the external power line is an external ground voltage line, the internal power line is an internal ground voltage line and the further power line is a supply voltage line. Due to the complementary nature of CMOS technology, the previous embodiment can also be equivalently realized in the complementary part of the CMOS, i.e. without altering its overall functional behavior. It is a further advantage if the further power line is an internal ground voltage line, said integrated circuit further comprising: an external ground voltage line; further coupling means coupling the external ground voltage line to the further power line. Although this slightly increases the area required for the implementation of the invention, it provides a useful alternative solution to the problem of power surges in the on/off switching of circuit portions by the introduction of additional on/off switching steps. Switching off the transistors in between both sets of power lines isolates the circuit portion from the external power lines, which further reduces the number of channels along which leakage current from the circuit portion can take place, thus increasing the lifetime of the charges stored in the circuit portion.

It is yet another advantage if the control circuitry is arranged to generate a third control signal; and said further coupling means are coupled to the control circuitry, said further coupling means comprising: third means for providing a first portion of a further supply current to the further power line in response to the first control signal; and fourth means for providing a second portion of a further supply current to the further power line in response to the third control signal. The introduction of additional power control means like gradual on/off switching facilities provides a more fine-grained control of the power flow to and from the circuit portion. In case of power control during power-up and/or power-down of the circuit portion, this has the result that the power fluxes that occur during start-up of the circuit portion can be further minimized, thus further increasing safety and stability of the integrated circuit. It is advantageous if the control circuitry comprises a further delay element for generating the third control signal a selected time delay after the second control signal has been generated.

This provides a more fine-grained control over the power-up/power-down of the circuit portion, because the delay times of both the delay element and the further delay element can be individually chosen.

It is yet a further advantage if the integrated circuit further comprises: further control circuitry for generating a first further control signal; said further coupling means being coupled to said further control circuitry, said further coupling means comprising: third means for providing a first portion of a further supply current to the further power line in response to the further control signal; a further delay element for generating a second further control signal a selected time delay after the first further control signal has been generated and fourth means for providing a second portion of a further supply current to the further power line in response to the second further control signal

Decoupling the control signals to the two sets of transistors coupling the internal and external power lines introduces individual control over each transistor. This provides an even finer- grained power control over the circuit portion, which for instance can be used to minimize the occurring power fluxes during power-up of the circuit portion even further. In an alternative embodiment of the present invention, the control circuitry comprises: a first data storage element for generating the first control signal based on a data value stored in the first data storage element; and a second data storage element for generating the second control signal based on a data value stored in the second data storage element.

This has the advantage that the power supply to the circuit portion can also be regulated during the active mode of the circuit portion. By loading appropriate data values in the data storage elements, the power flow to the circuit portion can be tuned, which enables the reduction of power consumption in active mode. This is particularly suitable for a circuit portion with internal clock signal generation, because the tuning of the supply voltage is then directly related to the tuning of the clock frequency of the circuit portion. The appropriate data values can be provided at run-time by means of suitable software, thus providing run- time power management.

It is an advantage if the first data storage element and the second data storage element form at least a part of a data register.

This provides a simple and cheap implementation of control circuitry for controlling the power consumption of the IC during active mode.

Now, the second object of the invention is realized in that the integrated circuit comprises: an external power line coupled to the power line for further providing the supply current to the integrated circuit; an internal power line; a further power line; a circuit portion coupled to the internal power line and the further power line; control circuitry for generating a first control signal and a second control signal; coupling means coupled to the control circuitry for coupling the external power line to the internal power line, said coupling means comprising: first means for providing a first portion of the supply current to the internal power line in response to the first control signal; second means for providing a second portion of the supply current to the internal power line in response to the second control signal.

An important quality of battery powered devices is the length of the operational period; this is the period in which the device will function without having to recharge the batteries. Obviously, an increase of the operational period of such a device strengthens its market position. Battery powered devices utilizing an IC according to the invention can provide longer operational times due to the fact that large parts of the IC can be safely switched on/off without the risk of causing damage to the device as a result of excessive power fluxes. In addition, a more gradual on/off switching of circuit portions reduces the magnitude of induced magnetic fields. This reduces the formation of signal noise, providing a better signal- to-noise ration for such devices. The latter is especially important for wireless telecommunication devices like mobile phones. Also, due to the fact that the power peaks associated with the on/off switching of parts of the device become less pronounced, requirements for the power supply of such devices become less demanding as well. Furthermore, the IC according to the invention allows for longer operational times of the device by means of power consumption reduction in the active mode of the circuit. Therefore, integration of an IC according to the invention in a battery-powered device yields advantages to that device beyond the mere use of such an IC.

It is an advantage if the control circuitry comprises a delay element for generating the second control signal a selected time delay after the control signal has been generated.

Such an arrangement is particularly useful for extending the battery lifetime during stand-by periods of the electronic device.

It is another advantage if the control circuitry comprises: a first data storage element for generating the first control signal based on a data value stored in the first data storage element; and a second data storage element for generating the second control signal based on a data value stored in the second data storage element. Such an arrangement is particularly useful for extending the battery lifetime during active periods of the electronic device.

The integrated circuit and device according to the invention are described in more detail and by way of non-limiting examples with reference to the accompanying drawings, wherein:

Fig. 1 shows a circuit with an on/off switching facility according to an embodiment of the invention; Fig. 2 shows a circuit with another on/off switching facility according to another embodiment of the invention;

Fig. 3 shows a circuit with yet another on/off switching facility according to yet another embodiment of the invention; Fig. 4 shows a circuit with yet another on/off switching facility according to yet another embodiment of the invention;

Fig. 5 shows another circuit with yet another on/off switching facility according to yet another embodiment of the invention;

Fig. 6 shows an alternative embodiment of the invention; and Fig. 7 shows a battery-powered device with an integrated circuit according to the invention.

In Fig. 1, circuit portion 120 of integrated circuit 100 is powered through internal power line 112 and further power line 130. Internal power line 112 is coupled to external power line 110 through transistor 140a and transistor 140b. It is emphasized that transistors 140a and 140b can readily be replaced by equivalent switching elements like for instance an ideal switch, e.g. a thyristor, in series with a resistor, or by a combination of equivalent switching elements. Transistor 140a and transistor 140b can be switched on/off separately to provide gradual on/off switching of circuit portion 120 in order to prevent the occurrence of power surges. A first control signal provided by control circuitry 180 can switch transistor 140a to a conductive state. This switches on a first part of the power supply to circuit portion 120. Simultaneously, the first control signal is also fed to a delay element 182. In Fig. 1, delay element 182 comprises a flip flop responsive to a clock signal provided by clock line 160. Now, after a delay of about one clock cycle, delay element 182 generates a second control signal, which switches transistor 140b to a conductive state causing the overall resistance between external power line 110 and internal power line 112 through transistors 140a and 140b to be reduced. Consequently, a second portion of the power supply to circuit portion 120 is switched on. This way, a stepwise increase of the power supply to the circuit portion 120 is provided and the occurrence of unwanted power surges in the integrated circuit is avoided. In this particular embodiment of integrated circuit 100, external power line 110 is the external N_dd-hne, whereas the further power line 130 is the N_ss-line. External power line 110 is coupled to internal power line 112, which is the internal Vdd-lme, and the supply voltage is fed to the internal power line 112 through the parallelly arranged transistor 140a and transistor 140b. When integrated circuit 100 is a CMOS circuit, transistor 140a and transistor 140b can be high-Nr pMOS transistors. It should be obvious to anyone moderately skilled in the art that equivalent implementations of transistor 140a and transistor 140b can easily be applied for other technologies as well, e.g. bipolar technology, without departing from the scope of the invention. In addition, a number of obvious variations and extensions to this and the other embodiments can be realized. For instance, a plurality of flip flops can also be used as delay element 182 to increase the delay between transistor 140a and transistor 140b, in cases where a delay of about a single clock cycle is too small to avoid large power surges. Another important advantage of using high-Nr pMOS transistors as transistor 140a and transistor 140b is that they may exhibit more modest dimensions than the single high-Nτ transistor used in the aforementioned embodiment of the circuit from IEEE Journal of Solid State Circuits, Vol. 32 (1); p. 52-61, 1997. As a result, they exhibit smaller capacitances than the single high-Nτ transistor from the aforementioned known embodiment, which leads to shorter response times for the individual high-Nτ transistors in the embodiment of the circuit of the present invention. Additionally, it is stipulated that a more fine-grained on/off switching arrangement can be achieved in this and the other embodiments of the invention by adding more switching elements in parallel with transistors 140a and 140b under control of additional delay elements like delay element 182. For instance, a third transistor being responsive to a second delay element can be added, resulting in a further extension of the on/off switching circuitry. This can be extended even further, if system requirements demand this, without departing from the teachings of the present invention.

Optionally, a decoupling capacitor 122 coupled to the internal power line 112 and the further power line 130 can be added to compensate for transient supply voltage drops as a result of the peak currents on power-up of circuit portion 120. Such a capacitor 122 is useful, because during stand-by the charges stored in the low-Nχ transistors of circuit portion 120 leak away. It is emphasized that because of the gradual nature of the power-up, this capacitor 122 not necessarily has to have the same capacitance as the capacitor used in the aforementioned embodiment from the prior art. Furthermore, the presence of decoupling capacitor 122 is not crucial to the embodiments according to the invention and it can therefore be omitted without departing from the scope of the invention, as indicated by its representation by dashed lines in the various figures.

In Fig. 2, the embodiment of the invention shown in Fig. 1 and described in the previous paragraph is modified in the following manner. Delay element 182 now comprises a chain of inverters. The advantage of using a self-timed delay element 182 like an inverter chain is that a clock signal is not required. Therefore, clock line 160 is absent in this embodiment, thus reducing the required area for this particular gradual on/off switching arrangement. The propagation of the control signal along control circuitry 180 can be tuned by variation of the length of the inverter chain in delay element 182. This can be realized by using standard design techniques. The use of self-timed delay elements is, for instance, particularly useful in applications where the gradual on/off switching can be completed within a single clock cycle. In such cases, flip flops would introduce longer delays than necessary, thus introducing latencies in the on/off switching of circuit portion 120. In addition, a self-timed delay element 182 can easily be integrated in asynchronous circuits, which is another advantage of this embodiment.

The complementary nature of certain types of circuitry like CMOS circuits also allows the realization of on/off switching arrangements in its complementary part. Integrated circuit 100, as shown in Fig. 3, comprises a transistor 142a being a nMOS high-N_T transistor. Transistor 142a couples external power line 230 being the external ground voltage line with the internal power line 232 being the internal ground voltage line. Circuit portion 120 is further connected to further power line 210, being the external supply voltage line. Similar to the embodiment depicted in Fig.l, by switching transistor 142a to a conductive state a first portion of the current starts flowing from circuit portion 120 to external power line 230. Transistor 142b is also a nMOS high-Nτ transistor, being responsive to delay element 182, and is switched to a conductive state after a certain time delay governed by delay element 182. This enables the flow of a second portion of the current from circuit portion 120 to external power line 230. Obviously, this embodiment can also be modified or extended with other or further delay elements and other or further switching elements like further high-Nτ nMOS transistors without departing from the scope of the invention. A combination of the embodiments depicted in Fig. 1 and Fig. 3 is shown in

Fig. 4. In this embodiment, transistors 140a and 140b as well as further transistor 242a and, as an option, further transistor 242b are present. Transistors 140a and 140b couple the external power line 110 with the internal power line 112, whereas further transistor 242a and optional transistor 242b couple the further power line 332 with an external ground voltage line 330. In this particular arrangement, both transistor 140a as well as further transistor 242a are made responsive to control circuitry 180. Consequently, circuit portion 120 can be disconnected with a single control signal from both external power line 110 as well as from external ground power line 330. This has the advantage that the charges from circuit portion 120 will leak away more slowly during stand-by mode of the circuit portion 120, because of the reduced number of leakage pathways. This means that its power demand on start-up can be smaller, thus adding to the reduction of the unwanted peak currents during start-up. Optionally, the coupling of further power line 332 to external ground voltage line 330 through further transistor 242a can be extended with further transistor 242b and further delay element 282 coupled to control circuitry 180, wherein further transistor 242b can be switched to a conductive state by a third control signal generated by further delay element 282. This way, gradual on/off switching of circuit portion 120 can be controlled by gradually altering the resistance of both transistors 140a and 140b and further transistors 242a and 242b by stepwise on/off switching of transistors 140a and 242a in a first step, and transistor 140b and further transistor 242b after a certain delay. Transistor 140b and further transistor 242b can be either switched on/off simultaneously or separately, depending on system requirements. This can be achieved by respectively choosing delay element 182 similar to or different from further delay element 282. In a CMOS implementation of this particular embodiment of integrated circuit 100, transistors 140a and 140b are high-Nτ pMOS transistors coupling the external and internal supply voltage lines. Further transistors 242a and 242b are high-Nr nMOS transistors coupling the external and internal ground voltage lines. Delay element 182 comprises a flipflop responsive to clock line 160, whereas delay element 282 comprises a flip flop responsive to a further clock line 260. Clock line 160 and further clock line 260 can be used to transmit clock signals originating from the same clock as well as from different clocks. As mentioned previously, it should be obvious anyone moderately skilled in the art that several equivalent realizations of transistors 140a, 140b, 242a and 242b and delay elements 182 and 282 can be thought of without departing from the scope of the invention.

Fig. 5 depicts a modification of the integrated circuit 100 depicted in Fig. 4. In this modification, the further transistors 242a and 242b have been made responsive to a first further control signal generated by further control circuitry 280, whereas transistors 140a and 140b are still responsive to control signal generated by control circuitry 180, thus uncoupling the controllability of these two sets of transistors. For example, control circuitry 180 can be used to transmit a clock signal from a first clock, while further control circuitry 280 can be used to transmit a clock signal from a second clock. Delay element 282 now generates a second further control signal by delaying the first further control signal provided by control circuitry 280 rather than the control signal provided by control circuitry 180 in the previous embodiment. By using independent clocks, the control over the various switching elements, e.g. transistors 140a, 140b, 242a and 242b can be completely decoupled. In other words, each of these transistors can be switched on/off on an individual basis, thus providing a very fine- grained on/off switching arrangement. This is particularly advantageous when a high level of control over the gradual on/off switching of circuit portion 120 is required.

However, the teachings, of the present invention, e.g. the decoupled control of switches, e.g. transistors, between an external and an internal power line in order to provide enhanced control over the power flow to and from a circuit portion 120 can be extended to the control of power consumption of an IC during active mode. In Fig. 6, an embodiment of such an application is given. Fig. 6 is described in backreference to the previous Figs; corresponding reference numerals have similar meanings unless explicitly stated otherwise. In Fig. 6, the control circuitry 180 comprises a first data storage element 192 that is coupled to the control terminal of transistor 140a, and a second data storage element 194 that is coupled to the control terminal of transistor 140b. The first data storage element 192 is arranged to generate the first control signal based on a data value, e.g. a bit, stored in the first data storage element 192, and the second data storage element 194 is arranged to generate the second control signal based on a data value, e.g. a bit, stored in the second data storage element 194. First data storage element 192 and second data storage element 194 can be configured through communication circuitry 196, which can be a data communication bus, hard- wired connections to additional control circuitry not shown or other known interconnection means. The additional control circuitry not shown can be a part of control circuitry 180, but this is not necessary. First data storage element 192 and second data storage element 194 can be independent data storage elements, e.g. flip flops or parts from different memories, or can be part of a larger storage device, e.g. a control register 190.

The presence of transistors 140a, 140b ensures that the power consumption of the circuit portion 120 can be partitioned. In the previous embodiments, this has been used to provide a more gradual power-up and power-down of the integrated circuit portion 120. In this embodiment, it is used to regulate the power consumption of the integrated circuit portion 120 in its active mode. Depending on the value of the bits stored in respective data storage elements 192 and 194, transistors 140a, 140b are switched to either a conductive or a non-conductive state, thus regulating the effective supply voltage to circuit portion 120 by varying the effective transistor channel resistance between the external power line 110 and the internal power line 112. The respective bit values can for instance be based on a power consumption forecast for the circuit portion 120, and can be included in the software that has to be executed by the circuit portion 120. Each time that the execution of a new software module is initialized either by the circuit portion 120 or by a controller not shown, the bit values in first data storage element 192 and second data storage element 194 are being updated by the additional control circuitry not shown, thus providing a software-driven reconfigurable power supply for the circuit portion 120. Obviously, the bit patterns to be fed to the first data storage element 192 and the second data storage element 194 can also originate from hardware, e.g. a memory device not shown, coupled to communication circuitry 196, from which they are transferred to the first data storage element 192 and the second data storage element 194 under control of the additional control circuitry not shown.

It will be obvious to those skilled in the art that such a power consumption control arrangement is particularly advantageous for a circuit portion 120 having internal clock signal generation. With local clock signal generation, like for instance is the case in systems having globally asynchronous, locally synchronous (GALS) operational modes, the clock frequency of the circuit portion 120 scales proportionally with the supply voltage as regulated by transistors 140a, 140b under control of first data storage element 192 and second data storage element 194. Consequently, if a circuit portion 120 has to perform an operation for which its full computational power is not required, its supply voltage and corresponding clock frequency can be adapted, e.g. reduced to match the latency of the circuit portion 120 with the delivery deadline for the operation result. This matching reduces or even avoids the waste of clock cycles by the circuit portion 120, which contributes to an efficient power use by the circuit portion 120.

Although the embodiment of the invention shown in Fig. 6 has been depicted and described in analogy with Fig. 1 , it will be obvious to those skilled in the art that the teachings of the embodiment of the invention as depicted in Fig. 6 can also be applied to the implementations of integrated circuit 100 that are shown in Figs 2-5 and described in the corresponding parts of the detailed description. In other words, this particular embodiment of the invention is not limited to pMOS transistors located between an external and internal Ndd-line; the variations to such an arrangement as disclosed in Figs 1-5 and their detailed description are also applicable to the embodiment shown in Fig. 6.

In addition, it will be obvious to those skilled in the art that the control circuitry for controlling the power-up/power-down of the circuit portion 120, e.g. the control circuitry including the delay elements, can be easily combined with the control circuitry for controlling the power consumption of the IC portion 120 during active mode.

This can, for instance, be realized in a straightforward manner by placing switches between the control terminals of transistors 140a, 140b and the various parts of control circuitry 180, with the switches being responsive to a power-up/power-down control signal. Under control of this signal, the switches will switch the control of the transistors from the delay element 182 to the data storage elements 192, 194 after power-up has completed, or vice versa, before power-down will commence. Many alternative implementations combining the active mode and standby power consumption control arrangements can be thought of without departing from the teachings of the present invention.

Fig.7 is described in backreference to the previous Figs. Corresponding reference numerals have similar meanings unless explicitly stated otherwise. In Fig. 7, the battery powered device 600 according to the present invention comprises an integrated circuit 100 coupled to a battery storage 620 through power line 610. Power line 610 may be indirectly coupled to external power line 110 or 230, or may be a direct extension of power line 110 or 230. The use of an integrated circuit 100 with power consumption control according to the present invention, e.g. on/off switching facilities, in a device like battery- powered device 600 enhances the sales value of such a device because of its reduced power consumption, because this lengthens the contiguous operational period, i.e. the period without the need for recharging or replacing the batteries, of the device. In addition, by avoiding transient voltage drops, the modus operandi of other battery powered elements e.g. displays or output signal generators of battery powered device 600 is less threatened by the avoidance of excessive power surges.

The control circuitry 180 of integrated circuit 100 can be equipped with an delay elements 182 as previously described for controlling the power consumption of the battery-powered device 600 during standby, or with data storage elements 192, 194 as previously described to enhance the contiguous operational period by means of power consumption control of the battery-powered device 600 in its active mode. Obviously, these measures can be combined to yield a battery-powered device 600 with power consumption control in both standby and active mode.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:

1. An integrated circuit comprising: an external power line for providing a supply current to the integrated circuit; an internal power line; a further power line; a circuit portion coupled to the internal power line and the further power line; control circuitry for generating a first control signal; coupling means coupled to the control circuitry (180) for coupling the external power line to the internal power line, characterized in that: the control circuitry is arranged to generate a second control signal; and said coupling means comprise: first means for providing a first portion of the supply current to the internal power line in response to the first control signal; and second means for providing a second portion of the supply current to the internal power line in response to the second control signal.

2. An integrated circuit as claimed in claim 1, characterized in that the control circuitry comprises a delay element for generating the second control signal a selected time delay after the first control signal has been generated.

3. An integrated circuit as claimed in claim 1 or 2, characterized in further comprising a decoupling capacitor coupled to the internal power line and the further power line.

4. An integrated circuit as claimed in claim 2, characterized in that the delay element comprises a flip flop responsive to a clock signal.

5. An integrated circuit as claimed in claim 2, characterized in that the delay element comprises a delay chain comprising a plurality of inverters.

6. An integrated circuit as claimed in any of the claims 1-5, characterized in that said first means and said second means are pMOS transistors, the external power line is an external supply voltage line, the internal power line is an internal supply voltage line and the further power line is a ground voltage line.

7. An integrated circuit as claimed in any of the claims 1-5, characterized in that said first means and said second means are nMOS transistors, the external power line is an external ground voltage line, the internal power line is an internal ground voltage line and the further power line is a supply voltage line.

8. An integrated circuit as claimed in any of the claims 1-5, characterized in further comprising: an external ground voltage line; further coupling means coupling the external ground voltage line to the further power line, wherein the further power line is an internal ground voltage line.

9. An integrated circuit as claimed in claim 8, characterized in that: the control circuitry is arranged to generate a third control signal; and said further coupling means are coupled to the control circuitry, said further coupling means comprising: third means for providing a first portion of a further supply current to the further power line in response to the first control signal; fourth means for providing a second portion of a further supply current to the further power line in response to the third control signal.

10. An integrated circuit as claimed in claim 9, characterized in that the control circuitry comprises a further delay element for generating the third control signal a selected time delay after the second control signal has been generated.

11. An integrated circuit as claimed in claim 8, characterized in further comprising: further control circuitry for generating a first further control signal; said further coupling means being coupled to said further control circuitry, said further coupling means comprising: third means for providing a first portion of a further supply current to the further power line in response to the first further control signal; a further delay element for generating a second further control signal a selected time delay after the first further control signal has been generated and fourth means for providing a second portion of a further supply current to the further power line in response to the second further control signal.

12. An integrated circuit as claimed in claim 1, characterized in that the control circuitry comprises: a first data storage element for generating the first control signal based on a data value stored in the first data storage element; and a second data storage element for generating the second control signal based on a data value stored in the second data storage element.

13. An integrated circuit as claimed in claim 12, characterized in that the first data storage element and the second data storage element form at least a part of a data register.

14. A battery-powered device comprising: a battery storage; an integrated circuit, a power line for providing a supply current to the integrated circuit from a battery stored in the battery storage; characterized in that the integrated circuit comprises: an external power line coupled to the power line for further providing the supply current to the integrated circuit; an internal power line; a further power line; a circuit portion coupled to the internal power line and the further power line; control circuitry for generating a first control signal and a second control signal; coupling means coupled to the control circuitry for coupling the external power line to the internal power line, said coupling means comprising: first means for providing a first portion of the supply current to the internal power line in response to the first control signal; and second means for providing a second portion of the supply current to the internal power line in response to the second control signal.

15. A battery powered device as claimed in claim 14, characterized in that the control circuitry comprises a delay element for generating the second control signal a selected time delay after the control signal has been generated.

16. A battery powered device as claimed in claim 14, characterized in that the control circuitry comprises: a first data storage element for generating the first control signal based on a data value stored in the first data storage element; and a second data storage element for generating the second control signal based on a data value stored in the second data storage element.