EP1064682A1 - Dram-zellenanordnung und verfahren zu deren herstellung - Google Patents

Dram-zellenanordnung und verfahren zu deren herstellung

Info

Publication number
EP1064682A1
EP1064682A1 EP99916756A EP99916756A EP1064682A1 EP 1064682 A1 EP1064682 A1 EP 1064682A1 EP 99916756 A EP99916756 A EP 99916756A EP 99916756 A EP99916756 A EP 99916756A EP 1064682 A1 EP1064682 A1 EP 1064682A1
Authority
EP
European Patent Office
Prior art keywords
word line
adjacent
trenches
sta
produced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP99916756A
Other languages
German (de)
English (en)
French (fr)
Inventor
Bernd Goebel
Eve Marie Martin
Emmerich Bertagnolli
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1064682A1 publication Critical patent/EP1064682A1/de
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/906—Dram with capacitor electrodes used for accessing, e.g. bit line is capacitor plate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/907—Folded bit line dram configuration

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
EP99916756A 1998-03-18 1999-02-25 Dram-zellenanordnung und verfahren zu deren herstellung Ceased EP1064682A1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19811882A DE19811882A1 (de) 1998-03-18 1998-03-18 DRAM-Zellenanordnung und Verfahren zu deren Herstellung
DE19811882 1998-03-18
PCT/DE1999/000510 WO1999048151A1 (de) 1998-03-18 1999-02-25 Dram-zellenanordnung und verfahren zu deren herstellung

Publications (1)

Publication Number Publication Date
EP1064682A1 true EP1064682A1 (de) 2001-01-03

Family

ID=7861402

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99916756A Ceased EP1064682A1 (de) 1998-03-18 1999-02-25 Dram-zellenanordnung und verfahren zu deren herstellung

Country Status (7)

Country Link
US (1) US6097049A (ja)
EP (1) EP1064682A1 (ja)
JP (1) JP2002507841A (ja)
KR (1) KR100615735B1 (ja)
DE (1) DE19811882A1 (ja)
TW (1) TW409409B (ja)
WO (1) WO1999048151A1 (ja)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19929211B4 (de) * 1999-06-25 2005-10-06 Infineon Technologies Ag Verfahren zur Herstellung eines MOS-Transistors sowie einer DRAM-Zellenanordung
US6355520B1 (en) * 1999-08-16 2002-03-12 Infineon Technologies Ag Method for fabricating 4F2 memory cells with improved gate conductor structure
KR100652370B1 (ko) * 2000-06-15 2006-11-30 삼성전자주식회사 플로팅 바디효과를 제거한 반도체 메모리소자 및 그제조방법
US6642552B2 (en) * 2001-02-02 2003-11-04 Grail Semiconductor Inductive storage capacitor
DE10125967C1 (de) * 2001-05-29 2002-07-11 Infineon Technologies Ag DRAM-Zellanordnung mit vertikalen MOS-Transistoren und Verfahren zu deren Herstellung
US6699777B2 (en) 2001-10-04 2004-03-02 Micron Technology, Inc. Etch stop layer in poly-metal structures
DE10232002B4 (de) * 2002-07-15 2008-12-11 Qimonda Ag Verfahren zur selbstjustierten selektiven Kontaktierung von Gate-Elektroden vertikaler Transistoren eines integrierten Halbleiterspeichers und integrierter Halbleiterspeicher
US7508075B2 (en) * 2003-08-01 2009-03-24 Micron Technology, Inc. Self-aligned poly-metal structures
CN100539184C (zh) * 2004-02-16 2009-09-09 富士电机电子技术株式会社 双方向元件及其制造方法、半导体装置
US7176662B2 (en) * 2005-02-23 2007-02-13 Coldwatt, Inc. Power converter employing a tapped inductor and integrated magnetics and method of operating the same
KR100697291B1 (ko) * 2005-09-15 2007-03-20 삼성전자주식회사 비휘발성 반도체 메모리 장치 및 그 제조방법
KR100660881B1 (ko) * 2005-10-12 2006-12-26 삼성전자주식회사 수직 채널 트랜지스터를 구비한 반도체 소자 및 그 제조방법
KR100833182B1 (ko) * 2005-11-17 2008-05-28 삼성전자주식회사 수직채널 트랜지스터를 구비한 반도체 메모리장치 및 그제조 방법
KR100881392B1 (ko) 2006-10-31 2009-02-05 주식회사 하이닉스반도체 수직형 트랜지스터를 구비한 반도체 소자 및 그의 제조방법
KR100912965B1 (ko) 2007-12-24 2009-08-20 주식회사 하이닉스반도체 수직 채널 트랜지스터를 구비한 반도체 소자의 제조 방법
CN102623049B (zh) * 2011-01-27 2015-03-11 北京兆易创新科技股份有限公司 一种非易失性存储单元及其数据编程、读取、擦除方法
TWI418008B (zh) * 2011-08-01 2013-12-01 Winbond Electronics Corp 半導體元件及其製造方法
CN113451269B (zh) * 2020-03-25 2022-07-22 长鑫存储技术有限公司 字线结构和半导体存储器

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0793365B2 (ja) * 1984-09-11 1995-10-09 株式会社東芝 半導体記憶装置およびその製造方法
US4737829A (en) * 1985-03-28 1988-04-12 Nec Corporation Dynamic random access memory device having a plurality of one-transistor type memory cells
DE3780895T2 (de) * 1986-09-24 1993-03-11 Nec Corp Komplementaerer feldeffekt-transistor mit isoliertem gate.
US4949138A (en) * 1987-10-27 1990-08-14 Texas Instruments Incorporated Semiconductor integrated circuit device
JPH03131064A (ja) * 1989-10-17 1991-06-04 Fujitsu Ltd 半導体装置
JP2932635B2 (ja) * 1990-08-11 1999-08-09 日本電気株式会社 半導体記憶装置
DE19519160C1 (de) * 1995-05-24 1996-09-12 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
DE19620625C1 (de) * 1996-05-22 1997-10-23 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
DE19727436C1 (de) * 1997-06-27 1998-10-01 Siemens Ag DRAM-Zellenanordnung mit dynamischen selbstverstärkenden Speicherzellen und Verfahren zu deren Herstellung
EP0917203A3 (de) * 1997-11-14 2003-02-05 Infineon Technologies AG Gain Cell DRAM Struktur und Verfahren zu deren Herstellung

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9948151A1 *

Also Published As

Publication number Publication date
DE19811882A1 (de) 1999-09-23
JP2002507841A (ja) 2002-03-12
TW409409B (en) 2000-10-21
WO1999048151A1 (de) 1999-09-23
US6097049A (en) 2000-08-01
KR20010041982A (ko) 2001-05-25
KR100615735B1 (ko) 2006-08-25

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