EP1046193B1 - Mit esd-schutz ausgestatteter integrierter schaltkreis - Google Patents

Mit esd-schutz ausgestatteter integrierter schaltkreis Download PDF

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Publication number
EP1046193B1
EP1046193B1 EP99939428A EP99939428A EP1046193B1 EP 1046193 B1 EP1046193 B1 EP 1046193B1 EP 99939428 A EP99939428 A EP 99939428A EP 99939428 A EP99939428 A EP 99939428A EP 1046193 B1 EP1046193 B1 EP 1046193B1
Authority
EP
European Patent Office
Prior art keywords
highly doped
doped surface
integrated circuit
surface area
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP99939428A
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English (en)
French (fr)
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EP1046193A1 (de
Inventor
Hans U. SCHRÖDER
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NXP BV
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NXP BV
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Publication date
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Priority to EP99939428A priority Critical patent/EP1046193B1/de
Publication of EP1046193A1 publication Critical patent/EP1046193A1/de
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Publication of EP1046193B1 publication Critical patent/EP1046193B1/de
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements

Definitions

  • the invention relates to an integrated circuit comprising protection means for protecting against electrostatic discharge, which protection means is provided on a substrate of a first conductivity type, and said protection means comprises a first highly doped surface area of a second, opposite, conductivity type, a second highly doped surface area of the second conductivity type, a first gate insulated from the surface of the integrated circuit, which first gate is positioned so as to form a first MOS-device in conjunction with the first and the second highly doped surface areas, and a third highly doped surface area of the first conductivity type, which is located directly beside the second highly doped surface area, the first gate and the second and the third highly doped surface areas are electrically coupled to a first reference terminal, the substrate being provided with a well of the second conductivity type, the well being partly stretched out into the region of the first highly doped surface area, and the well being provided with a fourth highly doped surface area of the first conductivity type which is electrically coupled to a bonding pad BP of the integrated circuit.
  • SCR element Silicon-Controlled Rectifier
  • the SCR element is in fact a four-layer pnpn (or npnp) structure with connections on the outer p-layer and the outer n-layer. One of the connections is formed by the fourth highly doped surface area and the other one of the connections is formed by the second highly doped surface area.
  • a purpose of the protection means is to avoid damage in the integrated circuit caused by electrostatic discharge (ESD).
  • ESD protection means In general, diodes, Field oxide NMOS, thin oxide NMOS, and Silicon Controlled Rectifiers are used as ESD protection means.
  • a problem of the known ESD protection means is that if for instance the bonding pad is negatively biased with respect to the first reference terminal, no n + diffusion is to be electrically connected to the bonding pad in a p-substrate CMOS integrated circuit, because the n + diffusion at the bonding-pad would be forward biased with respect to the substrate. This would cause a current through the substrate, which adversely affects the behaviour of the integrated circuit. For the same reason, an n + /p diode and an NMOS as ESD protection means coupled to the first reference terminal is not allowed.
  • An inventive integrated circuit of the type described in the opening paragraph is therefore characterized in that the well further comprises a fifth highly doped surface area of the first conductivity type, a second gate insulated from the surface of the integrated circuit, and a sixth highly doped surface area of the second conductivity type which is located directly beside the fifth highly doped surface area, and in that the second gate is positioned so as to form a second MOS-device in conjunction with the fourth and the fifth highly doped surface areas, and in that the second gate and the fifth and the sixth highly doped surface areas are electrically coupled to a second reference terminal.
  • the protection means provide for two protection paths. Let us for example assume that the first conductivity type is the p-type and the second conductivity type is the n-type.
  • first protection path comprises a p + n diode, which is formed by the p + diffusion (the fourth highly doped surface area) at the bonding pad and the n-well (i.e. the well if the second conductivity type is the n-type).
  • first protection path forms an ESD-protection between the bonding pad and the second reference terminal.
  • the other one of the two protection paths is formed by the SCR of which, in this example, the outer p-layer is formed by the fourth p + doped surface area in the n-well, and of which the outer n-layer is formed by the second n + doped surface area in the p-type substrate.
  • the protection means according to the invention do not have an n + diffusion which is electrically connected to the bonding-pad. This is in contrast with the known protection means.
  • Figure 1 is a cross-sectional view of a part of an integrated circuit having input protection means for protecting against electrostatic discharge.
  • the integrated circuit comprises a p-type substrate SBSTR.
  • the well WLL is of the n-type, and will hereinafter be referred to as the n-well WLL.
  • the integrated circuit is provided with highly doped surface areas d1, d2 and d6 of the n-type, which will hereinafter be referred to as n + areas, and with highly doped surface areas d3, d4 and d5 of the p-type which will hereinafter be referred to as p + areas.
  • a first gate g1 and the n + areas d1 and d2 jointly form a first MOS-device MN.
  • the first gate g1, the n + area d2, and the p + area d3 are electrically connected to a first reference terminal VSS.
  • a second gate g2 and the p + areas d4 and d5 jointly form a second MOS-device MP.
  • the second gate g2, the p + area d5, and the n + area d6 are electrically connected to a second reference terminal VDD.
  • the p + area d4, the p + area d5, and the n + area d6 are located within the n-well WLL.
  • the n + area d1 is only partially located within the n-well WLL.
  • the p + area d4 is electrically connected to a bonding pad BP of the integrated circuit.
  • the bonding pad BP is for instance an input pad which is electrically connected to an input of an electronic circuit (not shown in the Figures) of the integrated circuit.
  • a gate of a MOS-transistor of the electronic circuit is electrically connected to the input pad.
  • Such a MOS-transistor can very easily be damaged by an electrostatic discharge on its gate because the gate of such a MOS-transistor has a very high input impedance.
  • the protection means limits the voltage at the bonding pad, caused by an electrostatic discharge, for both positive and negative voltage spikes.
  • Figure 2 shows a simplified electrical circuit diagram corresponding to the part of the integrated circuit shown in Figure 1 .
  • the source and the back gate of the second MOS-transistor MP which are formed respectively by the p + area d5 and the n-well WLL, are connected to the second reference terminal VDD.
  • the second gate g2 is also connected to the second reference terminal VDD.
  • a drain of the MOS-transistor MP being the p + area d4, is connected to the bonding pad BP.
  • a first bipolar transistor T 1 is with an emitter connected to the bonding pad BP, with a collector to a base of a second bipolar transistor T 2 , and with a base to a collector of the second bipolar transistor T 2 .
  • the collector of the first bipolar transistor T 1 is connected via a first resistor R 1 to the first reference terminal VSS.
  • the collector of the second bipolar transistor T 2 is connected via a second resistor R 2 to the second reference terminal VDD.
  • the emitter of the second bipolar transistor T 2 is connected to the first reference terminal VSS.
  • the first resistor R 1 is caused by the resistance of the substrate SBSTR between the n + area d1 and the p + area d3.
  • the second resistor R 2 is caused by the resistance of the n-well WLL between the n + area d1 and the n + area d6.
  • the first and second bipolar transistors T 1 - T 2 , and the first and second resistors R 1 - R 2 together form the SCR the operation of which is well known.
  • the conductivity types may be reversed, in which case, of course, the voltages to be applied must be adapted.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Claims (1)

  1. Ein integrierter Schaltkreis, der Schutzmittel zum Schutz gegen elektrostatische Entladung umfasst, wobei das Schutzmittel auf einem Substrat (SBSTR) eines ersten Leitfähigkeitstyps vorgesehen ist und das Schutzmittel umfasst: einen ersten hoch dotierten Oberflächenbereich (d1) eines zweiten, entgegengesetzten Leitfähigkeitstyps, einen zweiten hoch dotierten Oberflächenbereich (d2) vom zweiten Leitfähigkeitstyp, ein erstes Gate (g1), das von der Oberfläche (S) des integrierten Schaltkreises isoliert ist, wobei das erste Gate (g1) so angeordnet ist, dass es zusammen mit dem ersten (d1) und dem zweiten (d2) hoch dotierten Oberflächenbereich ein erstes MOS-Bauelement (MN) ausbildet, und einen dritten hoch dotierten Oberflächenbereich (d3) vom ersten Leitfähigkeitstyp, der direkt neben dem zweiten hoch dotierten Oberflächenbereich (d2) befindlich ist, wobei das erste Gate (g1) und der zweite (d2) und der dritte (d3) hoch dotierte Oberflächenbereich mit einem ersten Bezugsanschlusspunkt (VSS) elektrisch verbunden sind, wobei das Substrat (SBSTR) mit einer Wanne (WLL) vom zweiten Leitfähigkeitstyp versehen ist, wobei sich die Wanne (WLL) teilweise in die Region des ersten hoch dotierten Oberflächenbereichs (d1) erstreckt und die Wanne (WLL) mit einem vierten hoch dotierten Oberflächenbereich (d4) vom ersten Leitfähigkeitstyp versehen ist, der mit einem Verbindungsfeld (BP) des integrierten Schaltkreises elektrisch verbunden ist, dadurch gekennzeichnet, dass die Wanne (WLL) ferner umfasst: einen fünften hoch dotierten Oberflächenbereich (d5) vom ersten Leitfähigkeitstyp, ein zweites Gate (g2), das von der Oberfläche (S) des integrierten Schaltkreises isoliert ist, und einen sechsten hoch dotierten Oberflächenbereich (d6) vom zweiten Leitfähigkeitstyp, der direkt neben dem fünften hoch dotierten Oberflächenbereich (d5) befindlich ist, und dass das zweite Gate (g2) so angeordnet ist, dass es zusammen mit dem vierten (d4) und dem fünften (d5) hoch dotierten Oberflächenbereich ein zweites MOS-Bauelement (MP) ausbildet, und dass das zweite Gate (g2) und der fünfte (d5) und der sechste (d6) hoch dotierte Oberflächenbereich mit einem zweiten Bezugsanschlusspunkt (VDD) elektrisch verbunden sind.
EP99939428A 1998-08-04 1999-07-29 Mit esd-schutz ausgestatteter integrierter schaltkreis Expired - Lifetime EP1046193B1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP99939428A EP1046193B1 (de) 1998-08-04 1999-07-29 Mit esd-schutz ausgestatteter integrierter schaltkreis

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP98202623 1998-08-04
EP98202623 1998-08-04
PCT/EP1999/005517 WO2000008688A1 (en) 1998-08-04 1999-07-29 An integrated circuit provided with esd protection means
EP99939428A EP1046193B1 (de) 1998-08-04 1999-07-29 Mit esd-schutz ausgestatteter integrierter schaltkreis

Publications (2)

Publication Number Publication Date
EP1046193A1 EP1046193A1 (de) 2000-10-25
EP1046193B1 true EP1046193B1 (de) 2008-10-08

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EP99939428A Expired - Lifetime EP1046193B1 (de) 1998-08-04 1999-07-29 Mit esd-schutz ausgestatteter integrierter schaltkreis

Country Status (5)

Country Link
US (1) US6215135B1 (de)
EP (1) EP1046193B1 (de)
JP (1) JP2002522906A (de)
DE (1) DE69939684D1 (de)
WO (1) WO2000008688A1 (de)

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TW457689B (en) * 2000-01-11 2001-10-01 Winbond Electronics Corp High current ESD protection circuit
DE10005811A1 (de) * 2000-02-10 2001-08-23 Micronas Gmbh Laterale Thyristorstruktur zum Schutz vor elektrostatischer Entladung
WO2002025750A1 (de) * 2000-09-22 2002-03-28 Siemens Aktiengesellschaft Elektrode und/oder leiterbahn für organische bauelemente und herstellungsverfahren dazu
DE10111462A1 (de) * 2001-03-09 2002-09-19 Infineon Technologies Ag Thyristorstruktur und Überspannungsschutzanordnung mit einer solchen Thyristorstruktur
US20030042498A1 (en) * 2001-08-30 2003-03-06 Ming-Dou Ker Method of forming a substrate-triggered SCR device in CMOS technology
US20040121474A1 (en) * 2002-12-19 2004-06-24 Genoptix, Inc Detection and evaluation of chemically-mediated and ligand-mediated t-cell activation using optophoretic analysis
US20050045952A1 (en) * 2003-08-27 2005-03-03 International Business Machines Corporation Pfet-based esd protection strategy for improved external latch-up robustness
TWI227052B (en) * 2003-12-23 2005-01-21 Macronix Int Co Ltd ESD protection circuit for dual-polarity input pad
KR100629436B1 (ko) * 2004-09-08 2006-09-27 매그나칩 반도체 유한회사 고전압 소자의 정전기 보호장치
US8010927B2 (en) * 2007-10-02 2011-08-30 International Business Machines Corporation Structure for a stacked power clamp having a BigFET gate pull-up circuit
TWI349368B (en) * 2008-01-24 2011-09-21 Raydium Semiconductor Corp Dual triggered silicon controlled rectifier
CN101521224B (zh) * 2008-02-27 2010-07-14 瑞鼎科技股份有限公司 双触发型可控硅整流器
US8198651B2 (en) 2008-10-13 2012-06-12 Infineon Technologies Ag Electro static discharge protection device
US8102002B2 (en) * 2008-12-16 2012-01-24 Analog Devices, Inc. System and method for isolated NMOS-based ESD clamp cell
JP5540801B2 (ja) 2010-03-19 2014-07-02 富士通セミコンダクター株式会社 Ｅｓｄ保護回路及び半導体装置
TWI416706B (zh) * 2010-12-20 2013-11-21 Univ Nat Chiao Tung 三維積體電路的靜電放電防護結構
CN114582866A (zh) * 2020-11-30 2022-06-03 三星电子株式会社 半导体器件
CN113782528B (zh) * 2021-11-11 2022-02-08 北京芯可鉴科技有限公司 半导体器件、集成电路产品以及制造方法

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JPH04230072A (ja) * 1990-12-27 1992-08-19 Toshiba Corp 半導体集積回路の保護回路
US5400202A (en) * 1992-06-15 1995-03-21 Hewlett-Packard Company Electrostatic discharge protection circuit for integrated circuits
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Also Published As

Publication number Publication date
JP2002522906A (ja) 2002-07-23
DE69939684D1 (de) 2008-11-20
US6215135B1 (en) 2001-04-10
WO2000008688A1 (en) 2000-02-17
EP1046193A1 (de) 2000-10-25

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