EP1023641A1 - Methode und system zur kontrolle von entwurfsregeln - Google Patents

Methode und system zur kontrolle von entwurfsregeln

Info

Publication number
EP1023641A1
EP1023641A1 EP98951922A EP98951922A EP1023641A1 EP 1023641 A1 EP1023641 A1 EP 1023641A1 EP 98951922 A EP98951922 A EP 98951922A EP 98951922 A EP98951922 A EP 98951922A EP 1023641 A1 EP1023641 A1 EP 1023641A1
Authority
EP
European Patent Office
Prior art keywords
design
corrected
image
data
layout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98951922A
Other languages
English (en)
French (fr)
Other versions
EP1023641A4 (de
Inventor
Fang-Cheng Chang
Yao-Ting Wang
Yagyensh C. Pati
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Synopsys Inc
Original Assignee
Numerical Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/931,921 external-priority patent/US5858580A/en
Priority claimed from US09/130,996 external-priority patent/US6757645B2/en
Priority claimed from US09/153,783 external-priority patent/US6470489B1/en
Priority claimed from US09/154,397 external-priority patent/US6453452B1/en
Application filed by Numerical Technologies Inc filed Critical Numerical Technologies Inc
Publication of EP1023641A1 publication Critical patent/EP1023641A1/de
Publication of EP1023641A4 publication Critical patent/EP1023641A4/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70058—Mask illumination systems
    • G03F7/70091—Illumination settings, i.e. intensity distribution in the pupil plane or angular distribution in the field plane; On-axis or off-axis settings, e.g. annular, dipole or quadrupole settings; Partial coherence control, i.e. sigma or numerical aperture [NA]
    • G03F7/70116—Off-axis setting using a programmable means, e.g. liquid crystal display [LCD], digital micromirror device [DMD] or pupil facets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
EP98951922A 1997-09-17 1998-09-17 Methode und system zur kontrolle von entwurfsregeln Withdrawn EP1023641A4 (de)

Applications Claiming Priority (13)

Application Number Priority Date Filing Date Title
US5930697P 1997-09-17 1997-09-17
US08/931,921 US5858580A (en) 1997-09-17 1997-09-17 Phase shifting circuit manufacture method and apparatus
US931921 1997-09-17
US59306P 1997-09-17
US6954997P 1997-12-12 1997-12-12
US69549P 1997-12-12
US130996 1998-08-07
US09/130,996 US6757645B2 (en) 1997-09-17 1998-08-07 Visual inspection and verification system
US154397 1998-09-16
US09/153,783 US6470489B1 (en) 1997-09-17 1998-09-16 Design rule checking system and method
US09/154,397 US6453452B1 (en) 1997-12-12 1998-09-16 Method and apparatus for data hierarchy maintenance in a system for mask description
US153783 1998-09-16
PCT/US1998/019510 WO1999014638A1 (en) 1997-09-17 1998-09-17 Design rule checking system and method

Publications (2)

Publication Number Publication Date
EP1023641A1 true EP1023641A1 (de) 2000-08-02
EP1023641A4 EP1023641A4 (de) 2009-04-22

Family

ID=27556793

Family Applications (2)

Application Number Title Priority Date Filing Date
EP98951922A Withdrawn EP1023641A4 (de) 1997-09-17 1998-09-17 Methode und system zur kontrolle von entwurfsregeln
EP98947103A Withdrawn EP1023639A4 (de) 1997-09-17 1998-09-17 Methode und gerät zur strukturierung hierarchischer daten in einer masken-definition

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP98947103A Withdrawn EP1023639A4 (de) 1997-09-17 1998-09-17 Methode und gerät zur strukturierung hierarchischer daten in einer masken-definition

Country Status (5)

Country Link
EP (2) EP1023641A4 (de)
JP (2) JP2003526110A (de)
KR (2) KR20010024117A (de)
AU (3) AU9775198A (de)
WO (1) WO1999014638A1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI681479B (zh) * 2015-08-17 2020-01-01 德商果尼阿克有限公司 用於分析半導體晶圓之處理的方法及裝置

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6453452B1 (en) 1997-12-12 2002-09-17 Numerical Technologies, Inc. Method and apparatus for data hierarchy maintenance in a system for mask description
US7412676B2 (en) 2000-06-13 2008-08-12 Nicolas B Cobb Integrated OPC verification tool
JP2004503879A (ja) 2000-06-13 2004-02-05 メンター　グラフィックス　コーポレイション 集積化検証および製造適応ツール
US6425113B1 (en) 2000-06-13 2002-07-23 Leigh C. Anderson Integrated verification and manufacturability tool
US6978436B2 (en) 2000-07-05 2005-12-20 Synopsys, Inc. Design data format and hierarchy management for phase processing
US6430737B1 (en) 2000-07-10 2002-08-06 Mentor Graphics Corp. Convergence technique for model-based optical and process correction
JP2002122977A (ja) * 2000-10-17 2002-04-26 Sony Corp フォトマスクの作成法、フォトマスク、並びに露光方法
KR100649969B1 (ko) * 2000-12-26 2006-11-27 주식회사 하이닉스반도체 마스크 제작방법
US6395438B1 (en) 2001-01-08 2002-05-28 International Business Machines Corporation Method of etch bias proximity correction
US6505327B2 (en) 2001-04-13 2003-01-07 Numerical Technologies, Inc. Generating an instance-based representation of a design hierarchy
JP3572053B2 (ja) * 2001-05-31 2004-09-29 株式会社東芝 露光マスクの製造方法、マスク基板情報生成方法、半導体装置の製造方法およびサーバー
US6721928B2 (en) 2001-07-26 2004-04-13 Numerical Technologies, Inc. Verification utilizing instance-based hierarchy management
US6560766B2 (en) 2001-07-26 2003-05-06 Numerical Technologies, Inc. Method and apparatus for analyzing a layout using an instance-based representation
US6735752B2 (en) 2001-09-10 2004-05-11 Numerical Technologies, Inc. Modifying a hierarchical representation of a circuit to process features created by interactions between cells
US6738958B2 (en) 2001-09-10 2004-05-18 Numerical Technologies, Inc. Modifying a hierarchical representation of a circuit to process composite gates
US6880135B2 (en) 2001-11-07 2005-04-12 Synopsys, Inc. Method of incorporating lens aberration information into various process flows
US7085698B2 (en) 2001-12-18 2006-08-01 Synopsys, Inc. Method for providing flexible and dynamic reporting capability using simulation tools
US7159197B2 (en) 2001-12-31 2007-01-02 Synopsys, Inc. Shape-based geometry engine to perform smoothing and other layout beautification operations
JP4138318B2 (ja) * 2002-01-08 2008-08-27 株式会社ルネサステクノロジ リソグラフィプロセスマージン評価装置、リソグラフィプロセスマージン評価方法およびリソグラフィプロセスマージン評価プログラム
US7293249B2 (en) 2002-01-31 2007-11-06 Juan Andres Torres Robles Contrast based resolution enhancement for photolithographic processing
US7386433B2 (en) 2002-03-15 2008-06-10 Synopsys, Inc. Using a suggested solution to speed up a process for simulating and correcting an integrated circuit layout
US6944844B2 (en) 2002-04-03 2005-09-13 Synopsys, Inc. System and method to determine impact of line end shortening
US6931613B2 (en) 2002-06-24 2005-08-16 Thomas H. Kauth Hierarchical feature extraction for electrical interaction calculations
US6687895B2 (en) 2002-07-03 2004-02-03 Numerical Technologies Inc. Method and apparatus for reducing optical proximity correction output file size
US7069534B2 (en) 2003-12-17 2006-06-27 Sahouria Emile Y Mask creation with hierarchy management using cover cells
US7861207B2 (en) 2004-02-25 2010-12-28 Mentor Graphics Corporation Fragmentation point and simulation site adjustment for resolution enhancement techniques
US7448012B1 (en) 2004-04-21 2008-11-04 Qi-De Qian Methods and system for improving integrated circuit layout
WO2005111874A2 (en) * 2004-05-07 2005-11-24 Mentor Graphics Corporation Integrated circuit layout design methodology with process variation bands
US7240305B2 (en) 2004-06-02 2007-07-03 Lippincott George P OPC conflict identification and edge priority system
JP4266189B2 (ja) 2004-07-09 2009-05-20 株式会社東芝 半導体集積回路パターンの検証方法、フォトマスクの作成方法、半導体集積回路装置の製造方法、及び半導体集積回路パターンの検証方法を実現するためのプログラム
JP4904034B2 (ja) * 2004-09-14 2012-03-28 ケーエルエー−テンカー コーポレイション レチクル・レイアウト・データを評価するための方法、システム及び搬送媒体
US7617473B2 (en) * 2005-01-21 2009-11-10 International Business Machines Corporation Differential alternating phase shift mask optimization
US7506285B2 (en) 2006-02-17 2009-03-17 Mohamed Al-Imam Multi-dimensional analysis for predicting RET model accuracy
US7739650B2 (en) 2007-02-09 2010-06-15 Juan Andres Torres Robles Pre-bias optical proximity correction
EP2153376B1 (de) 2007-05-23 2011-10-19 Nxp B.V. Prozessfensterbewusste detektion und korrektur von lithografischen druckproblemen auf maskenniveau
US7805699B2 (en) 2007-10-11 2010-09-28 Mentor Graphics Corporation Shape-based photolithographic model calibration
JP5100405B2 (ja) * 2008-01-16 2012-12-19 株式会社東芝 データベースの作成方法およびデータベース装置
US7975244B2 (en) 2008-01-24 2011-07-05 International Business Machines Corporation Methodology and system for determining numerical errors in pixel-based imaging simulation in designing lithographic masks

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19609652A1 (de) * 1995-03-13 1996-09-19 Sony Corp Verfahren und Vorrichtung zur Korrektur von Maskenmustern

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0608657A1 (de) * 1993-01-29 1994-08-03 International Business Machines Corporation Vorrichtung und Verfahren zur Verarbeitung von Formdaten zur Korrektur von Streveffekten
GB2291219B (en) * 1994-07-05 1998-07-01 Nec Corp Photo-mask fabrication and use
JPH08297692A (ja) * 1994-09-16 1996-11-12 Mitsubishi Electric Corp 光近接補正装置及び方法並びにパタン形成方法
US5682323A (en) * 1995-03-06 1997-10-28 Lsi Logic Corporation System and method for performing optical proximity correction on macrocell libraries
US5553273A (en) * 1995-04-17 1996-09-03 International Business Machines Corporation Vertex minimization in a smart optical proximity correction system
JP2917879B2 (ja) * 1995-10-31 1999-07-12 日本電気株式会社 フォトマスク及びその製造方法
US5705301A (en) * 1996-02-27 1998-01-06 Lsi Logic Corporation Performing optical proximity correction with the aid of design rule checkers
US5801954A (en) * 1996-04-24 1998-09-01 Micron Technology, Inc. Process for designing and checking a mask layout
US5707765A (en) * 1996-05-28 1998-01-13 Microunity Systems Engineering, Inc. Photolithography mask using serifs and method thereof
DE19818440C2 (de) * 1998-04-24 2002-10-24 Pdf Solutions Gmbh Verfahren zur Erzeugung von Daten für die Herstellung einer durch Entwurfsdaten definierten Struktur

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19609652A1 (de) * 1995-03-13 1996-09-19 Sony Corp Verfahren und Vorrichtung zur Korrektur von Maskenmustern

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
NEWMARK D M ET AL: "Large area optical proximity correction using pattern based corrections" PROCEEDINGS OF THE SPIE - THE INTERNATIONAL SOCIETY FOR OPTICAL ENGINEERING USA, vol. 2322, 1994, pages 374-386, XP002518834 ISSN: 0277-786X *
See also references of WO9914638A1 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI681479B (zh) * 2015-08-17 2020-01-01 德商果尼阿克有限公司 用於分析半導體晶圓之處理的方法及裝置

Also Published As

Publication number Publication date
KR20010024117A (ko) 2001-03-26
EP1023639A4 (de) 2009-04-29
JP4624550B2 (ja) 2011-02-02
AU9775198A (en) 1999-04-05
WO1999014638A1 (en) 1999-03-25
AU9396198A (en) 1999-04-05
EP1023641A4 (de) 2009-04-22
AU9396098A (en) 1999-04-05
JP2003526110A (ja) 2003-09-02
KR20010024113A (ko) 2001-03-26
EP1023639A1 (de) 2000-08-02
JP2003523545A (ja) 2003-08-05

Similar Documents

Publication Publication Date Title
US6470489B1 (en) Design rule checking system and method
US6453452B1 (en) Method and apparatus for data hierarchy maintenance in a system for mask description
US6370679B1 (en) Data hierarchy layout correction and verification method and apparatus
EP1023641A1 (de) Methode und system zur kontrolle von entwurfsregeln
EP1023640B1 (de) Methode und gerät zur kontrolle und korrektur der hierarchischen daten eines layouts
WO1999014637A1 (en) Data hierarchy layout correction and verification method and apparatus
Liebmann et al. TCAD development for lithography resolution enhancement
US7401319B2 (en) Method and system for reticle-wide hierarchy management for representational and computational reuse in integrated circuit layout design
US7657864B2 (en) System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques
US7172838B2 (en) Chromeless phase mask layout generation
US5682323A (en) System and method for performing optical proximity correction on macrocell libraries
US7237221B2 (en) Matrix optical process correction
US7337421B2 (en) Method and system for managing design corrections for optical and process effects based on feature tolerances
US7650587B2 (en) Local coloring for hierarchical OPC
US7165234B2 (en) Model-based data conversion
US7194725B1 (en) System and method for design rule creation and selection
US6782524B2 (en) Photomask and integrated circuit manufactured by automatically correcting design rule violations in a mask layout file
CN109559979A (zh) 集成电路制造方法
US20050005256A1 (en) Photomask and integrated circuit manufactured by automatically correcting design rule violations in a mask layout file
CN110968981A (zh) 集成电路布局图生成方法和系统
CN114556210A (zh) 在校正光刻掩模中使用掩模制造模型
US20230152683A1 (en) Mask Synthesis Integrating Mask Fabrication Effects and Wafer Lithography Effects
JP2000066370A (ja) マスクパターン作成方法および装置
Chiang et al. Systematic Yield-Lithography

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20000403

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB IT

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: NUMERICAL TECHNOLOGIES, INC.

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: SYNOPSYS MERGER HOLDINGS LLC

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: SYNOPSYS, INC.

A4 Supplementary search report drawn up and despatched

Effective date: 20090323

RIC1 Information provided on ipc code assigned before grant

Ipc: G03F 1/14 20060101AFI20090313BHEP

17Q First examination report despatched

Effective date: 20090925

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20111020