EP1002337A1 - Boitiers de puces de semiconducteur et leur procede de production - Google Patents

Boitiers de puces de semiconducteur et leur procede de production

Info

Publication number
EP1002337A1
EP1002337A1 EP98931882A EP98931882A EP1002337A1 EP 1002337 A1 EP1002337 A1 EP 1002337A1 EP 98931882 A EP98931882 A EP 98931882A EP 98931882 A EP98931882 A EP 98931882A EP 1002337 A1 EP1002337 A1 EP 1002337A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor chip
dielectric
current paths
film
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98931882A
Other languages
German (de)
English (en)
Inventor
Walter Schmidt
Marco Martinelli
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dyconex Patente AG
Original Assignee
Dyconex Patente AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dyconex Patente AG filed Critical Dyconex Patente AG
Publication of EP1002337A1 publication Critical patent/EP1002337A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body

Definitions

  • the invention relates to surface-mountable semiconductor chip packages and their production method according to the definition of the claims.
  • Today's surface-mountable semiconductor chip packages (chip-scale packaging or CSP) are characterized by an advanced miniaturization of the structures at low manufacturing costs. The trend has been that the package is the same size or only slightly larger than the semiconductor chip itself. At the same time, the number of inputs and outputs is constantly increasing. Another important advantage of semiconductor chip packages is their pre-testability, even under dynamic conditions.
  • An elastic intermediate layer must be applied between the semiconductor chip and the substrate of the electronic circuit so as to compensate for thermal stresses that occur during manufacture. At least one additional redirection layer from the semiconductor chip connections to the soldering points of the packaging interface is to be provided in order to carry out diversions.
  • the semiconductor chip itself should be adequately protected against mechanical and / or chemical attacks.
  • the manufacturing processes for semiconductor chip packages are intended to meet common assembly standards.
  • the semiconductor chip packages should reliably survive the overall assembly of the electronic circuit and not impair it.
  • the at least one additional redirection layer should be the size of the wafer on which the semiconductor chips are produced. This is not the case with the tester process, where semiconductor chips are individually connected to a redirection layer.
  • the semiconductor chip connections should be at a minimum distance of 100 ⁇ m from each other.
  • the maximum possible number of inputs and outputs per semiconductor chip should not be limited by the packaging manufacturing process itself. This is the case with the Tessera method, where the entire available semiconductor chip area cannot be used when the inputs and outputs are merged. It is an object of the present invention to show semiconductor chip packages and methods for their production which meet the requirements and criteria listed above. In particular, the manufacturing processes should be inexpensive and compatible with known and common manufacturing processes in the semiconductor industry.
  • the idea of the present invention is to provide semiconductor chips with at least one dielectric film, which film serves as an elastic intermediate layer or as a mechanical and / or chemical protective layer.
  • This dielectric film can be provided with openings which extend down to the semiconductor chip connections, so that current paths can be created on such a film and in such openings. Such current paths can form a redirection layer.
  • the number of bypass layers can be increased by repeatedly applying dielectric foils to bypass layers and by repeatedly creating openings and current paths. Soldering points of the packaging interface can be created in an external layer current paths.
  • the attachment of one or more dielectric foils to semiconductor chips and the creation of openings and the structuring of current paths can be carried out inexpensively in the present process, while fulfilling the requirements and criteria listed above.
  • the present invention has recognized that the wafer can already be provided with a large number of unribbed semiconductor chips with intermediate layers and / or protective layers, so that a semiconductor chip package is created which is simply provided with further redirection layers and / or soldering points Packing interface can be provided. This represents a considerable simplification of the production of semiconductor chip packages, since the semiconductor chips no longer have to be individually connected to redirection layers, as is known from the Tessera process.
  • the present invention has also recognized that individual semiconductor chips can be connected directly to foils or printed circuit boards that form part of the electrical circuit to be produced, so that semiconductor chip packages can be produced in an integrated manner in the electronic circuit.
  • semiconductor chip packages that are directly connected to a substrate and integrated into the structure of the electronic circuit no longer require a package interface with solder joints, and they also no longer require an elastic intermediate layer.
  • the present invention is completely compatible with the DYCOstrate® process for the production of printed circuit boards and film printed circuit boards, as disclosed, for example, in the applicant's document WO93 / 26143.
  • FIGS. 1 to 7 show a variant of the method for producing semiconductor chip packages presented here, in which a semiconductor chip is provided with a dielectric film, an opening is made in this film and current paths are created on the film and in the opening.
  • FIGS. 8 and 9 show a further variant of the method for producing semiconductor chip packages presented here, in which a soldering point of a package interface is attached to the semiconductor chip package according to FIG.
  • FIG. 10 shows a further variant of the method for producing semiconductor chip packages presented here, in which the elasticity of the soldering point of the semiconductor chip package according to FIG. 9 is increased by etching back.
  • FIG. 11 shows a further variant of the method for producing semiconductor chip packages presented here, in which the semiconductor chip package according to FIG. 9 is provided on one side with a further film, an opening is made in this further film and on the film and in the opening
  • FIG. 12 shows a further variant of the method for producing semiconductor chip packages presented here, in which the semiconductor chip package according to FIG. 9 or 11 is provided on both sides with a further film.
  • FIG. 13 shows a further variant of the method for producing semiconductor chip packages presented here, in which the semiconductor chip package according to FIG. 7 is provided with a further film, a further opening is made in this further film, and further current paths are applied to the further film and in the further opening on which a solder joint of a packaging interface is attached.
  • Figure 14 shows the decrease in the minimum distance between
  • FIG. 15 shows part of an exemplary embodiment of a semiconductor chip package produced by the method presented here.
  • FIGS. 1 to 7 show in section a variant of the method for producing semiconductor chip packages, in which a semiconductor chip is provided with a dielectric film, an opening is made in this film and current paths are applied to the film and in the opening.
  • FIG. 1 shows part of a semiconductor chip made of, for example, silicon 1 with a conductive layer 1.1 made of, for example, gold and a connection 1.2 made of, for example, nickel.
  • a semiconductor chip made of, for example, silicon 1 with a conductive layer 1.1 made of, for example, gold and a connection 1.2 made of, for example, nickel.
  • the person skilled in the art can use semiconductor chips made of other semiconductor materials as well as conductive layers and connections made of other conductive materials. This semiconductor chip can still be scratched in the wafer, but it can also be present individually.
  • FIG. 2 shows how the semiconductor chip according to FIG. 1 is provided on one side with at least one dielectric film 2.
  • a dielectric film 2 consists, for example, of 12 to more than 100 ⁇ m thick polyimide, acrylate, epoxy or epoxy-acrylate compounds. They enable a simple, inexpensive and proven adhesive connection. Such an adhesive connection is advantageously carried out by lamination under pressure and temperature.
  • Such a dielectric film 2 can be laminated onto a conductive film 3.
  • This conductive foil 3 consists, for example, of 12 to over 100 ⁇ m thick copper.
  • such a conductive film 3 can also be connected to this dielectric film 2 in a separate step, ie after the dielectric film 2 has been applied to the semiconductor chip.
  • non-structured foils 2, 3, which are connected in a flat manner are used.
  • these foils 2, 3 can have the dimension of the wafer, so that they can simultaneously be connected to a multiplicity of semiconductor chips of the (practically uncut, since mechanically more stable) wafer.
  • Such a dielectric forms an elastic intermediate layer between the semiconductor chip itself and a substrate of an electronic circuit and can compensate for thermal stresses that occur during manufacture.
  • the thickness of the intermediate layer can be set via the thickness and / or the number of dielectric 2 laminated on.
  • several different films of dielectric 2 can also be used, for example one or more first films of dielectric can be used for connection, while one or more further films of dielectric can serve as spacers.
  • FIG. 3 shows how an opening 3.1 is made in the guide film 3 according to FIG. 2. This takes place, for example, in a known photochemical structure. With such a structuring, a large number of such openings 3.1 can of course be made simultaneously in the guide film 3.
  • the opening 3.1 in the guide film 3 extends to the underlying dielectric 2.
  • this opening 3.1 in the guide film 3 is in the area, i.e. created above or in the vicinity of the semiconductor chip connection 1.2.
  • the diameter of this opening 3.1 in the conductive foil 3 corresponds to that of the semiconductor chip connection 1.2.
  • dielectric 2 is exposed area-wide through this opening 3.1 in the conductive foil 3.
  • This exposed dielectric 2 is then opened according to the opening 3.1 in the guide film 3 except for the semi-conductor terchip connection 1.2 removed.
  • One side of this semiconductor chip connection 1.2 is thus partially or completely exposed.
  • An opening 22 is created with, for example, sloping walls, which extends from the conductive film 3 into the dielectric film 2.
  • This removal of dielectric 2 can be done in a variety of ways. Removal by chemical or plasma etching processes in which the dielectric 2 is etched through and back-etched is known, so that inclined opening walls are formed. However, it is entirely within the scope of the present invention to carry out such ablation by other known and common methods such as laser ablation. With knowledge of this invention, the person skilled in the art thus has a wide variety of options for varying this method step.
  • FIG. 5 shows how any protruding edges of the opening 3.2 according to FIG. 4 are removed. This is done, for example, by thinning or etching away the conductive layer 3 to form a thinned conductive layer 30, protruding edges of the conductive material of the opening 3.2 preferably being removed.
  • This process step is disclosed in the applicant's application EP-0668712.
  • An opening 3.3 is formed which extends from the conductive foil 3 through the dielectric foil 2 to the semiconductor chip connection 1.2 and which has no protruding edges made of conductive foil material.
  • those skilled in the art are also aware of other ways of removing such edges when they know this invention. He can simply leave them standing or he can bend them towards the semiconductor chip.
  • FIG. 6 shows the semiconductor chip according to FIG. 5 after plating on a layer 4 made of electrically conductive material, for example made of copper.
  • a layer 4 made of electrically conductive material for example made of copper.
  • the electrically conductive material is electrochemically deposited and plated.
  • Through-plated openings 3.4 are also referred to as through-plating.
  • the deposited conductive material layer 4 is thin and has a thickness of less than 25 ⁇ m.
  • the semiconductor chip connection 1.2 has electrical contact with the plated-on conductive foil 300 via the plated-on and, for example, oblique walls of the plated-through plate 3.4.
  • FIG. 7 shows a semiconductor chip package produced in the present method after structuring of the conductive foil 300 and / or through-plating 3.4 according to FIG. 6.
  • This structuring takes place, for example, by means of known photochemical methods.
  • individual areas of the conductive film 300 and the through plating 3.4 are removed in a targeted manner by wet chemical etching.
  • current paths 40, 3000 separated by insulation regions are formed.
  • the wet chemical etching takes place specifically in the depth, i.e.
  • the conductive layer 300 and / or the through-plating 3.4 are removed in areas not covered by photoresist down to the film 2 and / or down to the semiconductor chip connection 1.2.
  • These current paths structured in this way run in the same way as one or more current paths 3000 on the flat dielectric 2 and / or as one or more current paths 40 in one or more openings in the dielectric 2.
  • the wet chemical etching takes place in all exposed areas (ie the areas for the harsh chemicals and liquids are accessible) simultaneously.
  • the semiconductor chip package according to FIG. 7 has a semiconductor chip on which an elastic intermediate layer made of dielectric 2 is applied on one side.
  • This dielectric 2 offers the semiconductor chip mechanical and / or chemical protection.
  • a semiconductor chip connection 1.2 is electrical Trisch contacted with current paths 40.3000.
  • Current paths 3000 on the flat dielectric 2 and / or current paths 40 in openings in the dielectric 2 form a redirection layer for redirecting current paths between semiconductor chip connections and a packaging interface.
  • the semiconductor chip package according to FIG. 7 can be processed further to form a semiconductor chip package with soldering points of a package interface.
  • the elastic intermediate layer can also be thickened by attaching further dielectric foils; further foils can also be attached to the semiconductor chip package on both sides for stronger mechanical and / or chemical protection. Exemplary variants of this are described with the aid of the following FIGS. 8 to 13.
  • the dielectric film 2 can already represent the substrate itself and the current paths 40, 3000 can already be part of the electronic circuit to be produced, so that the semiconductor chip package according to FIG. 7 is integrated in the electronic circuit and no more soldering points of a package interface are attached Need to become.
  • FIGS. 8 and 9 show in section a further variant of the method for producing semiconductor chip packages presented here, in which a soldering point of a package interface is attached to the semiconductor chip package according to FIG. 7.
  • FIG. 8 shows how part of the semiconductor chip package according to FIG. 7 can be selectively covered with one or more solder resistance layers 5.
  • a solder resistance layer 5 is applied, for example, around a soldering point to be applied, in such a way that a solder ball surrounded by the solder resistance layer 5 does not flow away during soldering can.
  • Known and common methods for the selective application of thin layers can be used. It is advantageous to use a few ⁇ m-thin layers of palladium or nickel as the solder resistance layer 5.
  • Other solder resistance materials can of course also be used if the present invention is known.
  • Solder lacquers for example those made from organic materials, can also be applied.
  • Known methods such as printing, spraying, casting, etc. can be used to apply solder resistance layers.
  • the application of one or more layers of soldering resistance material is optional, ie it is not essential for the teaching of the present invention.
  • FIG. 9 shows how, starting from a semiconductor chip package according to FIG. 8, a solder ball 6 is attached to a soldering point of a package interface.
  • This solder ball 6 is attached in the middle of a solder resistance layer 5, so that this solder ball 6 cannot flow away during soldering.
  • Known and common methods for attaching solder balls can be used. Of course, a large number of such solder balls 6 can be attached to the soldering points of a packaging interface.
  • the section according to FIG. 9 corresponds to part of a semiconductor chip package produced by the present method, as is shown in an exemplary embodiment in FIG.
  • FIG. 10 shows in section a further variant of the method for producing semiconductor chip packages presented here, in which the elasticity of the soldering point of the semiconductor chip package according to FIG. 9 is increased by etching back.
  • exposed dielectric 2 can be removed.
  • This removal of dielectric 2 can be done in a variety of ways. Removal by chemical or plasma etching processes, in which the dielectric 2 is thinned and etched back, is known, so that, for example, below a solder joint of a pack interface, a pocket 20.1 formed by back-etching arises. Of course, a large number of such bags 20.1 can be attached at the same time. However, it is entirely within the scope of the present invention to carry out such removal by other known and common methods.
  • the solder ball 6 of the solder joint is thus attached to a partially free-hanging current path 3000.
  • the solder joint thus has a certain elasticity, which elasticity of the solder joint allows easier assembly of the semiconductor chip package on an electronic circuit.
  • FIG. 11 shows in section a further variant of the method for producing semiconductor chip packages presented here, in which the semiconductor chip package according to FIG. 9 or 11 is provided on one side with a further dielectric film 22, so that a thicker dielectric formed from two films 2, 22 is formed.
  • a thicker layer consisting of two layers of dielectric, represents a larger elastic intermediate layer between the semiconductor chip itself and the substrate and can consequently compensate for larger thermal stresses which occur during production.
  • An opening is made in this further dielectric sheet 22, current paths are created on this sheet 22 and in this opening, and a soldering point of a package interface is attached.
  • a two-layer structure is formed from two foils 2.22 dielectric arranged one above the other and with a redirection layer from a semiconductor chip connection to a soldering point of the packaging interface.
  • This process step takes place in analogy to the process step according to FIG. 2.
  • a further adhesive connection is advantageously carried out by lamination under pressure and temperature.
  • the further dielectric film 22 can be laminated onto a conductive film 3. This guiding film 3 is advantageously not structured and connected in a two-dimensional manner.
  • the procedural Steps for creating the further opening in the further film 22 take place as already explained in the description of FIGS.
  • this further dielectric film 22 can be laminated together with a further conductive film, the further opening can be created in the dielectric 22 according to an opening in this further conductive film.
  • This further opening is advantageously created in the further conductive film in the region, ie above or in the vicinity of a current path 40, 3000 of the semiconductor chip package according to FIG. 7. Protruding edges of the further conductive foil can be removed by thinning and preferred etching in the edge area, this further conductive foil and this further opening in the further conductive foil and in the further dielectric 22 can be plated with further conductive material and current paths can be in this further conductive material and / or in the another foil in a structure process.
  • These current paths structured in this way run in the same way as one or more current paths 3002 on the flat dielectric 22 and / or as one or more current paths 42 in an opening in the dielectric 22.
  • the method step of applying a solder ball 6 for a solder joint of a packaging interface can as already explained in the description of FIGS. 8 and 9, so that reference is made to them. Of course, more than one additional opening and more than one solder ball 6 can be attached and applied.
  • the dielectric foils 2, 22 are provided with openings which extend down to the semiconductor chip connection 1.2.
  • Current paths 40, 3000, 42, 3002 are laid out on the foils 2, 22 and in the openings.
  • the current paths 40, 3000 form a redirection layer for redirecting current paths between semiconductor chip connections and soldering points of a packaging interface.
  • Soldering points of the packaging interface can be created in an external layer current paths 42.3002.
  • One redirection layer is sufficient for many applications of semiconductor chip packages, but complex semiconductor chips require several redirection layers.
  • FIG. 12 shows in section a further variant of the method for producing semiconductor chip packages presented here, in which the semiconductor chip package according to FIG. 9 or 11 is provided on both sides with a further dielectric film 2 ′, 22.
  • the method steps for attaching these further dielectric foils 2, 22 take place analogously to the description according to FIG. 2, so that reference is made to them.
  • These further dielectric foils 2, 22 are advantageously, but not necessarily, each connected to a conductive foil.
  • FIG. 12 shows another conductive foil 3 'laminated onto the dielectric foil 2' as an example. These foils and guiding foils are advantageously not structured and planarly coherent.
  • the method steps for the formation of one or more redirection layers for redirecting current paths between semiconductor chip connections and soldering points of a packaging interface and for forming soldering points of the packaging interface can be carried out in an outer layer of current paths analogously to the description according to FIG. 11, so it’s referenced.
  • the semiconductor chip package according to FIG. 12 is largely protected against mechanical and / or chemical attacks by dielectric foils 22 ′ 22 attached on both sides and by conductive foils structured in current paths and unstructured by conductive foils. Attachment on both sides according to FIG. 12 is not mandatory but advantageous for the implementation of the present teaching. In particular, this largely symmetrical design with double-sided foils made of dielectric and conductive material avoids bimetal effects. Of Furthermore, a semiconductor chip package protected in this way on both sides can be processed further more easily, for example, assembly in electronic circuits is simplified.
  • the conductive film 3 'laminated onto the further dielectric film 2' also forms an electromagnetic shield.
  • FIG. 13 shows in section a further variant of the method for producing semiconductor chip packages presented here, in which the semiconductor chip package according to FIG. 7 is provided with a further film, a further opening is made in this further film, further ones on the further film and in the further opening Current paths are created, on which a solder joint of a packaging interface is attached.
  • This variant largely corresponds to that according to FIG. 11, so that reference is made to this for its description.
  • the variant according to FIG. 13 shows that not only the internal current paths 40, 3000 form a redirection layer for redirecting current paths between semiconductor chip connections and solder points of a packaging interface, but the external current paths 3002, 42 form another such Redirection layer.
  • FIG. 14 schematically shows the reduction in the minimum distance between semiconductor chip connections produced using the method presented here compared with the minimum distance between known semiconductor chip connections.
  • the semiconductor chip connections are in accordance with the present method, as shown in FIG. 14 on the right On the side are not created in the middle of solder pads, ie they are solder-free with current paths 40.42 in openings for semiconductor chip connections and current paths 3000.3002 on a flat dielectric contacted. This soldering eye-free contacting drastically reduces the minimum possible distance between current paths.
  • FIG. 14 schematically shows the reduction in the minimum distance between semiconductor chip connections produced using the method presented here compared with the minimum distance between known semiconductor chip connections.
  • the distance between a current path 40, 42 in an opening to a semiconductor chip connection and a minimally guided current path 3000, 3002 on dielectric can be reduced by half, for example, and the minimum distance between two current paths 40, 42 in openings to semiconductor chip connections, for example by a third.
  • the semiconductor chip connections can be created, for example, at a minimum distance of 70 ⁇ m from one another. Shorter distances are quite possible.
  • FIG. 15 schematically shows a part of an exemplary embodiment of a semiconductor chip package produced using the method presented here.
  • the semiconductor chip 1 has on one side a multiplicity of inputs and outputs or semiconductor chip connections 1.2, which semiconductor chip connections 1.2 are connected via current paths 40, 3000 to the solder ball 6 of the package interface.
  • An elastic intermediate layer made of dielectric 2 is placed between the semiconductor chip connections 1.2 and that of the solder balls 6 of the package interface.
  • These current paths 40, 3000 run as current paths 3000 on the flat dielectric 2 and as current paths 40 in openings of the dielectric 2.
  • the maximum possible number of inputs and outputs per semiconductor chip 1 is not limited per se by the package production process. The entire available semiconductor chip area is used in particular when merging the inputs and outputs.
  • the semiconductor chip packages When producing the semiconductor chip packages using unribbed semiconductor chips of a wafer according to the present method, the semiconductor chip packages must be separated from one another. This can be done by sawing with a diamond saw. So that the soft dielectric films do not tear, they can be cooled to make them more brittle. Any residues of metal areas made of copper, for example, can be removed beforehand, for example by etching, so that the diamond saw does not come into contact with metal areas.
  • Another variant consists in the use of plasma in order to etch dielectric foils along the boundaries of the semiconductor chip packages.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un procédé de production de boîtiers de puces de semiconducteur faisant appel à des puces de semiconducteur (1). Selon ce procédé, au moins une puce de semiconducteur (1) est pourvue d'au moins une pellicule diélectrique (2, 2', 22), au moins une ouverture est pratiquée dans au moins une pellicule (2) et des chemins conducteurs (40, 42, 3000, 3002) sont placés dans la ou les ouvertures, de sorte qu'au moins une borne de puce de semiconducteur (1.2) soit mise en contact électrique avec les chemins conducteurs (40, 42, 3000, 3002) par l'intermédiaire d'au moins une ouverture.
EP98931882A 1997-07-24 1998-07-23 Boitiers de puces de semiconducteur et leur procede de production Withdrawn EP1002337A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CH178697 1997-07-24
CH178697 1997-07-24
PCT/CH1998/000318 WO1999005721A1 (fr) 1997-07-24 1998-07-23 Boitiers de puces de semiconducteur et leur procede de production

Publications (1)

Publication Number Publication Date
EP1002337A1 true EP1002337A1 (fr) 2000-05-24

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Application Number Title Priority Date Filing Date
EP98931882A Withdrawn EP1002337A1 (fr) 1997-07-24 1998-07-23 Boitiers de puces de semiconducteur et leur procede de production

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Country Link
EP (1) EP1002337A1 (fr)
CA (1) CA2296333A1 (fr)
WO (1) WO1999005721A1 (fr)

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JP2001085560A (ja) * 1999-09-13 2001-03-30 Sharp Corp 半導体装置およびその製造方法
DE19950885A1 (de) * 1999-10-22 2001-04-26 Wuerth Elektronik Gmbh Nachgiebige Kontakte zum anorganischen Substratträger mit dünner Metallisierung und Verfahren zu deren Herstellung
DE10126296B4 (de) * 2001-05-30 2008-04-17 Qimonda Ag Verfahren zur Herstellung eines elektronischen Bauelements
DE10149688B4 (de) * 2001-10-09 2004-09-09 Infineon Technologies Ag Verfahren zum Herstellen einer Mikrokontaktfeder auf einem Substrat

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Publication number Priority date Publication date Assignee Title
US4764485A (en) * 1987-01-05 1988-08-16 General Electric Company Method for producing via holes in polymer dielectrics
CA2137861A1 (fr) * 1994-02-21 1995-08-22 Walter Schmidt Procede de fabrication de structures

Non-Patent Citations (1)

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Title
See references of WO9905721A1 *

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WO1999005721A1 (fr) 1999-02-04
CA2296333A1 (fr) 1999-02-04

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