EP0853815A1 - Formation d'une region de source et de drain en verre dope - Google Patents

Formation d'une region de source et de drain en verre dope

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Publication number
EP0853815A1
EP0853815A1 EP96934065A EP96934065A EP0853815A1 EP 0853815 A1 EP0853815 A1 EP 0853815A1 EP 96934065 A EP96934065 A EP 96934065A EP 96934065 A EP96934065 A EP 96934065A EP 0853815 A1 EP0853815 A1 EP 0853815A1
Authority
EP
European Patent Office
Prior art keywords
source
substrate
dopant
glass
iayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP96934065A
Other languages
German (de)
English (en)
Other versions
EP0853815A4 (fr
Inventor
Scott E. Thompson
Chia-Hong Jan
Paul A. Packan
Tahir Ghani
Ebrahim Andideh
Farhad K. Moghadam
Mark T. Bohr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of EP0853815A1 publication Critical patent/EP0853815A1/fr
Publication of EP0853815A4 publication Critical patent/EP0853815A4/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/38—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions
    • H01L21/385—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

Definitions

  • the invention relates to the field of forming self-aligned source and drain regions for field-effect transistors.
  • ion implantation is used to align a source and drain region with a gate (and/or with gate spacers in some processes).
  • the ion implantation damages the crystalline structure of the silicon substrate necessitating thermal annealing.
  • the implanted dopant diffuses thereby deepening the source and drain regions. These deeper regions make it difficult to control the adverse effects of short channels.
  • the source and drain extension regions should be extremely shallow and heavily doped (e.g., 0.05 to 0.1 um versus 0.2 to 0.4 um for 0.2 to 0.5 um channel length transistors).
  • Scaling implanted p+ junctions is particularly difficult since the light boron (B 11 ) ions channel during implantation and secondly, since the ions damage the silicon bonds causing point defects. These point defects significantly increase the diffusion of the boron atoms (up to 1000 times) during subsequent thermal annealing. Thus, even for light ions, such as B11 , and low energy implants, the implant damage results in enhanced diffusion.
  • Another technique for solving this problem is to diffuse the portion of the source and drain regions adjacent to the gate (tip or tip region) from doped spacers and to form the more heavily doped main portions of the source and drain regions by ion implantation.
  • This provides some advantage over the ion implantation of both the tip region and main portion of the source and drain regions but implant damage from the source/drain implant still affects the depth of the diffused tip region resulting in degraded short channel effects. Short channel effects are discussed in numerous publications such as Silicon Processing forthe VLSI Era. Vol. 2, by S. Wolf, published by Lattice press, see Section 5.5, beginning at page 338.
  • the present invention permits the simultaneous formation of both an ultra shallow heavily doped source and drain extension region, main portions of the source and drain regions and doping of the polysilicon gate without ion implantation.
  • a method for fabricating field-effect transistors on a substrate where the source and drain regions are formed in alignment with a gate is described.
  • a source of dopant is used having (i) a more lightly doped region which is formed directly adjacent to the gate and (ii) a more heavily doped region spaced apart from the gate.
  • This dopant source is formed on the suiface of the substrate.
  • the dopant is diffused from the source of dopant in a heating step simultaneously forming both the lightly doped source and drain tip region and the main portion of the source and drain regions. This diffusion is done in an ambient that may include oxygen or ammonia.
  • boron is diffused from two different layers of borosilicate glass (BSG).
  • BSG borosilicate glass
  • Spacers are formed adjacent to the gate by anisotropically etching a silicon nitride layer which overlies a 2% BSG layer. Then a 6% BSG layer is formed over the spacers and 2% BSG layer to supply the dopant for the more heavily doped main portion of the source and drain regions.
  • Both BSG layers are annealed prior to being pattemed to prevent the formation of an unstable boron compound that would otherwise adversely effect diffusion. Rapid thermal processing is used to diffuse the dopant into the substrate from both BSG layers.
  • the substrate surface is first damaged by a heavy neutral species such as silicon or implanted with a neutral species -3- such as carbon which can be used to increase or decrease the diffusion of boron in the substrate before the doped glass is deposited on the substrate.
  • a chemically formed oxide of 5-20A is formed over the substrate prior to formation of the doped glass.
  • Figure 1 is a cross sectional elevation view of a section of a substrate showing an n-well isolated from a p-well. Polysilicon gates and a first glass layer are also shown.
  • Figure 2 illustrates the substrate of Figure 1 after a first photoresist layer has been masked and etching, and during an ion implantation step used to form the tip regions for the n-channel transistor.
  • Figure 3 illustrates the substrate of Figure 2 after the formation of a TEOS layer and a silicon nitride layer.
  • Figure 4 illustrates the substrate of Figure 3 after the silicon nitride layer has been anisotropically etched to form spacers and after the substrate has been covered with a second glass layer.
  • Figure 5 illustrates the substrate of Figure 4 after the masking and etching of a photoresist layer and during an ion implantation step used to form the main portion of the source and drain regions for the n-channel transistor.
  • Figure 6 illustrates the substrate of Figure 5 after diffusion of the boron dopant from the glass layers to form the source and drain regions for the p-channel transistor.
  • Figure 7 illustrates the substrate of Figure 4 for an alternate embodiment where the n-type dopant is diffused from a glass layer.
  • Figure 8 illustrates a preliminary processing step for the substrate of Figure 1 prior to the formation of the first glass layer.
  • Figure 9 illustrates another preliminary step for the substrate of Figure 1 prior to the formation of the first glass layer.
  • a method and structure for forming low damage, shallow source and drain regions in alignment with a gate for a field-effect transistor is described.
  • numerous well-known steps such as masking and etching steps are not discussed in detail in order not to obscure the present invention.
  • specific details are set forth such as specific boron dopant concentrations in order to provide a thorough understanding of the present invention.
  • While the present invention is not Iimited to any particular geometry in one embodiment, it is used for the fabrication of transistors having a channel length of approximately 0.1 um with transistors that operate from a 1.8 volt supply.
  • a section of a monocrystalline silicon substrate 15 is illustrated having a well doped within an n-type conductivity dopant (n well 21 ) and a region or well doped with a p-type conductivity dopant (p well).
  • n well 21 an n-type conductivity dopant
  • p well a region or well doped with a p-type conductivity dopant
  • an n well may be used for p-channel transistors with the n-channel transistors being formed directly in a p-type substrate.
  • n and p well of Figure 1 are isolated from one another by a recessed isolation region specifically, trench 10. Additionally, within the n well 21 there are other isolation trenches 12 for isolating from one another p-channel transistors formed within the n well. Likewise, there are isolation trenches 13 formed within the p well to isolate n-channel transistors formed in the p well from one another.
  • the isolation trenches may be formed using well-known technology. Other isolation technologies such as local oxidation of silicon (LOCOS) may be used instead of trenches
  • LOC local oxidation of silicon
  • a gate insulative layer (such as a high quality, thermally grown oxide to insulate the gate from the substrate) is formed over the substrate.
  • a polycrystalline silicon (polysilicon) layer is deposited and the gates for the field-effect transistors are fabricated using ordinary photolithographic and etching techniques. Two such gates insulated from the substrate are shown in Figure 1. Gate 11 , formed above the n well, as will be seen, is used for a p-channel transistor; the other gate 14, formed above the p well, is used for an n-channel transistor. Numerous steps typically used before the fabrication of the gates are not illustrated, such as cleaning steps, ion implantation steps to adjust threshold voltage, etc. Additionally, other processing steps for reducing the amount of diffusion are discussed later in conjunction with Figures 8 and 9.
  • a conformal layer 16 of borosilicate glass (BSG) is deposited over the entire substrate.
  • This layer may be 10 ⁇ A-30 ⁇ A thick.
  • the layer in one embodiment has a 2% functional description concentration of a p-type conductivity dopant (boron). This layer is referred to hereinafter as 2% BSG layer.
  • TEOS or silane based chemistry is used to deposit the 2% BSG layer.
  • This layer is formed in one embodiment at a temperature of 400-600°C.
  • the p-channel transistor is formed using the present invention while the n-channel transistor is formed using well-known ion implantation.
  • the formation of the n-channel transistor is described nonetheless since the masking steps for the n-type implants are used to diffuse the p-type dopant sources.
  • Figure 2 illustrates the first of two ion implantation step used in the formation of the n-channel transistor.
  • a photoresist layer 17 is formed over the substrate 15. This layer is masked exposed and developed by well-known techniques to reveal the substrate regions where the source and drains are formed for the n-channel transistors and additionally, regions where an n-type dopant is used for well tap 20. This is shown in Figure 2 where the photoresist members 17 protect predetermined areas of the substrate while leaving exposed other areas.
  • the exposed portions of glass layer 16 are etched in alignment with the photoresist members 17. This etching step uses a hydrogen fluoride (HF) based solution.
  • HF hydrogen fluoride
  • the substrate is then subjected to ion implantation of an arsenic dopant as shown by the arrows 18. This forms the regions 19 in alignment with the gate 14 and a region 20 between the trenches 12.
  • This arsenic doping implant is relatively light and is used for forming the tip regions of the source and drain regions for the n-channel transistor.
  • the main portions of the source and drain regions for this n- channel transistor are subsequently formed with the second ion implantation step.
  • a conformal layer of undoped silicon dioxide is formed from tetraethyl orthosilicate (TEOS) by low pressure chemical vapor deposition layer 30 or other undoped LPCVD oxide film is formed over the substrate using well-known processing.
  • This layer provides an etchant stop for the spacers formed for the n-channel transistor.
  • the TEOS layer may be 5 ⁇ A-30 ⁇ A thick.
  • a conformal layer 31 of silicon nitride is formed over the TEOS layer 30.
  • This silicon nitride layer is approximately 80 ⁇ A thick in one embodiment.
  • Well-known type, i.e., sufficient selectively anisotropic etching is used to etch the silicon nitride layer to form spacers 31 shown on opposite sides of gates 11 and 14 of Figure 4.
  • the TEOS layer acts as an etchant step to protect the silicon.
  • the TEOS and BSG regions not covered by the nitride spacers are then etched away. A wet etchant may be used for this purpose.
  • a thin layer of silicon dioxide (5-20A of chemically grown oxide) may now be formed so that there is an ultra thin uniform oxide on the exposed silicon prior to formation of the second glass layer.
  • This oxide is discussed in conjunction with Figure 8.
  • a second layer 35 of BSG is formed over the substrate. This time, however, the layer has a 6% concentration of boron (6% BSG).
  • This layer in one embodiment is approximately 20 ⁇ A-60 ⁇ A thick and is deposited using a TEOS or silane based chemistries at a temperature of 400-600°C in one embodiment.
  • This second glass layer is annealed prior to patterning in an RTA step in the same manner and for the same reason as the first glass layer as discussed above.
  • a photoresist layer 40 is masked, exposed and developed to expose generally the same areas that were exposed in Figure 2. Specifically, gate 12, the areas adjacent to gate 12 (source and drain regions) and region 20; the remainder of the substrate shown in Figure 5 is protected by the photoresist members 40.
  • the cap layer over the glass layer 35 (if used) and the 6% BSG layer 35 are then etched in alignment with the photoresist members 40. This is done by HF based chemistry.
  • the second n-type ion implantation step is now used to implant the arsenic dopant into the regions of the substrate not protected by the photoresist layer 40, spacers 31 , or gate 12.
  • the arrows 41 illustrate the implantation of this arsenic dopant.
  • This dopant is used to form the main portions N+ of the 45 source and drain regions for the n-channel transistors. Note that since the spacers 31 are in place, the dopant is implanted in alignment with the spacers and not in alignment with the gate.
  • this drive step employs rapid thermal processing. Specifically, driving at 1000°C to 1040°C for 10-20 seconds with ramping up to and down from this temperature at 70°C per second. A standard Halogen lamp band rapid thermal reactor is used.
  • the depth of these regions can be made even more shallow or intentionally made deeper by diffusing the dopant in an ambient that alters the diffusing in silicon.
  • ambients are ones that includes oxygen or ammonia. For instance, if the diffusion takes place in an ambient of 10% oxygen and 90% nitrogen the junction depth is reduced by approximately 20% compared to diffusion in an ambient of 100% nitrogen, in general, the oxygen atoms displace silicon atoms in the silicon lattice thereby slowing the diffusion of the boron in silicon.
  • Other annealing ambients or compounds that provide this function may be used.
  • Glass layers 16 and 35 may remain in place for the remainder of the processing and may stay in the completed integrated circuit.
  • Glass layer 35 may be removed to facilitate a subsequent selective TiSi or CoSi2 layer on gates 1 1 and 12 and regions 41 and 45.
  • Figure 8 shows one additional processing step which may be used prior to the deposition of the first glass layer shown in Figure 1.
  • the substrate of Figure 1 is again shown prior to the deposition of the 2% glass layer.
  • an ultra thin layer 60 of silicon dioxide (5-20A thick) is first formed on the substrate.
  • This layer may be a chemically grown oxide layer.
  • the glass layer is then formed on the silicon dioxide layer.
  • This oxide layer is no thicker than a typical native oxide layer, however, it is intentionally grown to assure its uniformity across the wafer. This is in contrast to a native oxide layer which may not be uniform across the wafer because of, for example, water drops on the wafer. This oxide strongly affects indiffusion of the boron from the glass.
  • the ultra thin oxide layer provides a uniform interface and thereby assures more predictable diffusion of the boron into the substrate. As mentioned earlier, this oxide is also formed prior to the deposition of the second glass layer.
  • FIG 9 another processing step which may be used to modulate the diffusion rate of the indiffused boron dopant is shown.
  • a heavy neutral species such as silicon or implanted with a neutral species such as carbon which alters the boron diffusing in silicon.
  • Other heavy or neutral atoms may be used such as arsenic, antimony, indium, nitrogen, fluorine, etc. While in Figure 9 this implantation is shown prior to the formation of the glass layer, the implantation may occur after the formation of the glass layer, that is through the glass layer. The damaging of the substrate surface or presence of neutral species in the substrate surface in this manner can be used to slow the rate of diffusion creating a shallower junction. Silicon damage above 3e14 dose reduces the boron diffusion.
  • the various techniques for reducing the diffusion or controlling it such as the growing of the 5-20A of silicon dioxide, the damaging of the upper surface of the substrate, implantation of a neutral species of diffusion in the ambient of oxygen, etc., and the densification of the glass layers prior to their patterning may be used in combination or alone for improving the reliability and performance of the resultant transistors.
  • the result of the processing described above is a source and drain region for the p-type transistor having a tip region 40 adjacent to the gate (from the dopant diffused into the substrate from the 2% BSG layer 16) and a more highly doped main portion of the source and drain regions 41 spaced apart from the gate (from the dopant diffused from the 6% BSG layer 35).
  • the p-type tip region has a dopant concentration of 1-5x10 19 cr ⁇ r 3 while the main portion of the source and drain region has a dopant concentration of 2-5x10 20 cn ⁇ 3 .
  • concentrations of dopants in the glass may be used.
  • layer 16 may have a dopant concentration between 1 to 4% and layer 35 may have a dopant concentration between 6 to 12%.
  • the ultra-shallow p+ regions formed with the described invention, as illustrated in the figures has shown to provide substantial improvement over prior art fabrication where the p-channel source and drain regions are formed with a tip implant in alignment with the gate followed by implantation of the main portion of source and drain regions in alignment with a spacer.
  • Transistors made with the low damage doped source and drain regions of the present invention have shown in one benchmark to have a 25% improved gate delay when operated at 1.8v even when compared to a prior art transistor operated at 2.5v.
  • the present invention as described above, two masking steps are saved when compared to the prior art technique of forming the p- channel device through two implantation steps, one for the tip implant and the other for the main portion of the source and drain regions. Note that with the present invention, the two masking steps used to expose those areas of the substrate which are doped with the n-type dopant for the n- channel transistor source and drain region are also used to etch the BSG layers 16 and 35. In the prior art, two additional masking steps are needed to protect the n-channel device when the p-channel device are implanted.
  • the glass layer 35 is etched in alignment with the photoresist members 40 prior to the implantation illustrated by lines 41. It may be desirable in some processes to leave the 6% BSG layer in piace.
  • the second ion implantation step used to form the N+ source and drain regions for the n-channel transistor is then done through this glass layer.
  • the counter doping effect of the boron dopant in the n- type source and drain regions in general will not present a problem.
  • the arsenic dopant level of the source and drain region for the n-channel transistor is high and consequently, not significantly affected by the introduction of the boron atoms. Leaving Iayer 35 in place saves the step used to remove this Iayer from the areas not protected by the photoresist members.
  • the p-channel transistor is shown fabricated with the present invention and the n-channel transistor is fabricated using conventional ion implantation, the n-channel transistor may likewise be fabricated using one or two layers of glass phosphorous or arsenic doped glass.
  • the dopant for the p-channel transistor was obtained from a glass, specifically BSG, other materials may be used as a source of the dopant such as polysilicon or germanium-silicon.
  • Figure 7 illustrates altemate processing where a single glass Iayer doped with an n-type dopant is used.
  • an additional glass Iayer 50 doped with the n-type dopant e.g., 6% PSG
  • the glass Iayer 50 is formed over the structure shown in Figure 5 without the photoresist Iayer 40.
  • the n-channel transistor is simultaneously formed.
  • Dopant from Iayer 50 forms the main source/drain regions of the n-channel transistor. Note the dopant from Iayer 50 does not diffuse into the Iayer 35. This dopant also diffused under the spacers on gate 12 to form more lightly doped tip regions for the n-channel transistor.
  • the gate 12 is doped with the n-type dopant from Iayer 50.
  • the glass Iayer 16 need not be used to form the p- channel transistor. That is, as in the case of the n-channel transistor described in conjunction with Figure 7, the dopant may be driving under the spacer from the 6% glass Iayer to form the tip source/drain regions. This permits the doping of source/drain for both n-channel and p-channel transistors with a single masking step.

Abstract

L'invention concerne un procédé de fabrication d'une région de source et de drain comprenant une région d'extrémité de source et de drain jouxtant la grille, qui est plus légèrement dopée, et une partie principale de la région de source et de drain espacée de la grille qui est plus fortement dopée. Une première couche (16) de verre (verre de borosilicate 2%) sert à constituer une source de dopage pour la région d'extrémité et une seconde couche (35) de verre (verre de borosilicate 6%) apporte le dopant à la portion de la partie principale des régions de source et de drain plus fortement dopée. Des éléments d'espacement (31) sont formés entre les couches de verre pour séparer la portion d'extrémité de la partie principale des régions de source et de drain.
EP96934065A 1995-10-04 1996-10-03 Formation d'une region de source et de drain en verre dope Withdrawn EP0853815A4 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US53884695A 1995-10-04 1995-10-04
US538846 1995-10-04
PCT/US1996/016002 WO1997013273A1 (fr) 1995-10-04 1996-10-03 Formation d'une region de source et de drain en verre dope

Publications (2)

Publication Number Publication Date
EP0853815A1 true EP0853815A1 (fr) 1998-07-22
EP0853815A4 EP0853815A4 (fr) 1999-10-27

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EP96934065A Withdrawn EP0853815A4 (fr) 1995-10-04 1996-10-03 Formation d'une region de source et de drain en verre dope

Country Status (6)

Country Link
EP (1) EP0853815A4 (fr)
JP (1) JP2001504639A (fr)
KR (1) KR19990064285A (fr)
AU (1) AU7257496A (fr)
IL (1) IL123799A0 (fr)
WO (1) WO1997013273A1 (fr)

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JP3107157B2 (ja) * 1998-04-20 2000-11-06 日本電気株式会社 半導体装置およびその製造方法
US6429062B1 (en) * 1999-09-20 2002-08-06 Koninklike Philips Electronics N.V. Integrated-circuit manufacturing using high interstitial-recombination-rate blocking layer for source/drain extension implant
US7192836B1 (en) * 1999-11-29 2007-03-20 Advanced Micro Devices, Inc. Method and system for providing halo implant to a semiconductor device with minimal impact to the junction capacitance
JP2007525813A (ja) * 2003-12-04 2007-09-06 インターナショナル・ビジネス・マシーンズ・コーポレーション 犠牲注入層を用いて非晶質ではない超薄膜半導体デバイスを形成させるための方法
US7271044B2 (en) 2005-07-21 2007-09-18 International Business Machines Corporation CMOS (complementary metal oxide semiconductor) technology

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KR19990064285A (ko) 1999-07-26
AU7257496A (en) 1997-04-28
WO1997013273A1 (fr) 1997-04-10
IL123799A0 (en) 1998-10-30
JP2001504639A (ja) 2001-04-03
EP0853815A4 (fr) 1999-10-27

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