EP0846289B1 - Circuits prediffuses programmables par l'utilisateur avec memoire ram repartie et utilisation accrue des cellules - Google Patents

Circuits prediffuses programmables par l'utilisateur avec memoire ram repartie et utilisation accrue des cellules Download PDF

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Publication number
EP0846289B1
EP0846289B1 EP97926441A EP97926441A EP0846289B1 EP 0846289 B1 EP0846289 B1 EP 0846289B1 EP 97926441 A EP97926441 A EP 97926441A EP 97926441 A EP97926441 A EP 97926441A EP 0846289 B1 EP0846289 B1 EP 0846289B1
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EP
European Patent Office
Prior art keywords
cells
logic
blocks
bus lines
cell
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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EP97926441A
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German (de)
English (en)
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EP0846289A1 (fr
EP0846289A4 (fr
Inventor
Frederick C. Furtek
Martin T. Mason
Robert B. Luking
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Atmel Corp
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Atmel Corp
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Priority to EP01107758A priority Critical patent/EP1158403B1/fr
Priority to EP01107756A priority patent/EP1158402B1/fr
Priority to EP01107760A priority patent/EP1143336B1/fr
Priority to EP01107759A priority patent/EP1150431B1/fr
Publication of EP0846289A1 publication Critical patent/EP0846289A1/fr
Publication of EP0846289A4 publication Critical patent/EP0846289A4/fr
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Publication of EP0846289B1 publication Critical patent/EP0846289B1/fr
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

Circuits prédiffusés avec matrice de cellules logiques programmables (11; 12) et un réseau de type bus comprenant des lignes de bus locales et express (19, 21, 23, 25). Le réseau de type bus réalise une répartition effective de la matrice en blocs (15) de cellules, chaque bloc possédant son propre ensemble distinct de lignes de bus locales. Les lignes de bus express s'étendent sur plus d'un bloc de cellules grâce à des unités commutateurs répéteurs (27) qui connectent également les lignes de bus locales aux lignes express. Le regroupement des cellules en blocs, avec des répéteurs alignés en rangs et en colonnes le long des délimitations (13) entre les blocs, laisse des espaces aux coins des blocs, ces espaces pouvant être remplis par des blocs de mémoire RAM (83), d'autres structures à mémoire, des structures logiques spécialisées, ou d'autres éléments de fonction spécialisée qui sont connectées au réseau de type bus. Les blocs de mémoire RAM (fig. 13) peuvent être des mémoires RAM statiques (85) comprenant un ou deux ports auxquelles on peut accéder par les lignes de bus (86; 178; 179).

Claims (12)

  1. Circuit intégré logique configurable comprenant,
    des cellules logiques non spécialisées (11) disposées en une pluralité de blocs identiques (15), chaque bloc (15) comportant une pluralité desdites cellules logiques (11), les blocs (15) des cellules (11) étant disposés suivant un motif de grille à rangées et à colonnes multiples de blocs (15), les cellules (11) à l'intérieur de chaque bloc communiquant les unes avec les autres le long de lignes internes aux blocs (15), les blocs (15) des cellules (11) communiquant les uns avec les autres le long des lignes par l'intermédiaire de répéteurs (27) qui sont situés entre lesdites rangées et colonnes des blocs (15), en laissant des espaces aux coins de chacun des blocs (15) de cellules (11), caractérisé en ce que
    des éléments à fonction spécialisée (83) sont disposés auxdits coins de chaque bloc de la pluralité de blocs (15) de cellules (11) dans lesdits espaces et communiquant avec les cellules (11) des blocs correspondants (15) par l'intermédiaire desdites lignes internes aux blocs, chaque élément à fonction spécialisée (83) étant construit de façon à remplir une fonction logique ou de mémoire spécifique.
  2. Circuit selon la revendication 1, dans lequel lesdites cellules logiques (11) sont disposées sous forme d'une matrice de rangées et de colonnes de cellules, ledit circuit formant une matrice de portes logiques programmable sur site.
  3. Circuit selon la revendication 2, dans lequel lesdites lignes forment un réseau de lignes de bus réparties le long des rangées et des colonnes des cellules logiques (11).
  4. Circuit selon la revendication 3, dans lequel ledit réseau de lignes de bus comprend des ensembles de lignes de bus locales internes aux blocs respectifs et un ensemble de lignes de bus rapides qui englobe des blocs multiples (15), les lignes de bus locales dans un ensemble quelconque pouvant être connectées sélectivement les unes aux autres et également connectées sélectivement aux cellules logiques (11) à l'intérieur du bloc qui est associé à cet ensemble, les lignes de bus rapides pouvant être connectées sélectivement les unes aux autres et aux lignes de bus locales mais sans pouvoir être directement connectées à une cellule logique quelconque (11).
  5. Circuit selon la revendication 4, dans lequel ledit réseau de lignes de bus comprend en outre un ensemble d'unités de commutateur répéteur (81) espacées le long desdites lignes de bus et connectant sélectivement des lignes de bus rapides les unes aux autres et à des lignes de bus locales associées, et permettant que des lignes de bus rapides reliées à celles-ci englobent plus d'un seul bloc de cellules logiques (11).
  6. Circuit selon la revendication 1, dans lequel lesdites unités de commutateur répéteur (81) sont alignées en rangées et colonnes le long des limites entre lesdits blocs (15), en laissant ainsi des espaces aux coins des blocs (15) où lesdites rangées et colonnes des unités de commutateur répéteur (81) se recoupent, lesdits éléments à fonction spécialisée étant situés dans lesdits espaces aux intersections desdites rangées et colonnes des unités de commutateur répéteur (81).
  7. Circuit selon la revendication 1, dans lequel lesdits éléments à fonction spécialisée (83) comprennent des structures de mémoire.
  8. Circuit selon la revendication 7, dans lequel lesdites structures de mémoire comprennent une mémoire vive (RAM).
  9. Circuit selon la revendication 7, dans lequel lesdites structures de mémoire comprennent une mémoire non volatile.
  10. Circuit selon la revendication 7, dans lequel lesdites structures de mémoire comprennent une mémoire en deux parties avec des entrées d'adressage séparées pour les opérations de lecture et d'écriture et également des bus de données séparés pour lesdites opérations de lecture et d'écriture.
  11. Circuit selon la revendication 1, dans lequel lesdits éléments à fonction spécialisée (83) comprennent des structures logiques spécialisées.
  12. Circuit selon la revendication 11, dans lequel lesdites structures logiques spécialisées comprennent des multiplicateurs.
EP97926441A 1996-05-20 1997-05-09 Circuits prediffuses programmables par l'utilisateur avec memoire ram repartie et utilisation accrue des cellules Expired - Lifetime EP0846289B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP01107758A EP1158403B1 (fr) 1996-05-20 1997-05-09 FPGA avec des lignes d'horloge configurables
EP01107756A EP1158402B1 (fr) 1996-05-20 1997-05-09 FPGA avec lignes de validation/invalidation
EP01107760A EP1143336B1 (fr) 1996-05-20 1997-05-09 FPGA avec utilisation accruée des cellules
EP01107759A EP1150431B1 (fr) 1996-05-20 1997-05-09 FPGA avec tableaux de consultation

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US650477 1996-05-20
US08/650,477 US5894565A (en) 1996-05-20 1996-05-20 Field programmable gate array with distributed RAM and increased cell utilization
PCT/US1997/007924 WO1997044730A1 (fr) 1996-05-20 1997-05-09 Circuits prediffuses programmables par l'utilisateur avec memoire ram repartie et utilisation accrue des cellules

Related Child Applications (4)

Application Number Title Priority Date Filing Date
EP01107756A Division EP1158402B1 (fr) 1996-05-20 1997-05-09 FPGA avec lignes de validation/invalidation
EP01107758A Division EP1158403B1 (fr) 1996-05-20 1997-05-09 FPGA avec des lignes d'horloge configurables
EP01107760A Division EP1143336B1 (fr) 1996-05-20 1997-05-09 FPGA avec utilisation accruée des cellules
EP01107759A Division EP1150431B1 (fr) 1996-05-20 1997-05-09 FPGA avec tableaux de consultation

Publications (3)

Publication Number Publication Date
EP0846289A1 EP0846289A1 (fr) 1998-06-10
EP0846289A4 EP0846289A4 (fr) 2000-11-22
EP0846289B1 true EP0846289B1 (fr) 2002-03-20

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Family Applications (5)

Application Number Title Priority Date Filing Date
EP01107760A Expired - Lifetime EP1143336B1 (fr) 1996-05-20 1997-05-09 FPGA avec utilisation accruée des cellules
EP01107758A Expired - Lifetime EP1158403B1 (fr) 1996-05-20 1997-05-09 FPGA avec des lignes d'horloge configurables
EP01107756A Expired - Lifetime EP1158402B1 (fr) 1996-05-20 1997-05-09 FPGA avec lignes de validation/invalidation
EP01107759A Expired - Lifetime EP1150431B1 (fr) 1996-05-20 1997-05-09 FPGA avec tableaux de consultation
EP97926441A Expired - Lifetime EP0846289B1 (fr) 1996-05-20 1997-05-09 Circuits prediffuses programmables par l'utilisateur avec memoire ram repartie et utilisation accrue des cellules

Family Applications Before (4)

Application Number Title Priority Date Filing Date
EP01107760A Expired - Lifetime EP1143336B1 (fr) 1996-05-20 1997-05-09 FPGA avec utilisation accruée des cellules
EP01107758A Expired - Lifetime EP1158403B1 (fr) 1996-05-20 1997-05-09 FPGA avec des lignes d'horloge configurables
EP01107756A Expired - Lifetime EP1158402B1 (fr) 1996-05-20 1997-05-09 FPGA avec lignes de validation/invalidation
EP01107759A Expired - Lifetime EP1150431B1 (fr) 1996-05-20 1997-05-09 FPGA avec tableaux de consultation

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Country Link
US (5) US5894565A (fr)
EP (5) EP1143336B1 (fr)
JP (1) JPH11510038A (fr)
KR (1) KR100429063B1 (fr)
CN (1) CN1105970C (fr)
DE (5) DE69721342T2 (fr)
HK (1) HK1011227A1 (fr)
WO (1) WO1997044730A1 (fr)

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