DE69721344D1 - FPGA mit konfigurierbaren Taktleitungen - Google Patents

FPGA mit konfigurierbaren Taktleitungen

Info

Publication number
DE69721344D1
DE69721344D1 DE69721344T DE69721344T DE69721344D1 DE 69721344 D1 DE69721344 D1 DE 69721344D1 DE 69721344 T DE69721344 T DE 69721344T DE 69721344 T DE69721344 T DE 69721344T DE 69721344 D1 DE69721344 D1 DE 69721344D1
Authority
DE
Germany
Prior art keywords
fpga
clock lines
configurable clock
configurable
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69721344T
Other languages
English (en)
Other versions
DE69721344T2 (de
Inventor
Frederick C Furtek
Martin T Mason
Robert B Luking
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of DE69721344D1 publication Critical patent/DE69721344D1/de
Application granted granted Critical
Publication of DE69721344T2 publication Critical patent/DE69721344T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE69721344T 1996-05-20 1997-05-09 FPGA mit konfigurierbaren Taktleitungen Expired - Fee Related DE69721344T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/650,477 US5894565A (en) 1996-05-20 1996-05-20 Field programmable gate array with distributed RAM and increased cell utilization
US650477 1996-05-20

Publications (2)

Publication Number Publication Date
DE69721344D1 true DE69721344D1 (de) 2003-05-28
DE69721344T2 DE69721344T2 (de) 2004-02-19

Family

ID=24609080

Family Applications (5)

Application Number Title Priority Date Filing Date
DE69721342T Expired - Fee Related DE69721342T2 (de) 1996-05-20 1997-05-09 FPGA mit erhöhter Zellnutzung
DE69721344T Expired - Fee Related DE69721344T2 (de) 1996-05-20 1997-05-09 FPGA mit konfigurierbaren Taktleitungen
DE69711159T Expired - Fee Related DE69711159T2 (de) 1996-05-20 1997-05-09 Benutzerprogrammierbares logisches feld mit verteiltem ram und erhöhter zellnutzung
DE69730254T Expired - Fee Related DE69730254T2 (de) 1996-05-20 1997-05-09 FPGA mit Nachschlagtabellen
DE69721343T Expired - Fee Related DE69721343T2 (de) 1996-05-20 1997-05-09 FPGA mit Setz-/Rücksetzleitungen

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE69721342T Expired - Fee Related DE69721342T2 (de) 1996-05-20 1997-05-09 FPGA mit erhöhter Zellnutzung

Family Applications After (3)

Application Number Title Priority Date Filing Date
DE69711159T Expired - Fee Related DE69711159T2 (de) 1996-05-20 1997-05-09 Benutzerprogrammierbares logisches feld mit verteiltem ram und erhöhter zellnutzung
DE69730254T Expired - Fee Related DE69730254T2 (de) 1996-05-20 1997-05-09 FPGA mit Nachschlagtabellen
DE69721343T Expired - Fee Related DE69721343T2 (de) 1996-05-20 1997-05-09 FPGA mit Setz-/Rücksetzleitungen

Country Status (8)

Country Link
US (5) US5894565A (de)
EP (5) EP1158403B1 (de)
JP (1) JPH11510038A (de)
KR (1) KR100429063B1 (de)
CN (1) CN1105970C (de)
DE (5) DE69721342T2 (de)
HK (1) HK1011227A1 (de)
WO (1) WO1997044730A1 (de)

Families Citing this family (204)

* Cited by examiner, † Cited by third party
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