FR2954023B1 - Matrice interconnectee de cellules logiques reconfigurables avec une topologie d'interconnexion croisee - Google Patents
Matrice interconnectee de cellules logiques reconfigurables avec une topologie d'interconnexion croiseeInfo
- Publication number
- FR2954023B1 FR2954023B1 FR0958957A FR0958957A FR2954023B1 FR 2954023 B1 FR2954023 B1 FR 2954023B1 FR 0958957 A FR0958957 A FR 0958957A FR 0958957 A FR0958957 A FR 0958957A FR 2954023 B1 FR2954023 B1 FR 2954023B1
- Authority
- FR
- France
- Prior art keywords
- logic cells
- reconfigurable logic
- interconnection topology
- interconnected matrix
- cross interconnection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000011159 matrix material Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0958957A FR2954023B1 (fr) | 2009-12-14 | 2009-12-14 | Matrice interconnectee de cellules logiques reconfigurables avec une topologie d'interconnexion croisee |
JP2012543875A JP2013514025A (ja) | 2009-12-14 | 2010-12-14 | 交差相互接続トポロジを再構成可能な論理セルの相互接続配列及び集積回路 |
PCT/FR2010/052717 WO2011080452A1 (fr) | 2009-12-14 | 2010-12-14 | Matrice interconnectee de cellules logiques reconfigurables avec une topologie d'interconnexion croisee |
EP10805804A EP2514096A1 (fr) | 2009-12-14 | 2010-12-14 | Matrice interconnectee de cellules logiques reconfigurables avec une topologie d'interconnexion croisee |
US13/512,967 US8742789B2 (en) | 2009-12-14 | 2010-12-14 | Interconnected array of logic cells reconfigurable with intersecting interconnection topology |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0958957A FR2954023B1 (fr) | 2009-12-14 | 2009-12-14 | Matrice interconnectee de cellules logiques reconfigurables avec une topologie d'interconnexion croisee |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2954023A1 FR2954023A1 (fr) | 2011-06-17 |
FR2954023B1 true FR2954023B1 (fr) | 2012-02-10 |
Family
ID=42942202
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0958957A Expired - Fee Related FR2954023B1 (fr) | 2009-12-14 | 2009-12-14 | Matrice interconnectee de cellules logiques reconfigurables avec une topologie d'interconnexion croisee |
Country Status (5)
Country | Link |
---|---|
US (1) | US8742789B2 (fr) |
EP (1) | EP2514096A1 (fr) |
JP (1) | JP2013514025A (fr) |
FR (1) | FR2954023B1 (fr) |
WO (1) | WO2011080452A1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP4235398A1 (fr) * | 2022-02-25 | 2023-08-30 | Universidade de Santiago de Compostela | Processeur hyperdimensionnel à signaux mixtes |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5451887A (en) * | 1986-09-19 | 1995-09-19 | Actel Corporation | Programmable logic module and architecture for field programmable gate array device |
US5338984A (en) * | 1991-08-29 | 1994-08-16 | National Semiconductor Corp. | Local and express diagonal busses in a configurable logic array |
US5208491A (en) * | 1992-01-07 | 1993-05-04 | Washington Research Foundation | Field programmable gate array |
GB9223226D0 (en) * | 1992-11-05 | 1992-12-16 | Algotronix Ltd | Improved configurable cellular array (cal ii) |
US5543640A (en) * | 1994-03-15 | 1996-08-06 | National Semiconductor Corporation | Logical three dimensional interconnections between integrated circuit chips using a two dimensional multi-chip module |
US5581199A (en) * | 1995-01-04 | 1996-12-03 | Xilinx, Inc. | Interconnect architecture for field programmable gate array using variable length conductors |
US5894565A (en) * | 1996-05-20 | 1999-04-13 | Atmel Corporation | Field programmable gate array with distributed RAM and increased cell utilization |
US5825202A (en) * | 1996-09-26 | 1998-10-20 | Xilinx, Inc. | Integrated circuit with field programmable and application specific logic areas |
US6097212A (en) * | 1997-10-09 | 2000-08-01 | Lattice Semiconductor Corporation | Variable grain architecture for FPGA integrated circuits |
JP3391374B2 (ja) | 1998-12-25 | 2003-03-31 | 富士通株式会社 | クロスポイントスイッチ回路および基本スイッチセル電子回路 |
US6184712B1 (en) * | 1999-02-25 | 2001-02-06 | Xilinx, Inc. | FPGA configurable logic block with multi-purpose logic/memory circuit |
US6864710B1 (en) * | 1999-12-30 | 2005-03-08 | Cypress Semiconductor Corp. | Programmable logic device |
EP1520298B1 (fr) * | 2002-06-28 | 2010-09-29 | Nxp B.V. | Circuit integre pourvu de blocs constitutifs |
US6930510B2 (en) * | 2003-03-03 | 2005-08-16 | Xilinx, Inc. | FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same |
US7068072B2 (en) * | 2003-06-30 | 2006-06-27 | Xilinx, Inc. | Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit |
US7317331B2 (en) * | 2004-11-08 | 2008-01-08 | Tabula, Inc. | Reconfigurable IC that has sections running at different reconfiguration rates |
US7605605B2 (en) * | 2005-01-27 | 2009-10-20 | Cswitch Corporation | Programmable logic cells with local connections |
US7253658B1 (en) * | 2005-06-14 | 2007-08-07 | Xilinx, Inc. | Integrated circuit providing direct access to multi-directional interconnect lines in a general interconnect structure |
US7477073B1 (en) * | 2006-06-16 | 2009-01-13 | Xilinx, Inc. | Structures and methods for heterogeneous low power programmable logic device |
FR2918823B1 (fr) | 2007-07-13 | 2009-10-16 | Ecole Centrale De Lyon Etablis | Cellule logique reconfigurable a base de transistors mosfet double grille |
JP5260077B2 (ja) * | 2008-02-15 | 2013-08-14 | 太陽誘電株式会社 | プログラマブル論理デバイスおよびその構築方法およびその使用方法 |
US7948265B1 (en) * | 2009-04-02 | 2011-05-24 | Xilinx, Inc. | Circuits for replicating self-timed logic |
US8098081B1 (en) * | 2010-06-21 | 2012-01-17 | Xilinx, Inc. | Optimization of interconnection networks |
-
2009
- 2009-12-14 FR FR0958957A patent/FR2954023B1/fr not_active Expired - Fee Related
-
2010
- 2010-12-14 EP EP10805804A patent/EP2514096A1/fr not_active Withdrawn
- 2010-12-14 US US13/512,967 patent/US8742789B2/en not_active Expired - Fee Related
- 2010-12-14 WO PCT/FR2010/052717 patent/WO2011080452A1/fr active Application Filing
- 2010-12-14 JP JP2012543875A patent/JP2013514025A/ja not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
US20120326749A1 (en) | 2012-12-27 |
FR2954023A1 (fr) | 2011-06-17 |
US8742789B2 (en) | 2014-06-03 |
EP2514096A1 (fr) | 2012-10-24 |
JP2013514025A (ja) | 2013-04-22 |
WO2011080452A1 (fr) | 2011-07-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20150831 |