EP0604485B1 - Vorrichtung zur erzeugung von zwischenspannungen - Google Patents

Vorrichtung zur erzeugung von zwischenspannungen Download PDF

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Publication number
EP0604485B1
EP0604485B1 EP92919019A EP92919019A EP0604485B1 EP 0604485 B1 EP0604485 B1 EP 0604485B1 EP 92919019 A EP92919019 A EP 92919019A EP 92919019 A EP92919019 A EP 92919019A EP 0604485 B1 EP0604485 B1 EP 0604485B1
Authority
EP
European Patent Office
Prior art keywords
voltage
voltages
accordance
value
vpos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP92919019A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0604485A1 (de
Inventor
Rudolf Koblitz
Karl Dieter Nutz
Jürgen Steiner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Deutsche Thomson Brandt GmbH
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Deutsche Thomson Brandt GmbH
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Filing date
Publication date
Application filed by Deutsche Thomson Brandt GmbH filed Critical Deutsche Thomson Brandt GmbH
Publication of EP0604485A1 publication Critical patent/EP0604485A1/de
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Publication of EP0604485B1 publication Critical patent/EP0604485B1/de
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/18—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using Zener diodes
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

Definitions

  • the invention relates to a device for generating an intermediate voltage according to the preamble of the main claim and a preferred use according to the preamble of the first use claim.
  • Previously known systems which emit intermediate voltages over a wide range of externally applied voltages, the values of which lie between those of the externally applied voltages, can be implemented, for example, as voltage dividers be. However, they are characterized by a relatively high power loss or by a low dynamic stability, for example by capacitive coupling between epitaxial regions and the substrate.
  • a circuit which can be implemented as part of an integrated circuit and whose power loss is below a predetermined value.
  • a current is controlled by an arrangement of semiconductor components which essentially implement the effect of a Zener diode in such a way that the intermediate voltage does not fall below a predetermined value, i.e. amount does not exceed the specified value.
  • the intermediate voltage generated according to the invention can be used to implement desired circuit functions.
  • the device according to the invention also allows the potential of connections of a component, for example of the substrate connection of a bipolar npn transistor, to such a value that the voltage differences between the individual regions of the component do not exceed predetermined values.
  • connection means such as housing connections or bond connections
  • the device according to the invention is interconnected with a step circuit, for example a cascode circuit, the result is a voltage-proof output stage for controlling further stages.
  • the exemplary embodiment according to FIG. 1 has a first connection terminal 20, to which a positive voltage Vpos is applied, and which is connected to a first connection of a voltage source 21 and a first end of a resistor 22.
  • Vpos has a potential with the represents the highest value occurring in the circuit arrangement under consideration.
  • Vneg which represents the potential with the lowest value occurring in the circuit arrangement under consideration
  • the term “voltage” is also to be understood for other potentials.
  • the second end of the resistor 22 is connected to a first input 23 of a comparison stage 24.
  • a second The input 25 of the comparison stage 24 is connected to a second connection of the voltage source 21.
  • the second end of the resistor 22 and the first input 23 of the comparison stage 24 are connected to the cathode of a Zener diode 26.
  • the anode of this zener diode 26 is connected to a second connection terminal 27 and to a first input of a current source 28.
  • the second connection of this current source 28 is connected to a third connection terminal 29, and a control input of the current source 28 is connected to the output of the comparison stage 24.
  • An intermediate voltage Vzw is available at the second connection terminal 27 and the negative voltage Vneg is applied to the third connection terminal 29.
  • the Zener diode 26 initially blocks, so that only a very small current flows through the resistor 22 and thus only a small voltage drops across it.
  • the Zener diode 26 becomes conductive and a substantially larger current flows through it, through the resistor 22 and through the current source 28, the value of which is predetermined by the current source 28.
  • the value of the intermediate voltage Vzw essentially corresponds to the negative voltage Vneg, ie except for the saturation voltage of the current source 28.
  • the voltage source 21 can be viewed as a setpoint stage, the voltage it outputs as a setpoint voltage, or generally as a setpoint signal, and its value as a setpoint.
  • the comparison stage 24 recognizes that the voltage drop across the resistor is higher than the target voltage, and then outputs a control signal to the current source 28 so that it regulates back the current impressed by it. This sets a current value in such a way that the intermediate voltage Vzw essentially corresponds to the zener diode blocking voltage and the voltage dropping across the resistor 22 corresponds to the voltage output by the voltage source 21.
  • FIG. 3 A second embodiment of the invention is shown in Figure 3. Components were grouped together according to their function. Means, components and assemblies that perform the same function as corresponding means of the embodiment of FIG. 1 have been given the same reference numerals and will be dealt with in the following only to the extent that it is important for the understanding of the present invention.
  • the voltage Vpos present at the first connection terminal 20 is forwarded via the resistor 22 to the first input 23 of the comparison stage 24.
  • the comparison stage 24 contains a first comparison transistor 24a, a second comparison transistor 24b and a comparison resistor 24c connected to the emitter of the first comparison transistor 24a with a first end, the second end of which leads to the first input 23.
  • the collector of the first comparison transistor 24a is connected to the emitter of the second comparison transistor 24b and its collector forms the output of the comparison stage 24.
  • the base of the second comparison transistor 24b is connected to the second connection terminal 27, to which the intermediate voltage Vzw is applied.
  • the transistors 24a, 24b thus form a cascode stage.
  • the first input 23 and the first connection terminal 20 are also connected to a first Zener block 26 ', the function of which corresponds to that of the Zener diode 26.
  • This block 26 ' contains Zener transistors 26a, ..., 26e, and a Zener resistor 26f.
  • a capacitor 31 for frequency response compensation is arranged between the second connection terminal 27 and the output of the comparison stage 24.
  • the current source 28 is formed by a Darlington stage, consisting of a first current source transistor 28a, a second current source transistor 28b and suitable current source resistors 28c, 28d.
  • FIG. 4 connects to the current source 28, the anode of a second Zener block 32, which contains Zener transistors 32a,... 32d, and to the connection terminal 27 of the cathode thereof.
  • This zener block 32 represents a protective circuit in the event that the externally applied voltage (Vpos, Vneg) exceeds predetermined values.
  • the circuit arrangement according to the invention would act as a Zener diode and the voltage applied to the connecting terminals 20, 29 would have a value of 8 ⁇ Vzt + 2 ⁇ V BE limit. It must be ensured that the current through the circuit arrangement does not exceed predetermined values.
  • a third Zener block 33 is provided, the anode of which is connected to the third terminal 29 and the cathode of which is connected to a fourth terminal 34 and a current mirror 35.
  • a voltage Vepi is output to the fourth terminal 34, the value of which is 5 ⁇ Vz above the voltage Vneg.
  • the third zener block 33 is supplied with a small current by the current mirror 35, which contains two transistors 35a, 35b and resistors 35c, 35d.
  • the voltage Vepi is of particular interest when the voltages emitted serve to avoid voltage difference values on a component, such as a resistor, which are above permissible values (V CBO ). Such an application will be discussed further below.
  • a bias voltage stage 36 can be provided in the circuit arrangement according to the invention, which outputs a bias voltage Vvs with a predetermined value, for example V BE + 0.6 volt, based on the intermediate voltage Vzw, to a fourth connection terminal 37.
  • the output voltages generated by the device according to the invention are preferably used to make a further circuit arrangement more voltage-resistant than the voltages Vpos, Vneg applied from the outside.
  • a possible downstream circuit arrangement which, on the one hand, brings the full voltage swing (Vpos, Vneg) to its output terminals and, on the other hand, is implemented in an integrated form and whose manufacturing process is designed for reverse voltages which are below the voltage difference Vpos - Vneg is indicated in FIG. 5 .
  • a cascode stage consisting of a first cascode transistor 41 and a second cascode transistor 42 is shown there.
  • the collector of the first cascode transistor 41 is connected to a first end of a collector resistor 43, the second end of which leads to a first supply connection 44, to which the voltage Vpos is applied.
  • the first Supply terminal 44 is also connected to the emitter of a first driver transistor 45, the base of which leads to a cascode input terminal 46.
  • the collector of the first driver transistor 45 is connected to the emitter of a second driver transistor 47, the base of the first cascode transistor 41 and the base of a further transistor 48, which is also connected to the collector of the transistor 48. Its emitter is connected on the one hand to a second supply connection 49 and to an input of a current mirror 50. Its output leads to the base of the second driver transistor 47, the collector of which is connected to the base of the second cascode transistor 42 and to a first end of a resistor 51, the second end of which leads to the emitter of the transistor 42.
  • the emitter of transistor 42 is connected to an output terminal 52, at which an output voltage V out dependent on the input voltage V in is provided, and to a first end of an emitter resistor 53, which is formed from a series connection of resistors 53 a and 53 b, and the second end thereof End leads to a third supply terminal 54 to which the negative voltage Vneg is applied.
  • the resistors 53a, 53b are, as is customary in an integrated circuit, designed in such a way that regions of a basic diffusion which are embedded in an epitaxial tub, also called a "box", determine the electrical values of the respective resistor.
  • the epitaxial well 55 of the resistor 53b is electrically connected to a fourth supply terminal 56, to which the voltage Vepi is applied.
  • the intermediate voltage Vzw is applied via the fifth supply connection 57.
  • Vout can also assume values that essentially correspond to Vpos, a voltage difference of approximately Vpos-Vneg is then applied to the emitter resistor 53. As assumed, this voltage difference lies above the permissible reverse voltage values, such as V CBO, which are predetermined by the manufacturing process.
  • the emitter resistor 53 can still process the voltage difference in the manufacturing process used, it is divided into the two resistors 53a and 53b, which have the same resistance values in this exemplary embodiment. This causes a voltage drop across both resistors that corresponds to half the voltage difference value (Vpos-Vneg).
  • Vpos-Vneg the voltage difference value
  • the epitaxial well 55 of the resistor 53b is at a voltage value which is at an allowable distance from both the voltage Vpos and the voltage Vneg
  • it is set to a potential corresponding to the voltage Vepi.
  • the voltage Vepi is chosen so that on the one hand the difference to the voltages Vpos and Vneg is not too high and on the other hand their value is not below the intermediate voltage Vzw which is applied to the substrate.
  • the collector connection and thus the epitaxial well of the second cascode transistor 42 a voltage is present which has a value which is above or equal to that of the substrate voltage Vzw.
  • parasitic effects such as the ignition of a parasitic triac, consisting of the substrate, the epitaxial region of transistor 42, the base of transistor 42 and the emitter of transistor 42, can be avoided.
  • a variant of the circuit arrangement of FIG. 5 described so far can contain a fourth zener block 58, as shown in broken lines in FIG. This has a similar structure to the Zener blocks already described and consists of four Zener transistors 58a, ..., 58d.
  • the fourth zener block limits a voltage difference between the collector and the base region of the transistor 42 to a value of 4 * Vzt, where Vzt corresponds to the Zener voltage of the transistors 58a, ..., 58d.
  • the use of the device according to the invention for generating an intermediate voltage is not limited to increasing the dielectric strength of an integrated circuit, but that this is merely a preferred application.
  • the intermediate voltages that increase the dielectric strength of a component can also be output by other suitable devices.
  • the device according to the invention emits an intermediate voltage, the value of which lies between the voltages Vpos, Vneg applied from the outside and which is generated by a current through an arrangement of components which perform the function of a Zener diode (Zener diode 26; Zener block 26 ' ), which is impressed by a controllable current source.
  • the current source is controlled in dependence on comparison values which result from a comparison of a nominal voltage (nominal value) with a voltage dropping at a component which is connected in series with the Zener diode (or the Zener block) and the current source.
  • the device according to the invention is characterized by good dynamic stability with low power loss.
  • the voltages generated are preferably applied to a circuit arrangement implemented using integrated technology, more precisely to individual diffusion regions, which increases the dielectric strength of the integrated circuit.
  • both individual stages which are part of the device for generating intermediate voltages, and downstream stages, are implemented accordingly, for example by cascading or series connection of resistors.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Nonlinear Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Control Of Electrical Variables (AREA)
  • Electronic Switches (AREA)
  • Amplifiers (AREA)
EP92919019A 1991-09-19 1992-09-07 Vorrichtung zur erzeugung von zwischenspannungen Expired - Lifetime EP0604485B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE4131170 1991-09-19
DE4131170A DE4131170A1 (de) 1991-09-19 1991-09-19 Vorrichtung zur erzeugung von zwischenspannungen
PCT/EP1992/002061 WO1993006541A1 (de) 1991-09-19 1992-09-07 Vorrichtung zur erzeugung von zwischenspannungen

Publications (2)

Publication Number Publication Date
EP0604485A1 EP0604485A1 (de) 1994-07-06
EP0604485B1 true EP0604485B1 (de) 1997-08-13

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP92919019A Expired - Lifetime EP0604485B1 (de) 1991-09-19 1992-09-07 Vorrichtung zur erzeugung von zwischenspannungen

Country Status (6)

Country Link
US (1) US5604428A (es)
EP (1) EP0604485B1 (es)
JP (1) JP3381919B2 (es)
DE (2) DE4131170A1 (es)
ES (1) ES2108133T3 (es)
WO (1) WO1993006541A1 (es)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19607802C2 (de) * 1996-03-01 1999-08-19 Temic Semiconductor Gmbh Schaltungsanordnung zum Erzeugen einer Versorgungsspannung
KR100400383B1 (ko) * 1996-03-07 2003-12-31 마츠시타 덴끼 산교 가부시키가이샤 기준 전압원 회로 및 전압 피드백 회로
EP0860762A3 (de) * 1997-02-25 1999-04-07 TEMIC TELEFUNKEN microelectronic GmbH Schaltungsanordnung und Verfahren zum Erzeugen einer Versorgungsgleichspannung
DE19707422C1 (de) * 1997-02-25 1998-08-27 Telefunken Microelectron Verfahren zum Erzeugen einer Versorungsgleichspannung für eine Signalgebereinheit
DE19707423C1 (de) * 1997-02-25 1998-08-13 Telefunken Microelectron Schaltungsanordnung zum Erzeugen einer Versorgungsspannung
EP2328056B1 (en) * 2009-11-26 2014-09-10 Dialog Semiconductor GmbH Low-dropout linear regulator (LDO), method for providing an LDO and method for operating an LDO
US10739800B2 (en) * 2016-07-21 2020-08-11 Hewlett-Packard Development Company, L.P. Regulating an output power of a monitored electronic device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3577167A (en) * 1968-02-29 1971-05-04 Rca Corp Integrated circuit biasing arrangements
AT302488B (de) * 1970-12-14 1972-10-10 Eumig Schaltungsanordnung zur Spannungskonstanthaltung
US3754787A (en) * 1971-12-02 1973-08-28 W Garber Operating support for surgeons
US3887863A (en) * 1973-11-28 1975-06-03 Analog Devices Inc Solid-state regulated voltage supply
DE2437700B2 (de) * 1974-08-05 1979-04-12 Siemens Ag, 1000 Berlin Und 8000 Muenchen Schaltungsanordnung zum Konstanthalten wenigstens zweier, aus einer gemeinsamen Versorgungsgleichspannung abgeleiteten Teilspannungen
US4099775A (en) * 1976-10-07 1978-07-11 Hoover Ball And Bearing Company Chair control with tilt lock
US4323794A (en) * 1980-01-30 1982-04-06 Itt Industries, Inc. Bias voltage generator for a monolithic integrated circuit
DE3303618A1 (de) * 1983-02-03 1984-08-09 Robert Bosch Gmbh, 7000 Stuttgart Schaltungsanordnung zur spannungsregelung
DE3405661A1 (de) * 1984-02-17 1985-08-22 Robert Bosch Gmbh, 7000 Stuttgart Elektronischer spannungsregler
DE3625211A1 (de) * 1986-07-25 1988-02-04 Bosch Gmbh Robert Spannungsregler fuer einen generator
US4774452A (en) * 1987-05-29 1988-09-27 Ge Company Zener referenced voltage circuit
DE3835863A1 (de) * 1988-10-21 1990-07-05 Philips Patentverwaltung Schaltungsanordnung zum ableiten von versorgungsgleichspannungen
DE3920279A1 (de) * 1989-06-21 1991-01-03 Licentia Gmbh Schaltungsanordnung zur erzeugung einer gleichbleibenden ausgangsgleichspannung aus einer veraenderlichen eingangsspannung

Also Published As

Publication number Publication date
DE4131170A1 (de) 1993-03-25
JPH06510875A (ja) 1994-12-01
DE59208798D1 (de) 1997-09-18
US5604428A (en) 1997-02-18
JP3381919B2 (ja) 2003-03-04
EP0604485A1 (de) 1994-07-06
ES2108133T3 (es) 1997-12-16
WO1993006541A1 (de) 1993-04-01

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