EP0598913B1 - Steuerungsverfahren und -schaltung für flüssigkristallelemente und bildanzeigevorrichtung - Google Patents

Steuerungsverfahren und -schaltung für flüssigkristallelemente und bildanzeigevorrichtung Download PDF

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Publication number
EP0598913B1
EP0598913B1 EP93911979A EP93911979A EP0598913B1 EP 0598913 B1 EP0598913 B1 EP 0598913B1 EP 93911979 A EP93911979 A EP 93911979A EP 93911979 A EP93911979 A EP 93911979A EP 0598913 B1 EP0598913 B1 EP 0598913B1
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Prior art keywords
row
voltage
column
electrodes
electrode
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French (fr)
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EP0598913A1 (de
EP0598913A4 (de
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Akihiko Seiko Epson Corporation Ito
Shoichi Seiko Epson Corporation Iino
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Seiko Epson Corp
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Seiko Epson Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G09G3/3625—Control of matrices with row and column drivers using a passive matrix using active addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3681—Details of drivers for scan electrodes suitable for passive matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2011—Display of intermediate tones by amplitude modulation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers

Definitions

  • the present invention relates to a multiplex driving method and a drive circuit of a matrix type liquid crystal electro-optical device such as a liquid crystal display panel, for example.
  • the present invention further relates to a liquid crystal display device.
  • Multiplex driving based on the amplitude selective addressing scheme is one known driving method for liquid crystal devices such as those referred to above (known from e.g. EP-A-0 349 415 and EP-A-0 479 450).
  • Fig. 45 is an applied voltage waveform diagram showing one example of a prior art driving method of multiplex driving a simple matrix type liquid crystal electro-optical device as shown in Fig. 46 by means of an amplitude selective addressing scheme;
  • Fig. 45 (a) and (b) are the voltage waveforms applied to row electrodes X 1 , X 2 , respectively,
  • Fig. 45 (c) is the voltage waveform applied to column electrode Y 1
  • Fig. 45 (d) is the voltage waveform applied to the pixel at the intersection of row electrode X 1 and column electrode Y 1 .
  • This example sequentially selects row electrodes X 1 , X 2 ,..., X n , one at a time, and depending on whether each pixel on the selected row electrode is ON or OFF applies a corresponding column voltage waveform to each of the column electrodes Y 1 , Y 2 ,..., Y m .
  • Fig. 47 is an applied voltage waveform diagram showing an example of this prior art driving method of simultaneously selecting and driving plural row electrodes, Fig. 47 (a) being the row voltage waveforms applied to the row electrodes X 1 , X 2 , and X 3 , (b) the row voltage waveforms applied to row electrodes X 4 , X 5 , and X 6 , (c) the column voltage waveform applied to column electrode Y 1 , and (d) the voltage waveform applied to the pixel at the intersection of row electrode X 1 and column electrode Y 1 .
  • This example simultaneously selects three sequential row electrodes (or lines) at a time for a display pattern as shown in Fig. 46. Specifically, three row electrodes X 1 , X 2 , and X 3 are first selected by row voltages as shown in Fig. 47 (a) applied to these row electrodes X 1 , X 2 , and X 3 , and a specified column voltage is simultaneously applied to each of the column electrodes Y1 to Y m as described in more detail below. Next, row electrodes X 4 , X 5 , and X 6 in Fig. 46 are selected by row voltages such as shown in Fig. 47 (b) applied as described above, and a column voltage is simultaneously applied to each of the column electrodes Y 1 to Y m .
  • the row select patterns i.e., when a positive pulse of a voltage waveform applied to a row electrode is defined as an ON state and a negative pulse as an OFF state, the voltage ON/OFF patterns applied to the three simultaneously selected row electrodes X 1 , X 2 , and X 3 are shown in the following table using values of 1 and 0 to represent an ON state and an OFF state, respectively.
  • X 1 0 0 0 0 1 1 1 1 1 X 2 0 0 1 1 0 0 1 1 X 3 0 1 0 1 0 1 0 1 0 1 0 1 0 1
  • Fig. 48 (a) The voltage waveforms generated based on these values for application to the row electrodes are shown in Fig. 48 (a).
  • the waveforms shown in Fig. 48 (a) contain several different frequency components, which can result in display ununiformity when applied.
  • Waveforms modified by reordering the row select patterns in the array shown above to reduce the differences in the frequency components are shown in Fig. 48 (b).
  • the prior art example shown in Fig. 47 also uses these waveforms.
  • the column voltages applied to each of the column electrodes Y 1 to Y m have the same number of patterns as the row voltages, and the voltage level of each pulse in the column voltage waveform has a value corresponding to the ON/OFF states of the selected row electrodes.
  • an ON state is when the row voltage waveform applied to any of the simultaneously selected row electrodes X1, X2, and X3 is a positive pulse and an OFF state is when it is a negative pulse.
  • the ON/OFF states of the display data (the display data pattern) for the pixels formed at the intersections of the column electrode and each of the simultaneously selected row electrodes, are compared pixel by pixel or bit by bit with the ON/OFF states of the selected row electrodes, and the level of the column voltage waveform is set according to the number of mismatches.
  • pulse voltages -V Y2 , -V Y1 , V Y1 , and V Y2 are applied when the number of mismatches is 0, 1, 2, and 3, respectively.
  • V X1 corresponds to ON and -V X1 to OFF in the voltage waveforms applied to row electrodes X1, X2, and X3 in Fig. 47
  • ON and OFF pixels are represented with a solid and a white dot, respectively, in Fig. 46
  • the pixels at the intersections of row electrodes X 1 , X 2 , and X 3 and column electrode Y 1 are ON-ON-OFF, respectively, and the initial row select pattern of the voltage applied to these row electrodes X 1 , X 2 , and X 3 is OFF-OFF-OFF.
  • voltage V Y1 as shown in Fig. 47 (c) is applied as the first pulse to the column electrode Y 1 .
  • the second row select pattern of the voltage applied to the row electrodes X 1 , X 2 , and X 3 is OFF-OFF-ON; because each of these is a mismatch when compared sequentially with the previous ON-ON-OFF display data pattern and the number of mismatches is therefore three, voltage V Y2 is applied as the second pulse to column electrode Y 1 .
  • V Y1 is applied as the third pulse, -V Y1 as the fourth pulse, and the following pulses are, in sequence, -V Y2 , V Y1 , -V Y1 , -V Y1 .
  • the next group of three row electrodes X 4 to X 6 are then selected, and when the voltages shown in Fig. 47 (b) are applied to these row electrodes X 4 to X 6 , a column voltage of the voltage level corresponding to the number of mismatches between the ON/OFF states of the pixels at the intersections of row electrodes X 4 to X 6 and the column electrode, i.e. the display data pattern, and the ON/OFF states of the voltages applied to the row electrodes X 4 to X 6 , i.e. the row select pattern, is applied as shown in Fig. 47 (c).
  • the values 1 and 0 are used for the positive and negative selection pulses, respectively, of the row voltage waveforms, and 1 and 0 are used for the ON and OFF display data states of pixels, respectively, and the column voltage waveform is set according to the number of mismatches
  • the values of 1 and 0 can be exchanged for each other and further the column voltage waveform can also be set according the number of matches or according to the difference between the number of matches and the number of mismatches.
  • this method of simultaneously selecting and driving plural sequential row electrodes allows to reduce the drive voltage while achieving the same on/off contrast ratio as the single line selection method explained with reference to Fig. 45.
  • the number of Ci is determined by the number of bits in one word, and not by the row select pattern.
  • V pixel (V column - V row ) or (V row - V column ) where V row is the row voltage and V column is the column voltage.
  • V pixel +Vr - V (i) or -Vr - V (i)
  • V pixel Vr - V (i) , Vr + V (i) , -Vr - V (i) , or -Vr + V (i) .
  • V pixel V r - V (i) or V r + V (i) .
  • the voltage applied to a given pixel be as high as possible with ON pixels and as low as possible with OFF pixels.
  • V pixel V row - V column will decrease with the increase in the number of mismatches.
  • the number of mismatches will provide the number of unfavorable voltages (column voltages).
  • Ci ⁇ (h-i)/h ⁇ ⁇ Ci
  • Ci Ci
  • Ci - Bi ⁇ (h-1)! ⁇ / ⁇ i ⁇ (h-i-1)! ⁇ where h ⁇ i + 1.
  • V ON (rms) ⁇ (S 1 + S 2 + S 3 ) / S 4 ⁇ 1/2
  • V OFF (rms) ⁇ (S 5 + S 6 + S 3 ) / S 4 ⁇ 1/2
  • Vr/V (o) N 1/2 /h row selection voltage
  • the object of the present invention is to provide a driving method and a drive circuit of a matrix type liquid crystal device, and a liquid crystal display device capable of achieving a good gray scale display even when simultaneously selecting and driving plural row electrodes.
  • This object is achieved with a driving method, a driving circuit and a display device, respectively, as claimed.
  • the above gray scale display can be achieved simply and reliably.
  • the display device provides a good gray scale display with little chance of crosstalk being generated.
  • Fig. 1 is an applied voltage waveform diagram used to describe the first embodiment of a driving method according to the present invention
  • Fig. 1 (a) being the voltage waveforms applied to row electrodes X 1 , X 2 , and X 3
  • (b) being the voltage waveforms applied to row electrodes X 4 , X 5 , and X 6
  • (c) being the voltage waveform applied to column electrode Y 1
  • (d) being the (composite) voltage waveform applied to the pixel at the intersection of row electrode X 1 and column electrode Y 1 .
  • the present embodiment simultaneously selects three sequential row electrodes to achieve the display as shown in Fig. 2.
  • a type waveforms shown in Fig. 48 (a) or (b) can be used as the voltage waveforms applied to the simultaneously selected row electrodes, a type of waveforms as shown in Fig. 1 (a) is used in this embodiment.
  • each pulse width becomes narrower.
  • the pulse width would be even narrower, resulting in crosstalk.
  • the voltage waveforms applied to the row electrodes are set as described below so that the pulse width is wider.
  • the voltage waveforms applied to the row electrodes are decided based on the conditions that:
  • the pattern of the applied voltages is appropriately determined from a natural binary, Walsh, Hadamard, or other systems of orthogonal functions considering the above conditions.
  • the first is absolute. To satisfy this condition the voltage waveforms applied to each row electrode are generated so that they are orthogonal to each other.
  • the applied voltage waveforms shown in Figs. 3 (a) and (b) were determined considering the above conditions.
  • the applied voltage waveforms in Fig. 3 (a) contain different frequency components, namely X 1 : 4 ⁇ t o X 2 : 4 ⁇ t o , 2 ⁇ t o X 3 : 2 ⁇ t o .
  • the applied voltage waveforms in Fig. 3 (b) contain different frequency components, namely X 1 : 4 ⁇ t o , 2 ⁇ t o X 2 : 4 ⁇ t o , 2 ⁇ t o X 3 : 6 ⁇ t o , 2 ⁇ t o .
  • Fig. 3 (a) and (b) are one example and can be changed as appropriate, and that the row electrode selection sequence and sequence of the row select patterns applied to the row electrodes can also be changed using the properties of the systems of orthogonal functions.
  • the row voltage waveforms shown in Fig. 1 (a) and (b) form the voltage waveforms applied to the three simultaneously selected row electrodes based on the waveform in Fig. 3 (b).
  • the selection period is divided into four separate selection subperiods t 1 , t 2 , t 3 , t 4 in each frame.
  • Each of the selection subperiods t 1 , t 2 , t 3 , t 4 divided as described above is subdivided into plural intervals as shown in Fig. 1 (c), and in each of these intervals a weighted voltage is applied to the column electrodes Y1 to Y m to obtain a desired display.
  • subperiod t 1 is subdivided into two equal intervals a and b.
  • the display data for each pixel are composed of two bits representing a binary code for a gray scale display with four gradations.
  • a column voltage specifically weighted for each bit based on the display data shown in Fig. 2 is applied, during interval a for the high or most significant bit and during interval b for the low or least significant bit as shown in Fig. 1.
  • V X1 applied to a row electrode represents the ON states and -V X1 the OFF state
  • the display data value 0 represents OFF and 1 ON
  • the ON/OFF states of the simultaneously selected row electrodes and the ON/OFF state of the display data are compared bit by bit to calculate the number of mismatches
  • the voltages applied for the high bit when the number of mismatches is 3, 2, 1, and 0, respectively are V Y4 , V Y2 , -V Y2 , and -V Y4
  • the voltages applied for the low bit when the number of mismatches is 3, 2, 1, and 0, respectively are V Y3 , V Y1 , -V Y1 , and -V Y3 .
  • the selected pulses applied to row electrodes X 1 , X 2 , and X 3 are ON, ON, OFF, respectively, and the display data for the pixels at the intersections of column electrode Y 1 and row electrodes X 1 , X 2 , and X 3 are (00), (01), (10), i.e. the high bits represent OFF, OFF, ON.
  • Comparison shows the number of mismatches is three, and voltage V Y4 is therefore applied to the column electrode Y 1 in interval a. Since the low bits represent OFF, ON, OFF, the number of mismatches compared with the row select pattern is one, and voltage -V Y1 is therefore applied in interval b.
  • the display data for the pixels on the row electrodes X 1 , X 2 , and X 3 is compared with the selected pulses applied to the row electrodes (the row select pattern), and a column voltage corresponding to the number of mismatches is applied.
  • row electrodes X 4 , X 5 , and X 6 are simultaneously selected and the corresponding column electrode waveforms are applied to the column electrodes.
  • the operation returns to the first group of row electrodes X 1 , X 2 , and X 3 and the specified voltages are sequentially applied following the above sequence in subperiods t 2 , t 3 , and t 4 .
  • a good gray scale display with minimal crosstalk can thus be achieved by driving as described above.
  • the sequence of the row voltage waveforms applied to the row electrodes in the above subperiods t 1 to t 4 can be changed for all frames or in single frames, and the waveforms shown in Fig. 3 (a) or other waveforms satisfying the conditions described above can be used as the row voltage waveforms applied to the row electrodes.
  • two kinds of waveforms can be alternately used for each group of simultaneously selected row electrodes, for example the kind of waveforms shown in Fig. 3 (a) for row electrodes X 1 to X 3 and the kind of waveforms shown in Fig. 3 (b) for row electrodes X 4 to X 6 , or a sequence of three or more kinds of waveforms can be used alternately.
  • the subperiods t 1 to t 4 can be separate in each frame period as in the above embodiment, or can be consecutive in each frame, if the subperiods of the selection period are separate, i.e. distributed within one frame as in the present embodiment, the period during which a row electrode continuously stays unselected becomes shorter and the contrast can be improved.
  • the selection period is divided into four subperiods t 1 to t 4 in the above embodiment, any number of divisions can be used; further, each of the subperiods t1 to t4 can be subdivided into two intervals as explained above, or it can be subdivided into more than two intervals allowing more gradations.
  • row electrodes sequential in position, are selected at a time in the above embodiment, but the number of the selected row electrodes can be any appropriate number and the row electrodes forming a group of simultaneously selected row electrodes do not necessarily need to be sequential in position.
  • a drive circuit executing the driving method described above is described based on Figs. 4 to Fig. 6.
  • Fig. 4 is a block diagram showing one example of a drive circuit.
  • 1 is a row electrode driver
  • 2 is a column electrode driver
  • 3 is a frame memory
  • 4 is an arithmetic operation circuit
  • 5 is a row data generating circuit
  • 6 is a latch.
  • Fig. 5 is a block diagram of the row electrode driver
  • Fig. 6 is a block diagram of the column electrode driver
  • 11 and 21 are shift registers
  • 12 and 22 are latches
  • 13 and 33 are decoders
  • 14 and 24 are level shifters.
  • each row electrode waveform is generated based on a scan data signal S3 indicating a positive selection, negative selection, or no selection, the scan data signal being generated from the row data generating circuit 5 and sent to the row electrode driver 1.
  • the scan data signal S3 from the row data generating circuit 5 is sent to the shift register 11 at the scan shift clock signal S5, and after the data for each of the row electrodes in one scanning period have been entered into the shift register, the data are latched in the latch 12 at latch signal S6, the data expressing the state of each row electrode are then decoded by decoder 13, and the decoded outputs are used, via level shifter 14, to switch on one of three analog switches 15 provided for each output, and voltage V X1 , -V X1 , or 0 is selected and output to the respective row electrode when the selection is positive, negative, or no selection, respectively.
  • the display data signal S1 for the three simultaneously selected row electrodes X 1 , X 2 , and X 3 is read from frame memory 3, and the display data signal S1 and scanning data signal S3, latched in latch 6, are converted by the arithmetic operation circuit 4. This data conversion is performed as described above, and the converted data are transferred to the column electrode driver 2 as column data signal.
  • the column data signal S2 from the arithmetic operation circuit 4 is sent to shift register 21 at shift clock signal S7, and after the data for each column electrode in one scanning period have been input, the data are latched in latch 22 at the latch signal S8, the data expressing the state of each column electrode are then decoded by decoder 23 whose outputs are used, via level shifter 24, to switch on one of the eight analog switches 25 provided for each output, and one of the eight voltages V Y4 , V Y3 , V Y2 , V Y1 , -V Y1 , -V Y2 , -V Y3 , and -V Y4 is output to each column electrode.
  • a driving method as described above can thus be simply and reliably achieved by using a drive circuit as described above.
  • a display apparatus comprising a display device as described above comprises a drive circuit as described above to execute the driving method as described above, a display apparatus capable of achieving a good gray scale display with minimal crosstalk generated can be achieved.
  • one of four voltages is selected according to the display data and applied to the column electrodes for each bit of the display data, but by providing a virtual electrode the number of voltage levels applied to the column electrodes can be reduced.
  • Fig. 7 is a voltage waveform diagram for an embodiment that is capable of driving by a reduced number of voltage levels applied to the column electrodes by providing a virtual row electrode in each group of simultaneously selected row electrodes
  • Fig. 8 illustrates the basis for reducing the number of voltage levels applied to the column electrodes by providing a virtual electrode.
  • This embodiment provides, for example, virtual row electrodes X n+1 , X n+2 ,... each after a corresponding group of simultaneously selected row electrodes as shown in Fig. 8, such that virtual row electrode X n+1 is selected simultaneously with row electrodes X 1 , X 2 , and X 3 , for example.
  • the number of mismatches is calculated as in the first embodiment assuming voltage V X1 is applied to the row electrode in each ON state, -V X1 is applied in each OFF state, and the display data value 0 represents OFF and 1 ON. In this case, the number of mismatches is always 1 or 3 by appropriately changing the ON/OFF state of the virtual row electrode.
  • the display shown in Fig. 2 is achieved by the waveforms in Fig. 7 applying the above principle.
  • the selected pulses applied to row electrodes X 1 , X 2 , X 3 and virtual row electrode X n+1 are ON, ON, OFF, ON, respectively
  • the display data for the pixels at the intersections of column electrode Y 1 and row electrodes X 1 , X 2 , X 3 and virtual row electrode X n+1 are (00), (01), (10), (11), and the high bits represent OFF, OFF, ON, ON.
  • Sequential comparison shows the number of mismatches is three; conversion data S2 is therefore generated according to this number of mismatches, and voltage V Y2 is therefore applied to the column electrode Y 1 in interval a.
  • the low bits represent OFF, ON, OFF, ON, and the number of mismatches if compared with the row select pattern is one; conversion data S2 is therefore generated according to this number of mismatches, and voltage -V Y1 is therefore applied in period b.
  • the display data for the pixels on the row electrodes X 1 , X 2 , X 3 and virtual electrode X n+1 i.e. the display data pattern
  • the selected pulses applied to the row electrodes i.e. the row select pattern
  • a column voltage corresponding to the number of mismatches is applied.
  • row electrodes X 4 , X 5 , X 6 and virtual row electrode X n+2 are simultaneously selected and the corresponding column electrode waveforms are applied to the column electrodes.
  • the operation returns to the first group of row electrodes X 1 , X 2 , and X 3 and sequential scanning using the row select pattern shown in t 2 continues.
  • One frame period is completed by scanning four times with the row select patterns shown in t 1 , t 2 , t 3 , and t 4 , and the same operation is repeated in the next frame.
  • the number of voltage levels applied to the column electrodes can be made less than that of the first embodiment.
  • the same drive circuit as that used in the first embodiment can be used in the present embodiment and each of the embodiments described below.
  • the arithmetic operation circuit 4 in Fig. 4 is adapted to execute data processing according to each of the embodiments, the voltage levels of the row electrode driver in Fig. 5 and the column electrode driver in Fig. 6 are provided according to each embodiment, and one of the voltage levels is selected by analog switches 15, 25.
  • the arithmetic operation circuit 4 in Fig. 4 and the row electrode driver in Fig. 5 are the same as those of the first embodiment, but while eight voltage levels V Y4 , V Y3 , V Y2 , V Y1 , -V Y1 , -V Y2 , -V Y3 , and -V Y4 are provided in the column electrode driver of the first embodiment in Fig. 6, it is sufficient to provide four voltage levels V Y2 , V Y1 , -V Y1 , and -V Y2 in the present embodiment.
  • the above embodiment achieves a gray scale display by changing the voltage value according to the display data, but a gray scale display can also be achieved by changing the pulse width.
  • Fig. 9 is an applied voltage waveform diagram of an embodiment achieving a gray scale display by changing the pulse width.
  • the period ⁇ t of each pulse is divided into f subperiods of unequal duration to achieve a gray scale display by means of pulse width modulation.
  • the display data is then represented by f bits:
  • the row select pattern and the display data pattern are then compared bit by bit, separately for each bit position of the display data, at an interval of ⁇ t g .
  • the low or least significant bits (d 1,1 , d 2.1, ...) of the display data pattern (d 1 , d 2 ,%) and the bits of the row select pattern are first compared and column voltage waveforms corresponding to the result is applied for display for subperiod ⁇ t 1 .
  • next to least significant bits d 1,2 , d 2.2 ,... and the row select pattern are then compared and corresponding column voltage waveforms applied for subperiod ⁇ t 2 .
  • Fig. 9 based on the present embodiment achieves a four gradation gray scale display as shown in Fig. 2 using pulse width modulation as described above.
  • the row voltage waveforms applied to the row electrodes X 1 to X n are the same as in the prior art example illustrated in Fig. 47, and the pulse widths of the column voltage waveforms applied to the corresponding column electrodes Y 1 to Y m are modulated according to the gray scale display as above.
  • each pulse width ⁇ t is divided into three equal parts, and a gray scale display with four gradations 0 to 3 is expressed using the 2-bit binary display data expressions (00), (01), (10), (11).
  • the signal voltage level of two of the three pulse width parts is determined based on the number of mismatches between the ON/OFF state of the simultaneously selected row electrodes and the high bit states of the display data pattern.
  • the signal voltage level of the remaining one part is determined based on the number of mismatches between the ON/OFF state of the row electrodes and the low bit states. Variations in the brightness of the gray scale display can be corrected by equally reducing the three parts.
  • the voltage for the high bit is applied during the latter two of the three pulse width parts, and the voltage for the low bit is applied during the first of the three pulse width parts.
  • the selection period can also be divided into plural separate selection subperiods each frame as described in the first embodiment above to drive a gray scale display.
  • FIG. 11 An example of such application is shown in Fig. 11.
  • the voltage waveforms of eight row select patterns (blocks) applied to the row electrodes and column electrodes in the embodiment shown in Fig. 9 are divided into eight equal selection subperiods one for each row select pattern.
  • the contrast can be improved as in the previous embodiment.
  • the four voltage levels V Y2 , V Y1 , -V Y1 , and -V Y2 are used as the column electrode voltage levels in the third and fourth embodiments above, but this number of voltage levels can be further reduced by providing virtual row electrodes as in the second embodiment.
  • Fig. 12 shows an example that makes use of the virtual electrodes of the third embodiment to reduce the number of voltage levels applied to a column electrode, and is driven by dividing the selection period in to plural separate selection subperiods within each frame as in the fourth embodiment.
  • e column electrodes are operated as virtual row electrodes (virtual lines).
  • virtual row electrodes virtual lines.
  • V column has h + 1 levels.
  • Original voltage level Original number of mismatches
  • Virtual row electrode Number of mismatches after correction Voltage level after correction -V Y2 0 Match 0 V a -V Y1 1 Mismatch 2 V b V Y1 2 Match 2 V b V Y2 3 Mismatch 4 V d
  • the original four voltage levels can be reduced to three. If the number of mismatches is controlled to be odd, the number of mismatches after correction will change in the above table to 1, 1, 3, 3 (from the top), and there will be only two voltage levels (Va, Va, Vb, Vb from the top) after correction.
  • the original number of voltage levels can thus be reduced from five to three. Note that the voltage levels can also be set by controlling the number of mismatches to be odd.
  • the virtual row electrodes can be provided in an area not affecting the display.
  • the virtual row electrodes X n+1 are provided outside the display area R as defined in Fig. 13.
  • any extra row electrodes outside the normal display area R can also be used as virtual row electrodes.
  • the number of voltage levels can be further reduced by increasing the number e of virtual row electrodes.
  • the present embodiment as shown in Fig. 12 simultaneously selects three row electrodes and one virtual electrode to reduce the number of voltage levels applied to the column electrodes, and drives by dividing the selection period into plural separate subperiods in each frame.
  • the present embodiment divides the selection period into four separate subperiods a frame, and the number of mismatches between the row select pattern and the display data pattern is counted bit by bit for four row electrodes, including the virtual row electrode, in each of the four subperiods to adjust the number of mismatches to an odd number.
  • the number of mismatches is thus either 1 or 3, and the voltage level of the column voltage waveform is therefore one of two levels, V Y1 or -V Y1 .
  • the virtual row electrode X n+1 even though shown outside of the display area R, is part of the first group of simultaneously selected row electrodes including the first three selected row electrodes X 1 , X 2 , and X 3 and the virtual row electrode X n+1 as shown in Fig. 8. Again, it is not essential for the virtual row electrode to be actually existent, but when it exists, it is preferably provided outside the display area R.
  • each of the selection subperiods ⁇ t is subdivided into three intervals, and the display data for the pixels on the simultaneously selected row electrodes X 1 , X 2 , and X 3 is (00), (01), (10) as shown in Fig. 13, then the display data for the virtual row electrode is (11) as shown in Fig. 8.
  • the number of mismatches between the row select pattern and the display data pattern is then counted separately for each bit position (high and low in case of 2-bit display data) to determine either voltage level V Y1 or -V Y1 , and the voltages for the high bits are applied for the latter two of the three intervals and the voltage for the low bit is applied for the first one interval. Note that, as in the third embodiment, it is also possible to apply the voltages for the high bits in the first two intervals and to apply the voltages for the low bits in the last one interval.
  • the present embodiment can reduce the number of voltage levels applied to the column electrodes, specifically to two in the above embodiment, by always setting the number of mismatches between the display data pattern and the row select pattern to 1, 3, or some other odd number. Note that an even number of mismatches can be alternatively used.
  • a display with a larger number of gradations is also possible.
  • eight gradations can be achieved by using 3-bit display data and subdividing each selection period or subperiod into three intervals the width of each weighted according to the position of a corresponding one of the display data bits.
  • a display with 16 gradations can be achieved by using 4-bit display data and subdividing each selection period or subperiod into four correspondingly weighted intervals.
  • different numbers of gradations of a gray scale display are possible by adapting the number of intervals each selection period or subperiod is subdivided into.
  • the above described fifth embodiment employs the type of voltage waveforms shown in Fig. 48 (b).
  • providing virtual row electrodes as in the fifth embodiment above to reduce the number of voltage levels applied to the column electrodes while also using pulse width modulation to achieve a gray scale display can also be applied to the case wherein the same type of row voltage waveforms as in the first embodiment is applied to the simultaneously selected row electrodes, and an example of this is shown in Fig. 14.
  • the voltage waveforms applied to the simultaneously selected row electrodes are the same as that of the first embodiment shown in Fig. 1, and each of the selection subperiods t 1 to t 4 , t 5 to t 8 is subdivided into three intervals.
  • the display data for the pixels on the simultaneously selected row electrodes X 1 , X 2 , and X 3 are (00), (01), (10) as shown in Fig. 13, the data of the virtual row electrode may be (11) as shown in Fig. 8.
  • V Y1 or -V Y1 is applied as the voltage for the high bits in two of the three intervals and the voltage for the low bits in one interval.
  • selection subperiods t 1 to t 4 may be provided consecutively (forming one continuous selection period) or separately in each frame F. The same is true of selection subperiods t 5 to t 8 .
  • a gray scale display by means of a so-called frame rate control modulation is also possible in addition to dividing the selection period and reducing the number of applied voltage levels as described above, and Fig. 15 shows an embodiment wherein the number of voltage levels applied to the column electrodes is reduced using three sequential row electrodes and one virtual row electrode similarly to the sixth embodiment, the selection period is divided into plural separate subperiods each frame, and a gray scale display is achieved by means of frame rate control modulation.
  • waveforms shown in Fig. 3 (b) are used as the voltage waveforms applied to the simultaneously selected row electrodes in this embodiment, the waveforms shown in Fig. 3 (a) or Fig. 48 (a) or (b) can also be used.
  • a gray scale display based on frame rate control modulation turns pixels ON in some frames and OFF in other frames during any given picture period, and in the example shown in Fig. 16, a gradation between on and off is displayed by applying an ON voltage during one frame F1 and an OFF voltage during another frame F2 assuming a picture period comprising two frames.
  • the brightness difference between frames F1 and F2 is reduced and flicker becomes less noticeable because the selection period is divided into four separate subperiods each frame.
  • the position of the selection pulses i.e. the row select pattern
  • the position of the selection pulses can be changed within the plural frames, and the difference between frames can be reduced by interchanging the row select patterns of subperiods t 3 and t 7 , for example, in Fig. 15.
  • a picture period may be defined to have a block of more frames, for example 7 (15) frames, to achieve 8 (16) gradations by changing the number of ON and OFF frames within the block.
  • a display with the desired number of gradations is possible depending on the number of frames of one block.
  • a gray scale display by means of frame rate control modulation is also possible in addition to dividing the selection period into separate subperiods and reducing the number of applied voltage levels as in the fifth embodiment above, and Fig. 17 shows an embodiment in which the number of voltage levels applied to the column electrodes is reduced using three sequential row electrodes and one virtual row electrode similarly to the fifth embodiment the selection period is divided into plural subperiods each frame, and a gray scale display is achieved by means of frame rate control modulation in combination with pulse width control.
  • Display flicker can be reduced and a multiple gray scale display can be achieved by thus dividing the selection period and reducing the number of applied voltage levels, and combining pulse width modulation with frame rate control modulation for the gray scale display. Note also that the order of the row select patterns can be changed as in the sixth embodiment above.
  • a gray scale display can still be achieved by means of frame rate control modulation or by a combination of frame rate control modulation and pulse width modulation even when no virtual row electrode is used.
  • Fig. 19 is the column electrode waveform when the display data for the pixels at the intersections of the row electrodes X 1 , X 2 , and X 3 and column electrode Y 1 are (001), (010), (100) and the row electrode waveform applied to each of the row electrodes in Fig. 2 is the same as that of the first embodiment.
  • the four selection subperiods t 1 to t 4 in the first embodiment are each subdivided into three equal intervals a, b, c, and the voltage waveform corresponding to the highest of the three display data bits is applied in the first interval a, the voltage waveform corresponding to the middle bit is applied in the next interval b, and the voltage waveform corresponding to the lowest bit is applied in the last interval c; each of these voltage waveforms is weighted according to each of the display data bits as in the first embodiment.
  • one of the voltages -V Y6 , -V Y4 , V Y4 , or V Y6 is selected for interval a according to the highest display data bit
  • one of the voltages -V Y5 , -V Y2 , V Y2 , or V Y5 is selected for interval b according to the middle display data bit
  • one of the voltages -V Y3 , -V Y1 , V Y3 , or V Y1 is selected for interval c according to the lowest display data bit.
  • a gray scale display with eight gradations can be achieved in a manner corresponding to that in the first embodiment by generating the column electrode waveforms based on the number of mismatches calculated separately for each bit position of the display data pattern.
  • a gray scale display with four gradations is obtained in the first embodiment by selecting a voltage for each of the two equal intervals into which the selection subperiod is subdivided, and applying this voltage to the column electrode, but in the present embodiment eight gradations are obtained by subdividing the selection subperiod into three equal intervals.
  • sixteen gradations can be obtained by subdividing the selection period or subperiod into four equal intervals, and, as this indicates, the number of gradations can be increased by appropriately subdividing the selection period or subperiod into plural intervals and applying a voltage selected for each of these intervals to the column electrode.
  • the brightness level of each gradation can be adjusted by changing the ratio of the voltages applied to each column electrode, or by slightly changing the duration of each interval instead of using equal intervals.
  • a voltage is applied according to each bit of the multi-bit display data, in sequence from the high or most significant bit in the intervals a, b, c, divided according to the number of display data bits, but this sequence can be appropriately changed for each column electrode.
  • the column voltage waveforms applied to the column electrodes Y1 to Y m will all be identical to the waveforms shown in Fig. 19. However, rounding of the waveform applied to each pixel becomes great in this case, and display quality deteriorates.
  • the voltage corresponding to the highest of the three display data bits is applied in sequence to column electrode Y 1 during interval a in Fig. 20, the voltage corresponding to the middle bit during interval b, and the voltage corresponding to the lowest bit during interval c.
  • the same is true of the other column electrodes Y 1 to Y m .
  • the order is changed for the next column electrodes, for example to (a, c, b) for column electrode Y 2 , (b, a, c) for column electrode Y 3 , (b, c, a) for column electrode Y 4 , (c, a, b) for column electrode Y 5 , and (c, b, a) for column electrode Y 6 , and similar combinations are repeated for Y 7 to Y m .
  • any combination of waveforms applied to the column electrodes can used such that, for example, if there are six column electrode drivers, each combination of waveforms is applied to each column electrode driver.
  • display quality can be improved if the number of rounding rises and falls cancel each other in the combination of waveforms applied to the respective column electrodes.
  • a gray scale display with eight gradations is obtained using a type of waveform as shown in Fig. 1 (a), i.e. as shown in Fig. 3 (b), as the row voltage waveforms applied to the row electrodes, but the type of waveforms shown in Fig. 3 (a) or in the Fig. 48 (a) or (b) for the prior art method can also be used.
  • the case wherein the waveforms shown in Fig. 3 (a) are used for an eight gradation gray scale display is described in further detail below.
  • Fig. 21 is an applied voltage waveform diagram of the embodiment achieving a eight gradations based on the display data shown in Fig. 22 and using the type of waveforms shown in Fig. 3 (a) as the row voltage waveforms applied to the row electrodes.
  • Fig. 21 (a) shows the row voltage waveforms applied to row electrodes X 1 , X 2 , and X 3
  • Fig. 21 (c) is the column voltage waveform applied to column electrode Y 1
  • Fig. 21 (d) is the voltage waveform applied to the pixel at the intersection of row electrode X 1 and column electrode Y 1 .
  • This embodiment also simultaneously selects three sequential row electrodes, and while only the three row electrodes X 1 , X 2 , and X 3 are shown in Fig. 21, the next three row electrodes X 4 , X 5 , and X 6 are selected after row electrodes X 1 , X 2 , and X 3 have been selected as shown in Fig. 23, and voltages are applied to these electrodes similarly to row electrodes X 1 , X 2 , and X 3 . Thereafter, the next row electrodes are selected in order, three at a time, and one frame ends when all row electrodes have been selected.
  • the minimum pulse width ⁇ t is twice the minimum pulse width ⁇ t o of the prior art method shown in Fig. 48 as described above, and all selection periods t for each of the row electrodes in a frame comprise four subperiods t 1 to t 4 of length ⁇ t.
  • the above four subperiods t 1 to t 4 are each subdivided into three intervals a, b, c according to the number of bits of display data, and a column voltage specifically weighted according to the bits of the display data is applied to the each column electrode in each of these intervals.
  • the high bit of the display data which is expressed as a three digit binary number as shown in Fig.
  • the middle bit corresponds to the next interval b
  • the low bit corresponds to the last interval c
  • the specifically weighted voltage ⁇ V Y4 or ⁇ V Y6 is applied according to the conditions described below for the high bit
  • ⁇ V Y2 or ⁇ V Y5 is applied for the middle bit
  • ⁇ V Y1 or ⁇ V Y3 is applied for the low bit.
  • ON represents the state when the voltage waveform applied to a row electrode is positive and OFF when it is negative, and a display data value of 1 represents ON and 0 represents OFF; the ON/OFF state of each of the simultaneously selected row electrodes and the ON/OFF state of the corresponding display data bit at the intersection of each selected row electrode and the column electrode to which the voltage is to be applied are compared for each bit position as explained in more detail above, and a voltage specified according to the number of mismatches is applied to the column electrode.
  • the three row electrodes X 1 , X 2 , and X 3 are first selected, and during selection subperiod t 1 the selected row electrodes X 1 , X 2 , and X 3 are OFF, OFF, ON, respectively, and the high bits of the display data at the intersections of the column electrode Y 1 and these row electrodes X 1 , X 2 , and X 3 are OFF, ON, ON.
  • the number of mismatches is 1, and the voltage - V Y4 is applied to column electrode Y 1 in the first interval a of the first subperiod t 1 .
  • a weighted voltage is simultaneously applied to the other column electrodes Y 2 to Y m in the same manner.
  • the ON/OFF state of row electrodes X 1 , X 2 , and X 3 is the same OFF, OFF, ON, and the middle bits corresponding to this interval b are, in order, ON, OFF, OFF; the number of mismatches is therefore 2, and voltage V Y2 is applied.
  • the low bits corresponding to the last interval c are OFF, ON, OFF; the number of mismatches is therefore 2, and voltage V Y1 is applied.
  • the voltages -V Y4 , V Y2 , and - V Y3 are applied to the column electrode Y 1 during intervals a, b, c because the ON/OFF states of row electrodes X 1 , X 2 , and X 3 are OFF, ON, OFF, the high bits of the display data at the intersections of the column electrode Y 1 and these row electrodes X 1 , X 2 , and X 3 are OFF, ON, ON, respectively, and the number of mismatches is 1 as described above, the middle bits are ON, OFF, OFF and the number of mismatches is 2, and the low bits are OFF, ON, OFF and the number of mismatches is 0.
  • the selection period t has been described to be subdivided into four subperiods, since these subperiods are consecutive they do in fact form one single selection period t for the row electrodes in each frame F.
  • the subperiods can also divide the selection period into plural separate parts in each frame F.
  • one field can be defined as the period required for all row electrodes to be selected in any one of the subperiods t 1 to t 4 , and with the four subperiods one frame F has four fields, or these subperiods can be subdivided and the sequence repeated for all of the row electrodes for each display data bit.
  • Fig. 24, Fig. 26, and Fig. 27 show an example of this case.
  • Fig. 24 is an applied voltage waveform diagram showing an embodiment in which the four consecutive subperiods t 1 to t 4 of the eleventh embodiment are separated into plural discrete subperiods for display drive, and Fig. 25 are waveforms of the row voltage applied to row electrodes X 1 to X 6 .
  • row electrodes X 1 , X 2 , and X 3 are selected and a column voltage corresponding to the number of mismatches, separately calculated for each of the three bit positions of the display data, is sequentially applied to column electrodes Y 1 to Y m in the same way as in the eleventh embodiment above, row electrodes X 4 , X 5 , and X 6 are next selected and a column voltage is again applied as above, and field f 1 for subperiod t 1 ends when all row electrodes have been selected.
  • the groups of row electrodes are again selected in sequence from row electrodes X 1 , X 2 , and X 3 , field f 2 corresponding to the next subperiod t 2 is executed, etc. When all four fields f 1 to f 4 corresponding to the four subperiods t 1 to t 4 are completed, one frame F is completed.
  • Fig. 26 shows the case in which execution is grouped for each display data bit, i.e., for each of the intervals a, b, c of the four subperiods tl to t4 in the above embodiment.
  • the first intervals a of the four subperiods t 1 to t 4 in Fig. 24 are treated as one field f 1 until all row electrodes have been selected, and one frame is completed when field f 2 corresponding to intervals b and field f 3 corresponding to intervals c are similarly completed. Note that the sign of the voltage applied to the row electrodes is reversed every field, and the voltage applied to the column electrodes is reversed accordingly.
  • Fig. 27 shows the case in which execution is further divided in that each group of four intervals a, four intervals b and four intervals c, respectively, is not treated as one continuous block as in Fig. 26, but separated in time within a field.
  • a first field f 1 all groups of simultaneously selected row electrodes are selected in sequence, each group during an interval a. This process is then repeated three times until all groups have been selected for a total of four times interval a while display is being controlled by one of the bits of the display data.
  • a second field f 2 the same procedure is then performed for interval b while display is controlled by another one of the display data bits, and during a third field f 3 the same is finally done for interval c based on the third bit of the display data.
  • the effect is the same as with the frame rate control modulation applied for each display data bit in the embodiment in Fig. 21 above.
  • the row electrode selection is executed plural times within one frame F as described above, the period in which the selected voltage is continuously not applied to each row electrode, i.e., to each pixel, can be shortened, the variation in display brightness can be reduced, and a loss of contrast can be prevented.
  • one selection subperiod is subdivided into the same number of intervals as the number n of bits of the display data used to represent the gradation, i.e., three, and a column voltage of one of six levels V Y1 to V Y6 is selectively applied to the column electrodes, but the number of column voltage levels can be reduced by increasing the above number of divisions.
  • the effective voltage when driving the liquid crystal elements of a liquid crystal display panel, etc. is generally determined by the voltage value and the voltage applied time (pulse width), and the panel can be equally driven whether a high voltage is applied for a short time or a low voltage is applied for a long time.
  • Fig. 28 is an applied voltage waveform diagram showing an embodiment in which the number of column voltage levels is decreased.
  • each selection subperiod is subdivided into (n+1) intervals, i.e., a, a, b, c, in the present embodiment, and the first two intervals a, a are assigned to the voltage apply time of the high display data bit.
  • V Y5 and V Y2 corresponding to the middle bit which are half the level of V Y6 and V Y4 , are respectively substituted for the V Y6 and V Y4 voltage levels corresponding to the high bit in the eleventh embodiment, and the apply time is twice that of the middle bit.
  • the voltage applied to the liquid crystal elements and the time are twice the middle bit and four times the low bit values, and the weighting ratio for each bit is 1:2:4, the same as the case shown in Fig. 1.
  • the two highest voltage levels V Y6 and V Y4 in the eleventh embodiment are eliminated by this embodiment, but the voltage levels V Y3 and V Y1 for the low bit can be used, respectively, in place of the middle bit voltage levels V Y5 and V Y2 in the eleventh embodiment, using an apply time twice that of the low bits in the same way as above. Furthermore, it is also possible to eliminate four or more voltage levels, and reducing the number of voltage levels as described above is a particularly effective means of simplifying the drive circuit configuration when there are many gradation levels.
  • Fig. 29 is a waveform diagram for the case in which one selection subperiod is subdivided into (n+1) intervals, i.e., 4intervals, and these selection subperiods are separated into plural parts in each frame, specifically into four fields f.
  • the period of one field is ⁇ t ⁇ N/h. Note, however, that the selection subperiods can also be subdivided into two or three intervals.
  • Fig. 30 shows a case similar to that of Fig. 26 in which all intervals assigned to the same bit of the display data of all subperiods are put together in one group and are treated as one block in the selection sequence.
  • the first ones of the two intervals a in each of the four subperiods t 1 to t 4 in Fig. 28 form a first block, and the period until all row electrodes have been selected for this block is one field f 1 .
  • the second ones of the two intervals a in each subperiod form a second block corresponding to a second field f 2 , the intervals b a third block corresponding to a third field f 3 and the intervals c a fourth block corresponding to a fourth field f 4 .
  • One frame is completed when after field f 1 fields f 2 , f 3 and field f 4 completed. Note that the sign of the voltage applied to the row electrodes is reversed each field, and the voltage applied to the column electrodes is also reversed accordingly.
  • Fig. 31 shows the case which corresponds to that of Fig. 27 and which differs from that of Fig. 31 in that execution is further divided in that in each field the intervals are not treated as one continuous block but are separated into discrete intervals.
  • it is selected four times in a field, each time for an interval of ⁇ t 1 .
  • the effective voltage when driving the liquid crystal elements as described above is generally determined by the voltage value applied and the apply time (pulse width), and the desired gray scale display can be achieved by appropriately combining the apply time and the value of the voltage applied to the column electrodes.
  • Fig. 32 is an applied voltage waveform diagram for an embodiment achieving a gray scale display with 16 gradations based on the display data shown in Fig. 33 by appropriately combining the apply time and the value of the voltage applied to the column electrode.
  • This embodiment also sequentially selects groups of three row electrodes, and applies a row voltage to each of the simultaneously selected row electrodes during the four selection subperiods t 1 to t 4 as in the first embodiment above.
  • Each of these four subperiods t 1 to t 4 is subdivided into six intervals a to f, and the first two intervals a, b correspond to the highest (most significant) bit in the four digit binary display data shown in Fig. 33, the next interval c corresponds to the second bit, the next two intervals d, e to the third bit, and the last interval f corresponds to the lowest (least significant) bit.
  • Column voltage ⁇ V Y4 or ⁇ V Y6 is selectively applied to the column electrodes according to the following conditions for the highest two bits, and ⁇ V Y1 or ⁇ V Y3 is selectively applied for the lowest two bits.
  • ON represent the state when the voltage waveform of the row electrode is positive and OFF when it is negative, and a display data value of 1 represents ON and 0 OFF; the ON/OFF state of the simultaneously selected row electrodes and the on/off state of the corresponding display data bits at the intersections of the selected row electrodes and the column electrode to which the voltage is to be applied are compared for each bit position, and a voltage specified according to the number of mismatches is applied to the column electrode.
  • the three row electrodes X 1 , X 2 , and X 3 are first simultaneously selected, and the selected row electrodes X 1 , X 2 , and X 3 are OFF, OFF, ON, respectively, and the bits of the highest bit position of the display data at the intersections of the column electrode Y 1 and these row electrodes X 1 , X 2 , and X 3 represent OFF, OFF, ON. Comparing both, the number of mismatches is 0, and the voltage -V Y6 is applied to column electrode Y 1 in the first intervals a, b of the first subperiod t 1 .
  • the bits of the second from highest bit position represent OFF, ON, OFF and the number of mismatches is 2 when compared with the OFF, OFF, ON states of the row electrodes X 1 , X 2 , and X 3 ; voltage V Y4 is therefore applied in period interval c.
  • the bits of the second from the lowest bit position represent ON, OFF, OFF, the number of mismatches is 2, and voltage V Y1 is applied in intervals d, e.
  • the bits of the lowest bit position represent OFF, ON, OFF, the number of mismatches is 2, and voltage V Y1 is therefore applied during interval f.
  • a weighted voltage is applied to the other column electrodes Y 1 to Y m in the same way.
  • a column voltage corresponding to the number of mismatches is simultaneously applied to all column electrodes Y 1 to Y m in the following subperiods t 2 to t 4 in the same way, selection of row electrodes X 1 , X 2 , and X 3 ends, the next row electrodes X 4 , X 5 , and X 6 are selected, the specified column voltages are applied to the column electrodes Y1 to Y m in the same way as described above, and when all row electrodes have been selected, one frame F ends.
  • the sign of the voltage applied to the row electrodes is then reversed because the first row electrodes X 1 , X 2 , and X 3 are again selected in sequence and the next frame begins, and the sign of the voltage applied to the column electrodes is also reversed for the so-called alternating current drive scheme.
  • a gray scale display can be achieved with fewer voltage levels, even when there are many gradations.
  • the selection subperiods can be separated into plural discrete parts within a single frame F as in the twelfth embodiment.
  • Fig. 34 shows this case.
  • the subperiods t 1 to t 4 in Fig. 32 are separated into four parts in a single frame F as in the twelfth embodiment, one field f lasts until all row electrodes have been selected in one subperiod, and the operation is repeated four times corresponding to four fields, one field for each subperiod, in one frame F.
  • the fifteenth embodiment can also be driven blockwise for each display data bit or can be further divided as shown in Fig. 30 and Fig. 31, respectively, in the fourteenth embodiment.
  • the voltage-time area of the voltage applied to the column electrodes i.e. either the voltage level or the time of applying it or both, is weighted corresponding to the display data bits for each column electrode to achieve a gray scale display, but it is also possible to weight or change the voltage level applied to the row electrode, for a gray scale display.
  • Fig. 35 is an applied voltage waveform diagram for an embodiment changing the voltage level applied to the row electrodes according to the display data bits to display eight gradations based on the display data shown in Fig. 22 similarly to the eleventh embodiment.
  • the row electrodes are selected sequentially, three at a time, and voltage V X4 or -V X4 is applied to each row electrode for the high display data bit, V X2 or -V X2 is applied for the middle bit, and V X1 or -V X1 is applied for the low bit where the ratio V X1 :V X2 :V X4 is 1:2:4.
  • the ON/OFF states of the row electrodes X 1 , X 2 , and X 3 and the display data ON/OFF states are compared bit by bit, and when the number of mismatches is 0, 1, 2, and 3, respectively, voltages -V Y3 , -V Y1 , V Y1 , and V Y3 are applied to the column electrodes Y 1 ,...; the V Y1 :V Y3 ratio is 1:3.
  • the number of voltage levels on the row electrode side is increased rather than increasing the voltage levels on the column electrode side as in the eleventh embodiment, the number of voltage levels applied to the column electrode can be significantly reduced, and the structure of the column electrode-side drive circuit can be simplified.
  • the selection subperiods can be separated into plural discrete parts within a single frame F as in the twelfth embodiment.
  • Fig. 36, Fig. 37, and Fig. 38 show this case.
  • Fig. 36 shows the case in which the subperiods t 1 to t 4 in Fig. 35 are separated into four parts in a single frame F as in the twelfth embodiment, one field f lasts until all row electrodes have been selected in one subperiod, and the operation is repeated four times in one frame F.
  • Fig. 37 shows the case wherein the display is driven blockwise for each display data bit, i.e., in each of the intervals of the four subperiods t 1 to t 4 in the previous embodiment.
  • the first interval a in the four subperiods t 1 to t 4 in Fig. 35 is treated as one field f 1 until all row electrodes have been selected, and one frame is completed when field f 2 corresponding to the other interval b and field f 3 corresponding to interval c are similarly completed. Note that the sign of the voltage applied to the row electrodes is reversed each field, and the voltage applied to the column electrodes is also reversed accordingly.
  • FIG. 39 This case is illustrated in Fig. 39.
  • Each of the subperiods t 1 to t 4 in Fig. 35 is subdivided into four intervals in one frame F as in Fig. 28 with the first two intervals being the apply time for the high bit, and the other intervals being the apply times for the middle and low bits, respectively.
  • the selection subperiods can also be separated into plural discrete parts within a single frame F.
  • Fig. 40, Fig. 41, and Fig. 42 show this case.
  • Fig. 40 shows the case where the subperiods t 1 to t 4 in Fig. 39 are separated into four parts in a single frame F. As in Fig. 25, one field f lasts until all row electrodes have been selected in one subperiod, and the operation is repeated four times in one frame F.
  • Fig. 41 shows the case in which execution is grouped for each interval of the four subperiods t 1 to t 4 in the previous embodiment; the first interval a of intervals a, a in the four subperiods t 1 to t 4 in Fig. 39 is treated as one field f 1 until all row electrodes have been selected, and one frame is completed when field f 2 corresponding to the other interval a, field f 3 corresponding to interval b, and field f 3 corresponding to interval c are similarly completed. Note that the sign of the voltage applied to the row electrodes is reversed each field, and the voltage applied to the column electrodes is also reversed accordingly.
  • Fig. 43 shows an example of this.
  • voltage V X4 or -V X4 is used as the applied voltage level to each row electrode for the two highest display data bits, V X1 or -V X1 is applied for the two lowest bits, and the ratio V X1 :V X4 is 1:4.
  • the ON/OFF states of the row electrodes X 1 , X 2 , and X 3 and the display data ON/OFF states are compared bit by bit, and when the number of mismatches is 0, 1, 2, and 3, respectively, voltages -V Y3 , -V Y1 , V Y1 , and V Y3 are applied to the column electrodes Y 1 ,...; the V Y1 :V Y3 ratio is 1:3.
  • the selection subperiods can also be separated into plural discrete parts within a single frame F.
  • Fig. 44 shows this case.
  • the subperiods t 1 to t 4 in Fig. 43 are separated into four parts in a single frame F as in Fig. 34, one field f lasts until all row electrodes have been selected in one subperiod, and the operation is repeated four times in one frame F.
  • embodiment 21 can also be driven blockwise for each display data bit or can be further divided as in embodiment 20 shown in Fig. 41 and Fig. 42, respectively.
  • the waveform of the voltages applied to the row electrodes shall not be limited to the embodiments, and the waveforms can be changed to the kind of waveforms as shown in Fig. 48 (a) and (b) or Fig. 3 (a) and (b), or the pulse widths thereof can be appropriately selected or the order changed insofar as the waveforms applied to the simultaneously selected row electrodes do not become intermixed and the row electrodes can be separately driven.

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  • Crystallography & Structural Chemistry (AREA)
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  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
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  • Liquid Crystal Display Device Control (AREA)
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Claims (14)

  1. Verfahren zum Multiplextreiben einer elektrooptischen Matrixflüssigkristallvorrichtung, die eine Flüssigkristallschicht umfaßt, die zwischen einem Zeilenelektroden (X1, X2, ...) tragenden ersten Substrat und einem Spaltenelektroden (Y1, Y2, ...) tragenden zweiten Substrat vorgesehen ist, wobei die Zeilen- und Spaltenelektroden eine Matrix aus Pixeln definieren, und wobei das Verfahren umfaßt:
    Unterteilen der Zeilenelektroden in Gruppen (X1, X2, X3; X4, X5, X6; X1, X2, X3, Xn+1; X4, X5, X6, Xn+2),
    gleichzeitiges Auswählen, während einer Auswahlperiode, der Zeilenelektroden einer Gruppe durch Anlegen einer jeweiligen Zeilenspannungswellenform an jede von ihnen, während eine Nichtauswahlspannung an die Zeilenelektroden aller anderen Gruppen angelegt wird, und nacheinander Auswählen der einzelnen Gruppen, wobei sich die Zeilenspannungswellenformen aus einer Mehrzahl von Zeilenauswahlimpulsen zusammensetzen, die eine entsprechende Mehrzahl an Zeilenauswahlmustern definieren, und
    Anlegen einer jeweiligen Spaltenspannung an die einzelnen Spaltenelektroden, wobei die Spaltenspannung als Antwort auf die einzelnen Zeilenauswahlmuster und Anzeigedaten bestimmt wird,
       wobei das Verfahren gekennzeichnet ist durch
    Unterteilen der Auswahlperiode in mehrere Teilperioden (t1, t2, t3, t4; Δto; Δt; Δt1) und
    Gewichten für jede Teilperiode, nach Maßgabe von Gradationsinformation von Grauskalenanzeigedaten, entweder
    der Pulsweite und/oder des Pegels der an eine jeweilige Spaltenelektrode angelegten Spannung,
    des Pegels der jeweiligen Spannung, die an die einzelnen ausgewählten Zeilenelektroden angelegt wird, oder
    der Pulsweite und des Pegels der jeweiligen Spannung, die an die einzelnen ausgewählten Zeilenelektroden angelegt wird.
  2. Verfahren nach Anspruch 1, bei dem jede Teilperiode (t1, t2, t3, t4) in eine Anzahl von Intervallen (a, b; a, b, c) entsprechend der Anzahl an Bits von Mehrbit-Grauskalenanzeigedaten unterteilt ist, wobei jedes Intervall einem anderen der Bits zugewiesen ist und der Pegel der während der einzelnen Intervalle angelegten Zeilen- oder Spaltenspannung nach Maßgabe des jeweiligen Bits gewichtet wird.
  3. Verfahren nach Anspruch 1, bei dem jede Teilperiode (t1, t2, t3, t4) in mehr Intervalle (a, a, b, c; a - f) als die Anzahl an Bits von Mehrbit-Grauskalenanzeigedaten unterteilt ist, mehrere der Intervalle demselben Bit zugewiesen sind und der Pegel der während der einzelnen Intervalle angelegten Zeilen- oder Spaltenspannung nach Maßgabe des jeweiligen Bits gewichtet wird.
  4. Verfahren nach einem der vorhergehenden Ansprüche, bei dem die Teilperioden jeder Auswahlperiode eine kontinuierliche Periode bilden. (Fig. 21, 28, 32, 35, 39, 43)
  5. Verfahren nach einem der Ansprüche 1 bis 3, bei dem die Teilperioden (Δt in Fig. 24, 29, 34, 36, 40, 44) zeitlich voneinander getrennt sind, so daß, wenn die Gruppen von Zeilenelektroden nacheinander ausgewählt werden, jede für die Dauer einer Teilperiode ausgewählt wird, wobei dies für jede der anderen Teilperioden wiederholt wird.
  6. Verfahren nach einem der Ansprüche 1 bis 3, bei dem jede Teilperiode (Δt in Fig. 26, 30, 37, 41) einem Bit von Mehrbit-Grauskalenanzeigedaten zugewiesen wird und der Impulspegel oder die Pulsweite sowie der -pegel der während der einzelnen Teilperioden angelegten Spannung nach Maßgabe des jeweiligen Bits gewichtet wird.
  7. Verfahren nach Anspruch 2 oder 3, bei dem die Intervalle (Δt1 in Fig. 27, 31, 38, 42) zeitlich getrennt sind, so daß, wenn die Gruppen von Zeilenelektroden nacheinander ausgewählt werden, jede für die Dauer eines Intervalls ausgewählt wird, wobei dies für jedes der anderen Intervalle und jede Teilperiode wiederholt wird.
  8. Verfahren nach einem der Ansprüche 1 bis 7, bei dem, wenn ein Rahmen als die Zeitspanne definiert ist, die gleich der Auswahlperiode multipliziert mit der Anzahl an Zeilenelektrodengruppen ist, die Spaltenspannungen während einer Periode mehrerer Rahmen so moduliert werden, daß zusätzliche Gradationen der Grauskalenanzeige erhalten werden.
  9. Verfahren nach einem der vorhergehenden Ansprüche, bei dem jede Gruppe gleichzeitig ausgewählter Zeilenelektroden zumindest eine virtuelle Zeilenelektrode umfaßt und der Anzeigezustand von der virtuellen Zeilenelektrode entsprechenden imaginären Pixeln nach Maßgabe des Zeilenauswahlmusters und der Anzeigedaten entsprechend den tatsächlichen Zeilenelektroden so eingestellt wird, daß die Anzahl erforderlicher Spaltenspannungspegel reduziert wird.
  10. Verfahren nach einem der vorhergehenden Ansprüche, bei dem, wenn ein Rahmen definiert ist als die Zeitspanne, die gleich der Auswahlperiode multipliziert mit der Anzahl an Zeilenelektrodengruppen ist, die Reihenfolge der Zeilenauswahlmuster unter den Gruppen innerhalb jedes Rahmens geändert oder unter den Rahmen geändert wird.
  11. Verfahren nach einem der vorhergehenden Ansprüche in Kombination mit Anspruch 2 oder 3, bei dem, wenn ein Rahmen als die Zeitspanne definiert ist, die gleich der Auswahlperiode multipliziert mit der Anzahl an Zeilenelektrodengruppen ist, die Reihenfolge, in der die Intervalle den Bits zugewiesen werden, unter den Spaltenelektroden und/oder unter den Gruppen innerhalb jedes Rahmens oder unter den Rahmen geändert wird.
  12. Verfahren gemäß einem der vorhergehenden Ansprüche, bei dem, wenn ein Rahmen als die Zeitspanne definiert ist, die gleich der Auswahlperiode multipliziert mit der Anzahl an Zeilenelektrodengruppen ist, die Polarität der an die Zeilenelektroden und an die Spaltenelektroden angelegten Spannungen mit jedem Rahmen oder innerhalb jedes Rahmens umgekehrt wird.
  13. Treiberschaltung einer elektrooptischen Matrixflüssigkristallvorrichtung, welche eine Flüssigkristallschicht umfaßt, die zwischen einem Zeilenelektroden (X1, X2, ...) tragenden ersten Substrat und einem Spaltenelektroden (Y1, Y2, ...) tragenden zweiten Substrat vorgesehen ist, wobei die Zeilen- und Spaltenelektroden eine Matrix aus Pixeln definieren, zum Ausführen des Verfahrens von Anspruch 1, wobei die Treiberschaltung umfaßt:
    einen Zeilenelektrodentreiber (1) zum gleichzeitigen Auswählen, während einer Auswahlperiode, der Zeilenelektroden einer Gruppe der Zeilenelektroden durch Anlegen einer jeweiligen Zeilenspannungswellenform an jede von ihnen, während eine Nichtauswahlspannung an die Zeilenelektroden aller anderen Gruppen angelegt wird, und Auswählen der einzelnen Gruppen nacheinander, wobei sich die Zeilenspannungswellenformen aus einer Mehrzahl von Zeilenauswahlimpulsen zusammensetzen, die eine entsprechende Mehrzahl an Zeilenauswahlmustern definieren,
    einen Spaltenelektrodentreiber (2) zum Anlegen einer jeweiligen Spaltenspannung an die einzelnen Spaltenelektroden, wobei die Spaltenspannung als Antwort auf die einzelnen Zeilenauswahlmuster und Anzeigedaten bestimmt ist,
    eine Abtastdatenerzeugungsschaltung (5) zum Erzeugen der Zeilenauswahlmuster,
    eine Rechenanordnung (4), welche die Zeilenauswahlmuster und die Anzeigedaten für jede Gruppe gleichzeitig ausgewählter Zeilenelektroden empfängt, zum Berechnen, als Antwort auf die einzelnen Zeilenauswahlmuster und die einzelnen Anzeigedaten, von Spaltenspannungsdaten,
    eine Anordnung zum Übertragen der Spaltenspannungsdaten an den Spaltenelektrodentreiber (2) und zum gleichzeitigen Übertragen des Zeilenauswahlmusters an den Zeilenelektrodentreiber (1),
       gekennzeichnet durch eine Anordnung zum Unterteilen der Auswahlperiode in mehrere Teilperioden (t1, t2, t3, t4; Δto; Δt; Δt1) und zum Gewichten für jede Teilperiode, nach Maßgabe von Gradationsinformation von Grauskalenanzeigedaten, entweder
    der Pulsweite und/oder des Pegels der an eine jeweilige Spaltenelektrode angelegten Spannung,
    des Pegels der jeweiligen Spannung, die an die einzelnen ausgewählten Zeilenelektroden angelegt wird, oder
    der Pulsweite und des Pegels der jeweiligen Spannung, die an die einzelnen ausgewählten Zeilenelektroden angelegt wird.
  14. Matrixflüssigkristallanzeigevorrichtung, die eine Treiberschaltung gemäß Anspruch 13 enthält.
EP93911979A 1992-05-08 1993-05-10 Steuerungsverfahren und -schaltung für flüssigkristallelemente und bildanzeigevorrichtung Expired - Lifetime EP0598913B1 (de)

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JP19907792 1992-07-02
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PCT/JP1993/000604 WO1993023844A1 (en) 1992-05-08 1993-05-10 Method and circuit for driving liquid crystal device, etc., and display device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102568370A (zh) * 2010-12-22 2012-07-11 财团法人工业技术研究院 多重稳态显示面板的驱动装置与驱动方法

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5739803A (en) * 1994-01-24 1998-04-14 Arithmos, Inc. Electronic system for driving liquid crystal displays
JP3169763B2 (ja) * 1994-05-18 2001-05-28 セイコーインスツルメンツ株式会社 液晶表示パネルの階調駆動装置
KR100344861B1 (ko) * 1994-08-23 2002-11-23 아사히 가라스 가부시키가이샤 액정 디스플레이 장치의 구동 방법
JP2796619B2 (ja) * 1994-12-27 1998-09-10 セイコーインスツルメンツ株式会社 液晶表示パネルの階調駆動装置
KR100337865B1 (ko) * 1995-09-05 2002-12-16 삼성에스디아이 주식회사 액정 표시 소자의 구동방법
FR2784489B1 (fr) * 1998-10-13 2000-11-24 Thomson Multimedia Sa Procede d'affichage de donnees sur un afficheur matriciel
TW580672B (en) 1999-03-15 2004-03-21 Seiko Epson Corp Liquid-crystal display device and method of driving the same
KR100515468B1 (ko) 2001-06-13 2005-09-14 가와사키 마이크로 엘렉트로닉스 가부시키가이샤 단순 매트릭스액정의 구동방법 및 장치, 단순 매트릭스액정의 멀티 라인 어드레싱 구동방법 및 장치, 및 액정표시디스플레이 패널
JP3642328B2 (ja) * 2001-12-05 2005-04-27 セイコーエプソン株式会社 電気光学装置、その駆動回路、駆動方法及び電子機器
EP1365384A1 (de) * 2002-05-23 2003-11-26 STMicroelectronics S.r.l. Ansteuerverfahren für Flachbildschirme
JP2004287118A (ja) 2003-03-24 2004-10-14 Hitachi Ltd 表示装置
EP1471496A1 (de) * 2003-04-23 2004-10-27 STMicroelectronics S.r.l. Verfahren zum Steuern eines Flüssigkristallanzeigegeräts
JP2006527407A (ja) * 2003-06-12 2006-11-30 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 省エネルギー・パッシブ・マトリクス・ディスプレイ装置および駆動方法
JP4945119B2 (ja) * 2005-11-16 2012-06-06 株式会社ブリヂストン 情報表示用パネルの駆動方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5715393B2 (de) * 1973-04-20 1982-03-30
JPS61262724A (ja) * 1985-05-08 1986-11-20 Stanley Electric Co Ltd 液晶表示器
JPS62102230A (ja) * 1985-10-30 1987-05-12 Seiko Epson Corp 液晶素子の駆動方法
JP2675060B2 (ja) * 1988-04-20 1997-11-12 株式会社日立製作所 アクティブマトリクス方式の表示装置及びその走査回路と走査回路の駆動回路
FR2633764B1 (fr) * 1988-06-29 1991-02-15 Commissariat Energie Atomique Procede et dispositif de commande d'un ecran matriciel affichant des niveaux de gris
JP2823614B2 (ja) * 1989-12-15 1998-11-11 株式会社日立製作所 階調表示方式および液晶表示装置
US5103144A (en) * 1990-10-01 1992-04-07 Raytheon Company Brightness control for flat panel display
US5485173A (en) * 1991-04-01 1996-01-16 In Focus Systems, Inc. LCD addressing system and method
US5459495A (en) * 1992-05-14 1995-10-17 In Focus Systems, Inc. Gray level addressing for LCDs
DE69214206T2 (de) * 1991-07-08 1997-03-13 Asahi Glass Co. Ltd., Tokio/Tokyo Steuerverfahren für ein Flüssigkristallanzeigeelement
US5621425A (en) * 1992-12-24 1997-04-15 Seiko Instruments Inc. Liquid crystal display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102568370A (zh) * 2010-12-22 2012-07-11 财团法人工业技术研究院 多重稳态显示面板的驱动装置与驱动方法

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EP0598913A1 (de) 1994-06-01
DE69331812T2 (de) 2002-11-14
EP0598913A4 (de) 1994-10-26
DE69326740T2 (de) 2000-04-06
JP2000347163A (ja) 2000-12-15
TW280874B (de) 1996-07-11
EP0836173B1 (de) 2002-04-10
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WO1993023844A1 (en) 1993-11-25
EP0836173A2 (de) 1998-04-15

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