EP0594670B1 - Generateur d'oscillations et son utilisation - Google Patents
Generateur d'oscillations et son utilisation Download PDFInfo
- Publication number
- EP0594670B1 EP0594670B1 EP92914310A EP92914310A EP0594670B1 EP 0594670 B1 EP0594670 B1 EP 0594670B1 EP 92914310 A EP92914310 A EP 92914310A EP 92914310 A EP92914310 A EP 92914310A EP 0594670 B1 EP0594670 B1 EP 0594670B1
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- European Patent Office
- Prior art keywords
- signal
- delay
- output
- stage
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000010355 oscillation Effects 0.000 title claims description 21
- 230000000737 periodic effect Effects 0.000 claims description 11
- 238000006073 displacement reaction Methods 0.000 claims 2
- 238000012360 testing method Methods 0.000 description 9
- 230000007704 transition Effects 0.000 description 5
- 230000015654 memory Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000012937 correction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000001934 delay Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 241001136792 Alle Species 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/03—Astable circuits
- H03K3/0315—Ring oscillators
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S331/00—Oscillators
- Y10S331/03—Logic gate active element oscillator
Definitions
- the present invention relates to a device for generating vibrations according to the preamble of claim 1 and a preferred use of the device according to the preamble of the first use claim.
- Devices for generating vibrations also called oscillators, are known to emit periodic vibrations which have a sinusoidal, rectangular, or other periodic course.
- These output signals are determined by their amplitude and by their frequency f, the reciprocal of which determines the period T, also called the oscillation period.
- Digital switching stages are particularly suitable for generating square-wave output signals.
- a known embodiment of an oscillator with digital elements is the so-called ring oscillator, which is known, for example, from the book "Introduction to VLSI systems", C. Mead, L. Conway, Addison-Wesley Publishing Company, 1980.
- a ring oscillator is constructed in such a way that an odd number of inverters in a chain are connected in series, the output of the last inverter being connected to the input of the first inverter.
- Each of these inverters causes a delay time and the oscillation period T of the output signal is determined by the number of inverters and the respective delay time.
- the oscillation period T itself is twice the total delay time.
- a ring oscillator which has a chain of delay elements and emits a periodic square-wave signal.
- the ring oscillator contains a logic stage which is supplied with a first signal which is derived from the output signal of the last delay element and a second signal which is derived from a delay element arranged within the delay chain and which outputs an input signal to the input of the first delay element.
- the period of the oscillator signal corresponds to the total delay time of the delay elements used. However, additional means are required here in order to multiply the period of the oscillator signal.
- the oscillation period T essentially corresponds to the total delay time of the inverter chain used.
- Inverters or other assemblies known to those skilled in the art can be used as suitable delay elements.
- the frequency and / or the duty cycle of the output signal can thus also be varied even after the oscillator has been started up.
- target value stage which can be designed, for example, as an input device, as a memory, or the like
- target / actual comparison stage which Controlled switching means
- output signals can be specified and set in a wide range.
- the delay elements are such that the individual delay times of at least some of them can be changed.
- the period and / or the pulse duty factor can be finely adjusted by appropriate control.
- a preferred use of the device according to the invention for generating vibrations is that it is used as part of a phase detector.
- oscillator oscillates with an oscillator oscillation with a predetermined frequency value
- periodic output signals can be picked up at the outputs of the individual delay elements, which are phase-shifted with respect to one another.
- phase-shifted output signals are fed to a comparison stage, which is also fed a test signal to be analyzed.
- the comparison stage recognizes when the test signal has a predetermined value and which of the digital phase-shifted output signals have a high (logic "1” or “high”) and which have a low (logic "0” or “low”) value. This allows conclusions to be drawn about the phase relationship of the periodic output signal with that of the test signal.
- PLL phase-controlled
- This compares the output phase of any of the stage output signals with the desired phase of a desired signal and, in the event of an undesired difference between these two phases, emits an actuating signal. This allows individual delay times and / or positions of at least some of the delay elements to be changed, so that the step output signal and the desired signal are in phase with one another.
- Such use of the oscillator according to the invention can serve, among other things, to keep the individual delay times at predetermined values. This allows the phase shift of a test signal already mentioned to be determined very precisely.
- Figure 1 shows a first embodiment of the oscillator device according to the invention.
- a chain of delay elements 10.1, ..., 10.l is connected in series.
- a logic stage 11, which in this exemplary embodiment has an AND gate 12 and a NOR gate 13, has its first input 11a, which is identical to the first input 12a of the AND gate 12, to the output of the last delay element 10 .l, which is designed as an inverter, connected.
- the second input 11b of the logic stage 11, which corresponds to the second input 12b of the AND gate 12, is connected to the output of a delay element 10.m. Its output is still connected to the input of the delay element 10.m + 1.
- the output 12c of the AND gate 12 leads to a first input 13a of the NOR gate 13.
- Whose second input 13b, which corresponds to the third input 11c of the logic stage 11, is connected to the output of a delay element 10.n, which additionally leads to the input of the delay element 10.n + 1.
- the output signal of the oscillator device is also present here.
- FIG. 2 consisting of FIGS. 2a, b, c.
- the last delay element is thus designated as 10.32. 22 is set for m, so that the output of the 22nd delay element 10.22 leads to the second input 11b of the logic stage 11. Furthermore, the output of the 15th (n) delay element 10.15 is connected to the third input 11c of the logic stage 11.
- the 32nd delay element 10.32 which is designed as an inverter, emits a signal with logic "1" (high) at its output. Since the second input 12b of the AND gate 12 is initially low, it outputs a low signal at its output 12c to the first input 13a of the NOR gate 13. Since a low signal is also present at the second input 13b of the NOR gate 13, a high signal is made available at the output 13c of the NOR gate 13.
- each of the delay elements has a delay time of one time unit, as defined by the top line of FIG. 2a.
- the AND gate 12 and the NOR gate 13 also each have a delay of one time unit.
- switch 20 is closed, with the result that the high signal of output 13c from NOR gate 13 is applied to the input of first delay element 10.1.
- This has the effect that at time t 16 at output 13c of NOR gate 13 there is a low signal (edge B) which is fed to the input of first delay element 10.1.
- This creates a second front i.e. a transition from "high” to "low” causes, which runs from the input of the first delay element.
- the first front has reached the output of delay element 10.22, as a result of which a high signal is applied to second input 12b of AND gate 12 (edge C).
- a high signal is also present at the first input 12a, a high signal is present at the output 12c of the gate 12 (edge D). This is present at the first input 13a of the NOR gate 13 at the same time, but this does not affect its behavior, since a high signal is already present at the second input 13b.
- the second front has the exit of the Delay element 10.15 and thus reaches the second input of NOR gate 13 (edge E). However, since the high output signal of the AND gate 12 is still present at its first input, nothing further is initially effected.
- the first front reaches the output of the last delay element 10.32. Since this last delay element 10.32 is designed as an inverter, the first front causes a changeover from "high" to "low” (edge F).
- This output signal is present at the input of the first delay element 10.1 and causes a third front which progresses through the chain of delay elements 10.1, ..., 10.32 and, analogously to the switching of the corresponding gates 12 and 13 already mentioned, causes.
- This causes edges A ', B', C ', etc. which have an analogous meaning to the edges A, B, C, etc. already described.
- Such a mode of operation is realized in this embodiment in that the output signal of the m-th delay element 10.m is processed by the logic stage 11 as indicated.
- m is to be selected as indicated.
- the presence of the switch 20 serves first of all to better describe the functioning of the exemplary embodiment. However, it is also conceivable that it serves as an on / off switch.
- the logic stage causes a delay other than the one mentioned, the values for the oscillation period T and the duty cycle TV change accordingly.
- FIG. 3 Another embodiment of the invention is shown in Figure 3.
- an electronic control unit 14 which receives signals from an input unit 15. These can be used to enter setpoints for the frequency fset, corresponding to the reciprocal of the oscillation period, and the duty cycle TVset.
- Another input of the control device 14 is connected to the output 11d of the logic stage 11.
- the electronic control unit 14 outputs a signal STV to the control input of a duty cycle switch 16, to the switching inputs of which the outputs of the delay elements 10n + 1, 10.n, ... are connected.
- the switching output of the duty cycle switch 16 is connected to the third input 11c of the logic stage 11.
- the electronic control unit 14 also emits a control signal Sm to the control input of a second changeover switch 17, at the changeover inputs of which the outputs of the delay elements 10.m + 1, 10.m, ... Its switching output is connected to the second input 11b of the logic stage 11.
- the electronic control unit 14 also outputs a signal Sf to the control input of the frequency switch 18, at whose switch inputs the outputs of the delay elements 10.l-1, 10.l-2, ... are applied.
- the electronic control unit 14 is also connected to a display device 19, via which errors when the frequency fset and / or the duty cycle TVset are entered can be displayed.
- the display device 19 can be designed both as a simple error "lamp” and as a display, via which a detailed error description can be made in alphanumeric characters.
- operating states of the oscillator can be displayed by means of the display device 19.
- step 100 After starting in step 100, setpoints for the frequency fset and for the duty cycle TVset are entered via the input unit 15 (step 101). In step 102, a value lsoll is determined from the value fsoll, and a value msoll is determined from the value TVsoll.
- step 103 it is determined whether the value lsoll is greater than a maximum value lmax, which corresponds to the total number of delay elements, possibly taking further delays into account, for example by gates 12, 13. If “yes”, the method according to the invention leads to step 104, in which an error is displayed via the display unit 19. If it is determined in step 103 that If it is less than or equal to I max, the method leads to step 105 in which it is determined whether nset is less than or equal to Iset / 2. If “no”, this in turn leads to an error display (step 106) and if the result from step 105 is "yes", the method continues at step 107. After steps 104 and 106, step 101 is again performed, in which frequency fset and duty cycle TVset can be re-entered.
- step 109 the output signal, which is present at the output 13c of the NOR gate 13, is compared in terms of its frequency and its duty cycle with the target values, and if a correction is necessary, this is carried out in step 110. After step 110 or if no correction in step 109 is required, the query from step 109 takes place again.
- the oscillation period T can thus be varied if the total number l is changed by delay elements by driving the frequency switch 18.
- the duty cycle TV can be predetermined by driving the duty cycle switch 16.
- the aforementioned controls of the changeover switches 16, 18 each change the positions of the delay elements from which the first, second and third signals are tapped.
- a signal present at input 22a can be delayed and output non-inverted at output 22b.
- the respective delay times of the inverters 20, 21 determine the individual delay time of the delay element 10 shown in FIG. 5.
- a first delay transistor 23, the gate connection of which leads to a first control input 24, and a second delay transistor 25, the gate connection of which leads to a second control input 26, are provided in FIG. 5.
- the delay transistors 23, 25 are connected in series with the first inverter 20, a ground connection and a positive supply voltage U +.
- the source-drain resistance of the controlled delay transistor 23 or 25 is changed by control signals at one of the control inputs 24, 26.
- the delay time of the first inverter 20 for signals present at the input 22 increases with an edge too logically "high".
- the individual delay time of the first inverter 20 and thus of the entire delay element 10 can thus be varied by control signals at the control inputs 24, 26.
- FIG. 6 A preferred application of oscillator devices with delay elements is shown in FIG. 6.
- a switching device 27 has a plurality of switching elements 27.1, ..., 27.l, which can be implemented as registers, memories, latches or the like.
- the inputs of the delay elements 10.1, ..., 10.l are each connected to one of the first switching connections of the switching elements 27.1, ..., 27.l.
- Second switching connections of the switching elements 27.2, ..., 27.l-1 are each provided with an input of inverters 28.2, ..., 28.l-1 as well as with a first input of NOR gates 29.1, ..., 29.l-2 connected.
- the second switching connection of the first switching element 27.1 leads only to the input of a first inverter 28.1 and the second switching connection of a last switching element 27.l is only connected to the first input of a NOR gate 29.l-1.
- the outputs of the inverters 28.1, ... 26.l-1 are each connected to second inputs of the NOR gates 29.1, ..., 29.l-1.
- a control input of the switching device 27 leads to the output of a threshold stage 30, to which a test signal to be analyzed is fed at its input.
- the arrangement according to FIG. 6 serves to determine the phase position of the test signal in relation to the vibration with which the oscillator device vibrates.
- test signal When a predetermined threshold value is exceeded or undershot, the test signal causes the threshold value stage 30 to emit a signal with a logic "high” or “low” at its output at the relevant point in time.
- the switching device 27 may be controlled in such a way that all switching elements 27.1,..., 27.l are closed. Depending on the input signal of the delay elements 10.1, ..., 10.l, a transition from "high” to “low” is present, one of the NOR gates 29 emits a "high” signal.
- phase position of the test signal with respect to the oscillator oscillation can be concluded.
- the input stages of the inverters 28 are preferably designed in such a way that lastly applied voltages are stored, for example on the input (gate) capacitances.
- a corresponding storage of output signals can, however, also be carried out by the evaluation stage (not shown) or its connected memory.
- the switching device 27 is designed as a register, memory, latch or the like and that signals are stored here.
- Versions of this application example can contain combinations of features, as previously mentioned with reference to the exemplary embodiments described.
- the setting of values of the oscillation period T and / or the duty cycle TV by changing positions and / or individual delay times of delay elements is advantageous.
- a television horizontal synchronization pulse can serve as the test signal. Its phase position can be determined by the phase detector shown in FIG. 6 and evaluated by appropriate means. For this purpose, it is advantageous if the oscillator device oscillates at exactly the same frequency as the clock frequency of the television set.
- the logic stage 11 can be formed from further combinations of digital modules that are known to the person skilled in the art.
- FIG. 7 Exemplary designs are indicated in FIG. 7, consisting of FIGS. 7a, b, c.
- An oscillator which contains a chain of delay elements and emits an output signal, the period T of which essentially corresponds to the total delay time of the chain.
- the oscillator according to the invention has a logic stage, to which signals which can be tapped along the chain or which are generated by additional means are fed. The logic stage then influences the input signal of the first delay element in the chain.
- the oscillator according to the invention can be used as part of a phase detector.
Landscapes
- Pulse Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Electrophonic Musical Instruments (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Claims (4)
- Un dispositif générateur d'oscillations comportant une chaîne de I éléments de retard (10.1, ..., 10.l) et émettant au moins un signal périodique de sortie d'étage commuté entre une première valeur (logique « 1 ») et une seconde valeur (logique « 0 ») avec une durée de période T et avec un étage logique (11) auquel sont fournis au moins- un premier signal dérivé du signal de sortie du dernier élément de retard (10.l) et- un second signal dérivé du signal de sortie d'un élément de retard d'analyse (10.n) situé au sein de la chaîne,et qui émet un signal d'entrée à l'entrée du premier élément de retard (10.1) et pour lequel la durée de période T présente une valeur sensiblement égale au temps de retard total des éléments de retard utilisés (10.1, ..., 10.l) et le second signal entraîne la commutation du signal d'entrée du premier élément de retard par lequel le taux d'impulsions (TV) du signal de sortie d'étage sera fourni en fonction de la position n de l'élément de retard d'analyse (10.n) et le signal de sortie d'étage sera dérivé des signaux de sortie d'au moins un des éléments de retard (10.1, ..., 10.l) ou de l'étage logique (11), caractérisé en ce que le taux d'impulsions TV est réglable et déterminé par la relation
- Une utilisation du dispositif générateur d'oscillations conforme à la revendication 1 en tant que composant d'un détecteur de phase, caractérisé en ce que le dispositif générateur d'oscillations émet des signaux de sortie d'étage déphasés établis à partir des signaux de sortie d'au moins un des éléments de retard (10.1, ..., 10.l) situés dans la chaîne, pour lesquels il est possible de déterminer le déphasage des signaux de sortie d'étage en fonction de leur position dans la chaîne.
- Une utilisation selon la revendication 2, caractérisée en ce que les temps de retard d'au moins un des éléments de retard (10.1, ..., 10.l) situés dans la chaîne peuvent être prédéfinis et que le déphasage des signaux de sortie d'étage peut être défini par le réglage des temps de retard et/ou par modification de la position d'au moins un des éléments de retard (10.1, ..., 10.l).
- Une utilisation selon la revendication 3, caractérisée en ce que le dispositif générateur d'oscillations est utilisé en tant que composant d'un circuit à boucle à verrouillage de phase qui compare la phase de sortie d'un signal de sortie d'étage avec la phase de consigne d'un signal de consigne et en cas de différence entre ces deux phases émet un signal de commande par lequel les temps de retard et/ou la position d'au moins un des éléments de retard (10.1, ..., 10.l) seront modifiés.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE4123388 | 1991-07-15 | ||
DE4123388A DE4123388A1 (de) | 1991-07-15 | 1991-07-15 | Vorrichtung zur erzeugung von schwingungen und deren anwendung |
PCT/EP1992/001519 WO1993002504A1 (fr) | 1991-07-15 | 1992-07-06 | Generateur d'oscillations et son utilisation |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0594670A1 EP0594670A1 (fr) | 1994-05-04 |
EP0594670B1 true EP0594670B1 (fr) | 1997-10-08 |
Family
ID=6436175
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP92914310A Expired - Lifetime EP0594670B1 (fr) | 1991-07-15 | 1992-07-06 | Generateur d'oscillations et son utilisation |
Country Status (8)
Country | Link |
---|---|
US (1) | US5448205A (fr) |
EP (1) | EP0594670B1 (fr) |
JP (1) | JP3347729B2 (fr) |
KR (1) | KR100239988B1 (fr) |
DE (2) | DE4123388A1 (fr) |
FI (1) | FI110728B (fr) |
SG (1) | SG47792A1 (fr) |
WO (1) | WO1993002504A1 (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107193533A (zh) * | 2017-07-31 | 2017-09-22 | 南京航空航天大学 | 一种新型低成本高速真随机数发生器 |
Families Citing this family (20)
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DE4211701A1 (de) * | 1992-04-08 | 1993-10-14 | Thomson Brandt Gmbh | Verfahren und Vorrichtung zur Phasenmessung |
US5452759A (en) * | 1993-09-10 | 1995-09-26 | Weatherford U.S., Inc. | Whipstock system |
US5887655A (en) * | 1993-09-10 | 1999-03-30 | Weatherford/Lamb, Inc | Wellbore milling and drilling |
JP2663397B2 (ja) * | 1994-04-07 | 1997-10-15 | 高エネルギー加速器研究機構長 | 電圧制御発振回路及びこれを用いた信号検出器 |
JP2830735B2 (ja) * | 1994-04-19 | 1998-12-02 | 日本電気株式会社 | 位相同期型タイミング発生回路 |
JP3299631B2 (ja) * | 1994-06-07 | 2002-07-08 | 三菱電機株式会社 | 電圧制御型発振器およびそれを用いた位相同期ループ回路 |
US5543730A (en) | 1995-05-17 | 1996-08-06 | Altera Corporation | Techniques for programming programmable logic array devices |
JPH08330912A (ja) * | 1995-06-05 | 1996-12-13 | Mitsubishi Electric Corp | リングオシレータ |
EP1359592A3 (fr) * | 1995-10-31 | 2006-12-20 | STMicroelectronics S.r.l. | Générateur d'horloge pour cellules de mémoire morte programmable électriquement |
US5740410A (en) * | 1995-12-15 | 1998-04-14 | Cyrix Corporation | Static clock generator |
JP3564855B2 (ja) * | 1996-02-29 | 2004-09-15 | ソニー株式会社 | リングオシレータ及びpll回路 |
US6384630B2 (en) | 1996-06-05 | 2002-05-07 | Altera Corporation | Techniques for programming programmable logic array devices |
US6115769A (en) * | 1996-06-28 | 2000-09-05 | Lsi Logic Corporation | Method and apparatus for providing precise circuit delays |
DE19724088C2 (de) * | 1997-06-07 | 1999-08-05 | Fraunhofer Ges Forschung | Spannungsgesteuerter Ring-Oszillator |
US6415008B1 (en) | 1998-12-15 | 2002-07-02 | BéCHADE ROLAND ALBERT | Digital signal multiplier |
US6557066B1 (en) | 1999-05-25 | 2003-04-29 | Lsi Logic Corporation | Method and apparatus for data dependent, dual level output driver |
US6294937B1 (en) | 1999-05-25 | 2001-09-25 | Lsi Logic Corporation | Method and apparatus for self correcting parallel I/O circuitry |
JP2003060060A (ja) * | 2001-08-21 | 2003-02-28 | Fujitsu Ltd | 半導体集積回路装置 |
US6731179B2 (en) * | 2002-04-09 | 2004-05-04 | International Business Machines Corporation | System and method for measuring circuit performance degradation due to PFET negative bias temperature instability (NBTI) |
US6963250B2 (en) * | 2003-11-20 | 2005-11-08 | International Business Machines Corporation | Voltage controlled oscillator with selectable frequency ranges |
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US4023110A (en) * | 1975-12-04 | 1977-05-10 | The United States Of America As Represented By The Secretary Of The Army | Pulse comparison system |
JPS5937611B2 (ja) * | 1979-01-17 | 1984-09-11 | 株式会社日本自動車部品総合研究所 | 抵抗容量型発振回路 |
US4322643A (en) * | 1980-04-28 | 1982-03-30 | Rca Corporation | Digital phase comparator with improved sensitivity for small phase differences |
DE3115057C2 (de) * | 1981-04-14 | 1984-03-29 | Siemens AG, 1000 Berlin und 8000 München | Phasenregelkreis mit einem digitalen Phasendiskriminator |
US4388536A (en) * | 1982-06-21 | 1983-06-14 | General Electric Company | Pulse generator for IC fabrication |
US4517532A (en) * | 1983-07-01 | 1985-05-14 | Motorola, Inc. | Programmable ring oscillator |
EP0395118A1 (fr) * | 1984-07-31 | 1990-10-31 | Yamaha Corporation | Circuit de retard pour signal analogique |
US4965815A (en) * | 1988-07-21 | 1990-10-23 | U.S. Philips Corporation | Phase detection circuit for stepwise measurement of a phase relation |
US5059924A (en) * | 1988-11-07 | 1991-10-22 | Level One Communications, Inc. | Clock adapter using a phase locked loop configured as a frequency multiplier with a non-integer feedback divider |
KR930000965B1 (ko) * | 1989-08-17 | 1993-02-11 | 금성 일렉트론 주식회사 | 프로그래머블 구형파 발생기 |
US5045811A (en) * | 1990-02-02 | 1991-09-03 | Seagate Technology, Inc. | Tuned ring oscillator |
US5119045A (en) * | 1990-05-07 | 1992-06-02 | Ricoh Company, Ltd. | Pulse width modulation circuit |
-
1991
- 1991-07-15 DE DE4123388A patent/DE4123388A1/de not_active Withdrawn
-
1992
- 1992-07-06 SG SG1996004395A patent/SG47792A1/en unknown
- 1992-07-06 EP EP92914310A patent/EP0594670B1/fr not_active Expired - Lifetime
- 1992-07-06 KR KR1019940700076A patent/KR100239988B1/ko not_active IP Right Cessation
- 1992-07-06 DE DE59208957T patent/DE59208957D1/de not_active Expired - Lifetime
- 1992-07-06 US US08/175,369 patent/US5448205A/en not_active Expired - Lifetime
- 1992-07-06 JP JP50254693A patent/JP3347729B2/ja not_active Expired - Fee Related
- 1992-07-06 WO PCT/EP1992/001519 patent/WO1993002504A1/fr active IP Right Grant
-
1994
- 1994-01-14 FI FI940202A patent/FI110728B/fi active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107193533A (zh) * | 2017-07-31 | 2017-09-22 | 南京航空航天大学 | 一种新型低成本高速真随机数发生器 |
CN107193533B (zh) * | 2017-07-31 | 2020-08-18 | 南京航空航天大学 | 一种低成本高速真随机数发生器 |
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Publication number | Publication date |
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EP0594670A1 (fr) | 1994-05-04 |
FI940202A0 (fi) | 1994-01-14 |
FI940202A (fi) | 1994-01-14 |
JP3347729B2 (ja) | 2002-11-20 |
DE59208957D1 (de) | 1997-11-13 |
FI110728B (fi) | 2003-03-14 |
SG47792A1 (en) | 1998-04-17 |
US5448205A (en) | 1995-09-05 |
WO1993002504A1 (fr) | 1993-02-04 |
JPH06508971A (ja) | 1994-10-06 |
DE4123388A1 (de) | 1993-01-21 |
KR100239988B1 (ko) | 2000-01-15 |
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