EP0558055B1 - Dispositif semi-conducteur comprenant une couche d'oxyde d'indium-étain - Google Patents

Dispositif semi-conducteur comprenant une couche d'oxyde d'indium-étain Download PDF

Info

Publication number
EP0558055B1
EP0558055B1 EP93103100A EP93103100A EP0558055B1 EP 0558055 B1 EP0558055 B1 EP 0558055B1 EP 93103100 A EP93103100 A EP 93103100A EP 93103100 A EP93103100 A EP 93103100A EP 0558055 B1 EP0558055 B1 EP 0558055B1
Authority
EP
European Patent Office
Prior art keywords
film
insulating film
porous
semiconductor device
ito
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP93103100A
Other languages
German (de)
English (en)
Other versions
EP0558055A1 (fr
Inventor
Masaru Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP35855992A external-priority patent/JPH05303116A/ja
Application filed by Canon Inc filed Critical Canon Inc
Publication of EP0558055A1 publication Critical patent/EP0558055A1/fr
Application granted granted Critical
Publication of EP0558055B1 publication Critical patent/EP0558055B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0224Electrodes
    • H01L31/022466Electrodes made of transparent conductive layers, e.g. TCO, ITO layers
    • H01L31/022475Electrodes made of transparent conductive layers, e.g. TCO, ITO layers composed of indium tin oxide [ITO]
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136277Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
    • G02F1/136281Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon having a transmissive semiconductor substrate

Definitions

  • the present invention relates to a semiconductor device having an indium-tin-oxide (ITO) film which is in contact with a semiconductor or a metal.
  • ITO indium-tin-oxide
  • an insulating film has hitherto been provided between a pixel electrode and an oriented film with a view to preventing the liquid crystal from leaking (Japanese Patent Laid-Open No. 57-76525).
  • an ITO film is used as a pixel electrode in the above-described prior art
  • an insulating film in contact with an ITO film is formed of a compound containing oxygen, such as SiO 2
  • the semiconductor device may be thermally unstable, ohmic contact cannot be made, the resistance value of ITO increases, variations in characteristics occur, or delay time increases.
  • a generic semiconductor device comprising a first insulating film consisting of silicon nitride (SiN x ) in contact with an indium-tin-oxide (ITO).
  • SiN x silicon nitride
  • ITO indium-tin-oxide
  • a semiconductor device for liquid crystal device comprising TaO x formed between indium-tin-oxide of a pixle electrode and SiN x .
  • the other surface of the indium-tin-oxide is arranged on the surface of a glass substrate.
  • both sides of the indium-tin-oxide are contacted to oxygen containing materials.
  • the object of the invention is to provide a semiconductor device which can be operated at high speed with low power consumption.
  • a semiconductor device is provided to be used in a photoelectric converting device and in a liquid-crystal display device having high-image quality.
  • Fig. 1 is a sectional view of a liquid-crystal display device in which a semiconductor device of the present invention is used.
  • polysilicon thin film transistor TFT
  • An ITO film 107 is formed thereon with a first insulating film 106 provided in between, and a second insulating film 108 is formed on the ITO film 107.
  • Reference numeral 102 denotes a channel area of a polysilicon TFT; reference numeral 103 denotes a gate oxide film thereof; reference numeral 104 denotes a gate electrode thereof; and reference numeral 105 denotes a source/drain area thereof.
  • the first insulating film 106 and the second insulating film 108 are formed of SiN x films.
  • the reason for this is to prevent the composition ratios of In-O and Sn-O of the ITO film 107 from varying because oxygen within the insulating film is diffused, thereby increasing the resistance value (Fig. 9), and to prevent the ohmic property of the insulating film from being lost because oxygen within the insulating film is diffused (Figs. 10 and 11) since the film is present on an ITO/Si contact portion particularly in the second insulating film 108.
  • SiN x means a film in which the stoichiometric composition of Si 3 N 4 is varied.
  • the thickness of a film with SiN x as the main constituent is preferably from 300 ⁇ to 2 ⁇ m in the present invention. When the thickness is less than 300 ⁇ , the insulation properties of the film cannot be ensured. When the thickness is greater than 2 ⁇ m, the stress of the film increases and the film becomes likely to peel.
  • a more preferable range for the thickness of a film with SiN x as the main constituent is from 500 ⁇ to 1.5 ⁇ m.
  • Fig. 9 shows changes in the resistance value of ITO when a sputtered insulating film was formed directly on ITO under the conditions of 4 KW and 4 mmTorr after a vacuum of 10 -6 Torr had been reached.
  • Fig. 2 is a sectional view of a liquid-crystal display device in which a semiconductor device of this embodiment is used.
  • TFT is formed on an Si substrate 201.
  • a first insulating film 210, a second insulating film 212, and a third insulating film 214 are each formed of an SiN x film.
  • the Si substrate 201 is removed by etching a light transmission area from the rear surface of the Si substrate 201 after TFT is formed in a step to be described later.
  • LOCOS localized oxidation of silicon
  • a gate oxide film 205 is formed.
  • Polycrystalline Si is formed as a gate electrode 206 and patterned.
  • a source/drain area 207 is formed using the gate electrode 206 by ion implantation on the basis of self-alignment.
  • an interlayer insulating film 208 is formed, a window is provided in a predetermined portion, and metallic wiring 209 is performed.
  • an SiN x film which serves as the first insulating film 210 is formed by use of plasma CVD.
  • SiN x films which serve as the ITO films 211 and 213, the second insulating film 212, and the third insulating film 214 are in turn formed.
  • the semiconductor device shown in Fig. 3(c) is obtained.
  • SiN x is used as storage capacitance in the second insulating film 212, SiN x having a dielectric constant greater than that of SiO 2 can be formed into a thick film, which is advantageous with respect to pinholes or the like.
  • SiN x is advantageous over SiO 2 in terms of protection capability (resistance to humidity, resistance to ions or the like) in the third insulating film 214.
  • An SOI substrate is not limited to a specific substrate.
  • a liquid-crystal element, a liquid-crystal driving circuit and other peripheral driving circuits can be formed on one substrate at the same time by using a substrate having a monocrystalline Si layer manufactured by the method described below. This is a preferable feature.
  • the monocrystalline Si layer of the semiconductor substrate is formed by using a porous Si base in which a monocrystalline Si base is made porous.
  • An observation using a transmission type electron microscope shows that holes having an average diameter of approximately 600 ⁇ are formed in the porous Si base.
  • the monocrystallinity of the porous Si base is maintained in spite of the fact that the density of the porous Si is one-half or less than that of monocrystalline Si. It is possible to epitaxially grow a monocrystalline Si layer toward the upper portion of the porous layer. However, internal holes are rearranged above 1,000°C, and enhanced etching characteristics deteriorate.
  • the following low-temperature growth methods are considered preferable for the epitaxial growth of the Si layer: a monomolecular-beam epitaxial growth method, a plasma CVD method, a thermal CVD method, an optical CVD method, a bias sputtering method, and a liquid-crystal growth method.
  • a Si monocrystalline base is prepared.
  • This base is made porous by an anodization method using an HF solution. Even though the concentration of monocrystalline Si is 2.33 g/cm 3 , the concentration of the porous Si base can be changed from 0.6 to 1 g/cm 3 by varying the concentration of the HF solution from 20 to 50 wt%.
  • This porous layer is readily formed into a porous Si base due to the reasons described below:
  • P-type Si can be made porous during an investigation on electrolytic polishing of semiconductors.
  • a Si dissolution reaction during anodization positive holes are required in the Si anodization reaction within the HF solution.
  • the reaction can be expressed as follows: Si + 2HF + (2-n)e + ⁇ SiF 2 + 2H + + ne - SiF 2 + 2HF ⁇ SiF 4 + H 2 SiF 4 + 2HF ⁇ H 2 SiF 6 , or Si + 4HF + (4- ⁇ )e + ⁇ SiF 4 + 4H + + ⁇ e - SiF 4 + 2HF ⁇ H 2 SiF 6 where e + and e - represent positive holes and electrons, respectively, and n and ⁇ each indicate the number of positive holes required to dissolve one atom of Si.
  • n > 2 or ⁇ > 4 porous Si is formed. It may be said from the above that P-type Si containing positive holes can easily be made porous.
  • Si can be made porous irrespective of whether Si is of P-type or N-type.
  • the density of the layer decreases by one half.
  • the surface area of the porous layer is markedly increased as compared with the volume thereof, its chemical etching speed is made considerably faster in comparison with an ordinary etching speed for a monocrystalline layer.
  • a starting material for porous Si formed by anodization is not limited to monocrystalline Si, but Si of other crystalline structures may also be used.
  • a monocrystalline Si thin film is formed by epitaxially growing Si on the porous Si base formed in the above manner.
  • the thickness of the monocrystalline Si thin film is preferably less than 50 ⁇ m and, more preferably, less than 20 ⁇ m.
  • a base which will eventually form a substrate is prepared and the oxidized film on the surface of the monocrystalline Si thin film is laminated on the base.
  • the surface of the newly prepared monocrystalline Si thin film is oxidized, the surface is laminated on the monocrystalline Si layer on the porous Si base.
  • the reason for providing the oxidized film between the base and the monocrystalline Si layer is that when, for example, glass is used as a base, the characteristics of an electronic device can be enhanced considerably. This is because the interface level which depends on the substrate interface of a Si active layer, the level of the oxide film interface can be made lower than that of a glass interface.
  • a monocrystalline Si thin film in which porous Si gas is removed by selective etching which will be described later may be laminated on a new base.
  • the film and the base are brought into complete contact by merely making them contact each other at room temperature after the respective surfaces thereof are cleaned to such an extent that the film and the base cannot be peeled off from each other easily by a van der Waals force, they are heat treated in a nitrogen atmosphere at a temperature of 200 to 900°C, more preferably 600 to 900°C, so that they are completely laminated to each other.
  • a Si 3 N 4 layer is deposited as an etching preventing layer on the entire surface of each of two laminated bases, and then only the Si 3 N 4 layer on the surface of the porous Si base is removed.
  • Abietic acid wax may also be used instead of the Si 3 N 4 layer.
  • a semiconductor substrate having a thin-film monocrystalline Si layer can be obtained by removing the entire porous Si base by means of etching or the like.
  • etching solutions which have no etching effect on crystal Si and are capable of selectively etching only porous Si are: hydrofluoric acid, bufferred hydrofluoric acid, such as ammonium fluoride (NH 4 F) or hydrogen fluoride (HF), a solution of hydrofluoric acid or bufferred hydrofluoric acid mixed with a hydrogen peroxide solution, a solution of hydrofluoric acid or bufferred hydrofluoric acid mixed with alcohol, or a solution of hydrofluoric acid or bufferred hydrofluoric acid mixed with a hydrogen peroxide solution and alcohol.
  • bufferred hydrofluoric acid such as ammonium fluoride (NH 4 F) or hydrogen fluoride (HF)
  • a solution of hydrofluoric acid or bufferred hydrofluoric acid mixed with a hydrogen peroxide solution a solution of hydrofluoric acid or bufferred hydrofluoric acid mixed with alcohol, or a solution of hydrofluoric acid or bufferred hydrofluoric acid mixed with a hydrogen peroxide solution and alcohol.
  • the etching speed depends upon the concentration and temperature of the solution of hydrofluoric acid, bufferred hydrofluoric acid, and the hydrogen peroxide solution.
  • the addition of the hydrogen peroxide solution permits the oxidation of Si to be faster than when such an addition is not made. Further, the reaction speed can be controlled by varying the ratio of the hydrogen peroxide solution.
  • the reaction produced air bubbles caused by the etching can be removed instantaneously from the etching surface without stirring. Thus, porous Si can be etched uniformly and efficiently.
  • the HF concentration of bufferred hydrofluoric acid is preferably set at 1 to 95 wt%, more preferably at 1 to 85 wt%, and even more preferably at 1 to 70 wt%.
  • the NH 4 concentration of bufferred hydrofluoric acid is preferably set at 1 to 95 wt%, more preferably at 5 to 90 wt%, and even more preferably at 5 to 80 wt%.
  • the HF concentration is preferably set at 1 to 95 wt%, more preferably at 5 to 90 wt%, and even more preferably at 5 to 80 wt%.
  • the H 2 O 2 concentration is preferably set at 1 to 95 wt%, more preferably at 5 to 90 wt%, and even more preferably at 10 to 80 wt%. That is, the concentration is set in a range in which the effect of the hydrogen peroxide solution can be exhibited.
  • the alcohol concentration is preferably set at 80 wt% or less, more preferably at 60 wt% or less, and more preferably at 40 wt% or less. That is, the concentration is set in a range in which the effect of the alcohol can be exhibited.
  • the temperature is preferably set at 0 to 100°C, more preferably at 5 to 80°C, and even more preferably at 5 to 60°C.
  • a monocrystalline Si layer is formed on a large area of the entire area of the semiconductor substrate produced in the above manner in such a way that the layer is formed into a flat and uniform thin layer equivalent to an ordinary Si wafer.
  • a liquid-crystal display device was manufactured in the same way as in the second embodiment except that the third insulating film 214 was formed into a stacked structure formed of an SiN x film 221 and an SiO 2 film 222.
  • the insulating film is formed into a stacked structure, stress can be softened and pinholes can be prevented. Since the SiN x film 221 serves as an oxygen barrier, insulating films containing oxygen may also be used. Examples of materials for the films other than films with SiN x as the main constituent are: SiO 2 , polyimide, Ta 2 O 5 , PSG (phospho-silicate glass) and AsSG (arsenic silicate glass). The same effect can also be obtained if the stacked structure is used in the second insulating film 212.
  • a liquid-crystal display device was manufactured in the same way as in the second embodiment except that the second insulating film 212 was formed into a stacked structure formed of the SiN x film 221 and a Ta 2 O 5 film 223.
  • gradation is superior because the dielectric constant of the Ta 2 O 5 film 223 is high.
  • examples having a dielectric constant equivalent to that of p-SiN, in addition to Ta 2 O 5 are: TiO 2 , Al 2 O 3 , PbTiO 3 , PZT (composite oxide of Pb, Zr and Ti), and KTN (composite oxide of K, Ta and Nb).
  • Fig. 7 is a sectional view of a photoelectric converting device in which a semiconductor device of the present invention is used.
  • Fig. 8 is a plan view thereof. This is an example of an application into a bipolar type photoelectric converting device having a control electrode provided on a base. A considerable decrease in an opening ratio is caused by an emitter output electrode. The opening ratio can be increased by 10% by replacing the electrode with ITO.
  • Reference numeral 301 denotes a collector area (N + ); reference numeral 302 denotes a base area (P - ); reference numeral 303 denotes a gate oxide film; reference numeral 304 denotes a base control electrode; reference numeral 305 denotes a base area (N + ); reference numeral 306 denotes an emitter area (N + ); and reference numeral 312 denotes metallic wiring.
  • An emitter electrode 308 is formed of ITO.
  • Reference numerals 307, 309 to 311 denote a first to a fourth insulating film, respectively.
  • the first and second insulating films 307 and 309 are formed of SiN x films.
  • a third and a fourth insulating film 310 and 311 are not necessarily formed of SiN x films because the films 310 and 311 are not directly in contact with the emitter electrode (ITO) 308, and no problem is posed even if SiO 2 type insulating films may be used.
  • a high-speed semiconductor device whose characteristics, such as the resistance value of ITO, do not change and which consumes a small amount of power can be obtained.
  • a liquid-crystal display device having high image quality and a photoelectric converting device can be obtained by using the semiconductor device.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Claims (4)

  1. Dispositif à semiconducteurs, comprenant un film d'oxyde d'indium-étain (107 ; 211 ; 213 ; 308) qui est électriquement en contact avec un semiconducteur ou un métal, dans lequel une surface dudit film d'oxyde d'indium-étain (107 ; 211 ; 213 ; 308) est en contact avec une face d'un film de nitrure de silicium de 30 nm à 2 µm d'épaisseur (106 ; 210 ; 212 ; 221 ; 307) et dans lequel un film d'oxyde (103 ; 204 ; 222 ; 223 ; 303) est en contact avec l'autre face dudit film de nitrure de silicium.
  2. Dispositif à semiconducteurs suivant la revendication 1, dans lequel le film d'oxyde (103 ; 222 ; 223 ; 303) est présent sur la surface du film de nitrure de silicium (106 ; 221 ; 307).
  3. Dispositif à semiconducteurs suivant la revendication 1 ou 2, dans lequel un film isolant (108 ; 214 ; 212 ; 210 ; 309) comprenant du nitrure de silicium est présent sur une autre surface dudit film d'oxyde d'indium-étain (107 ; 213 ; 211 ; 308).
  4. Dispositif à semiconducteurs suivant une des revendications 1 à 3, dans lequel le film d'oxyde consiste en oxyde de silicium.
EP93103100A 1992-02-28 1993-02-26 Dispositif semi-conducteur comprenant une couche d'oxyde d'indium-étain Expired - Lifetime EP0558055B1 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP75879/92 1992-02-28
JP7587992 1992-02-28
JP7587992 1992-02-28
JP35855992A JPH05303116A (ja) 1992-02-28 1992-12-28 半導体装置
JP358559/92 1992-12-28
JP35855992 1992-12-28

Publications (2)

Publication Number Publication Date
EP0558055A1 EP0558055A1 (fr) 1993-09-01
EP0558055B1 true EP0558055B1 (fr) 2000-11-02

Family

ID=26417045

Family Applications (1)

Application Number Title Priority Date Filing Date
EP93103100A Expired - Lifetime EP0558055B1 (fr) 1992-02-28 1993-02-26 Dispositif semi-conducteur comprenant une couche d'oxyde d'indium-étain

Country Status (2)

Country Link
EP (1) EP0558055B1 (fr)
DE (1) DE69329603T2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07221174A (ja) * 1993-12-10 1995-08-18 Canon Inc 半導体装置及びその製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03502148A (ja) * 1987-10-15 1991-05-16 ステムコー コーポレーション 低ノイズ光検出及びそのための光検出器
US4990460A (en) * 1989-01-27 1991-02-05 Nec Corporation Fabrication method for thin film field effect transistor array suitable for liquid crystal display

Also Published As

Publication number Publication date
DE69329603D1 (de) 2000-12-07
DE69329603T2 (de) 2001-05-10
EP0558055A1 (fr) 1993-09-01

Similar Documents

Publication Publication Date Title
US5714790A (en) Semiconductor device with an indium-tin-oxide in contact with a semiconductor or metal
JP3191972B2 (ja) 半導体基板の作製方法及び半導体基板
EP0528229B1 (fr) Procédé de fabrication d'un substrat semi-conducteur
Shi et al. Characterization of low-temperature processed single-crystalline silicon thin-film transistor on glass
US5750000A (en) Semiconductor member, and process for preparing same and semiconductor device formed by use of same
EP0553775B1 (fr) Procédé de fabrication d'un dispositif semi-conducteur
US6118151A (en) Thin film semiconductor device, method for fabricating the same and semiconductor device
CN100394563C (zh) 制作薄膜半导体器件的工艺以及液晶显示器
US6891578B2 (en) Method of manufacturing a thin-film semiconductor device used for a display region and peripheral circuit region
US7750367B2 (en) Semiconductor member, manufacturing method thereof, and semiconductor device
EP0558007B1 (fr) Connexion électrique entre une région de silicium et une couche d'oxyde comprenant d'indium
US5760443A (en) Silicon on insulator with active buried regions
EP0558055B1 (fr) Dispositif semi-conducteur comprenant une couche d'oxyde d'indium-étain
US5827772A (en) Fabrication process for thin film transistor
JPH05241200A (ja) 液晶表示装置
JP2834928B2 (ja) 半導体素子
JP3101779B2 (ja) 液晶表示装置
JP2864658B2 (ja) 薄膜トランジスタの製造方法
JPH05241139A (ja) 液晶表示装置
JPH06204168A (ja) 半導体装置
JP3016486B2 (ja) 薄膜トランジスタ
JP3128076B2 (ja) バイポーラトランジスタの製造方法及びそれを用いた半導体装置の製造方法
JP3088033B2 (ja) 半導体装置
JPH05232482A (ja) 液晶表示装置
JPH03108319A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB

17P Request for examination filed

Effective date: 19940118

17Q First examination report despatched

Effective date: 19950323

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

REF Corresponds to:

Ref document number: 69329603

Country of ref document: DE

Date of ref document: 20001207

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20090223

Year of fee payment: 17

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20101029

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100301

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20110228

Year of fee payment: 19

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20110224

Year of fee payment: 19

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20120226

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 69329603

Country of ref document: DE

Effective date: 20120901

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120226

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120901