EP0518695B1 - Pre-charge triggering to increase throughput by initiating register output at beginning of precharge phase - Google Patents

Pre-charge triggering to increase throughput by initiating register output at beginning of precharge phase Download PDF

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Publication number
EP0518695B1
EP0518695B1 EP92305434A EP92305434A EP0518695B1 EP 0518695 B1 EP0518695 B1 EP 0518695B1 EP 92305434 A EP92305434 A EP 92305434A EP 92305434 A EP92305434 A EP 92305434A EP 0518695 B1 EP0518695 B1 EP 0518695B1
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EP
European Patent Office
Prior art keywords
input
logic
data
charge
charged
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Expired - Lifetime
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EP92305434A
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German (de)
English (en)
French (fr)
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EP0518695A3 (enrdf_load_stackoverflow
EP0518695A2 (en
Inventor
Aswin N. Mehta
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Texas Instruments Inc
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Texas Instruments Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising

Definitions

  • the invention relates generally to pre-charged digital devices, and more particularly relates to a pre-charge triggering apparatus and method for achieving an increase in throughput by triggering register output at the beginning of the pre-charge phase of a clock cycle (rather than the beginning of the next clock cycle).
  • a pre-charge triggered register is responsive to a PRECHARGE signal (indicating the end of the active phase and the beginning of the pre-charge phase) to transfer the data in the master latch to the output of the register, initiating data input to the following function stage prior to the beginning of the next clock cycle.
  • Microprocessors and other digital systems commonly use synchronous pipelining techniques to increase throughput. These systems are functionally divided into synchronous pipeline stages that generally include an input register followed by a function section with an output section. Each pipeline stage receives its input from an upstream pipeline stage, and after completing its task, makes its output available to a downstream pipeline stage.
  • Synchronous pipeline systems commonly pre-charge lines activated by n-channel transistors HI and lines activated by p-channel transistors LO, thereby taking into account the respective speeds at which these transistor-types propagate HI/LO data values.
  • each clock cycle can be divided into active (or evaluation) and pre-charge phases.
  • the specific problem to which the invention can be applied is increasing register throughput in pre-charged synchronous pipeline systems.
  • a more general problem is reducing the effect of the required pre-charge phase on the throughput of a given pipeline stage.
  • a random access memory will generally include: (a) input address/data registers, (b) a memory section that includes a decoder front-end and a memory cell array defined by wordlines and bitlines, and (c) an output section that includes sense amps and drivers. While pre-charge operations are performed in connection with the memory array (wordlines and bitlines) and the sense amp, implementing pre-charge for the decoder front-end is generally impractical.
  • a valid address/data from an upstream stage may be available at the input address/data registers significantly prior to the beginning of a new clock cycle, i.e., while the memory stage is still in the pre-charge phase of the current clock cycle.
  • This address/data is held at the input registers until the beginning of the new clock cycle and the completion of the pre-charge phase, at which time it is latched by the master latch in the input register and propagates through the slave latch to the decoder front end and from there to the pre-charged memory array.
  • the memory stage awaits the completion of the pre-charge phase even though the valid address/data is available at the input registers.
  • IBM 'I'echnical Disclosure Bulletin Vol. 29 No. 10 (March 1987) pages 447 - 448 discloses a memory device wherein an address buffer and a column decoder, which are CMOS devices that are not pre-charged, are actuated during the pre-charge period.
  • the invention provides a pre-charge triggering method for use in a pre-charged stage which is so controllable by a system clock as to complete its processing in a system clock cycle,
  • the invention also provides a pre-charged stage which is so controllable by a system clock as to complete its processing during a system clock cycle including:
  • the input logic includes a master latch followed by a slave latch and is capable of passing data from the master latch to the slave latch when triggered.
  • the input logic includes a slave pass gate responsive to the system clock for passing input data from the master latch to the slave latch and a pre-charge pass gate responsive to the pre-charge signal for passing input data from the master latch to the slave latch independently of the slave pass gate.
  • the-charged stage is a memory and, preferably, includes an input address/data register connected to front-end decoder logic which is connected to a memory array, the memory array being connected to sense amplifier logic which is connected to output driver logic, the output driver being capable of providing a pre-charge signal and being connected to the input address/data register for triggering the input address/data register.
  • a synchronous pipeline system includes a plurality of the pre-charged stages.
  • the pre-charge triggering technique involves (a) presenting input data to the input register in preparation for the next active phase; (b) prior to the beginning of the next clock cycle, triggering the input register using the PRECHARGE signal; and (c) in response to pre-charge triggering, transferring the input data from the input register to the front-end logic to initiate a new active phase prior to end of the pre-charge phase for the pre-charged logic.
  • This pre-charge triggering technique provides an additional design parameter for improving throughput of a functional stage. That is, throughput improvements may be achieved even for functional stages in which all logic sections can be pre-charged by designing the function section to include non-pre-charged front-end logic such that the pre-charge time for the remaining pre-charge is hidden in the propagation delay through the non-pre-charged front end.
  • the pre-charge triggering technique is used with a synchronous pipeline memory stage that includes input address/data registers, non-pre-charged front-end decoder logic, a pre-charged memory array, and pre-charged output logic.
  • Each input address/data register is a conventional master/slave register to which is added a pre-charge pass gate in parallel with the slave latch pass gate -- when turned on by the PRECHARGE signal, the pre-charge pass gate passes data latched in the master latch through the slave latch to the register output.
  • An upstream pipeline stage presents valid address/data to the input address/data registers prior to the end of the current active phase for the memory stage.
  • the input address/data registers are responsive to the PRECHARGE signal to transfer the valid address/data to the front-end decoder logic, thereby beginning the next active phase prior to the end of the current pre-charge phase.
  • the technical advantages of the invention include the following.
  • the pre-charge triggering technique permits a new active phase to-begin prior to the end of the current pre-charge phase by triggering the start of an active phase using a PRECHARGE signal.
  • the PRECHARGE signal causes data latched in the master latch to be passed through the slave latch to the register output prior to the slave pass gate being triggered at the beginning of the next clock cycle.
  • the PRECHARGE signal can be used to cause valid data at the input register to be passed directly to non-pre-charged front-end logic, initiating a new active phase prior to completing pre-charge of the pre-charged logic, thereby permitting at least a portion of the pre-charge phase to be hidden in the propagation delay through the non-pre-charged front-end logic.
  • pre-charge triggering provides design flexibility in achieving optimum throughput for functional stages through the inclusion of non-pre-charged front-end logic.
  • a minimum throughput improvement corresponding to the propagation delay through the slave pass gate and latch of the input register can be achieved by pre-charge triggering the input register so that data transfer to the following function section begins immediately at the beginning of the next clock cycle (i.e., at the beginning of the next active phase).
  • the exemplary pre-charge triggering technique used in connection with a pipeline stage in a synchronous pipeline system that includes an input register that feeds a function section with both nonpre-charged front-end logic and pre-charged function logic.
  • FIGURE 1a illustrates a portion of a synchronous pipeline system with pipeline stages 10.
  • Each pipeline stage 10 includes an input register 11, followed by a function section 12 and an output section 13.
  • the output section includes pre-charge control logic that activates a PRECHARGE line to provide a PRECHARGE signal at the beginning of the pre-charge phase, i.e., at the end of the active phase.
  • pre-charge control logic that activates a PRECHARGE line to provide a PRECHARGE signal at the beginning of the pre-charge phase, i.e., at the end of the active phase.
  • FIGURE 1b illustrates in more detail one of the pipeline stages.
  • the function section 12 includes non-pre charged front-end logic 12a and pre-charged logic 12b.
  • the output section which may be pre-charged, includes the pre-charge control logic necessary to control the PRECHARGE line.
  • the pre-charge triggering technique requires that the upstream stage complete its active phase so that valid data is available at the input register when it is triggered.
  • the input register is triggered (21) when the PRECHARGE line is switched active, before the next rising clock edge, so that the next active phase begins prior to the beginning of the next clock cycle (and prior to the end of the pre-charge phase of the current clock cycle).
  • Input data present at the input register is then transferred (22) to the front-end logic 12a. Because the front-end logic does not have to wait for the pre-charge phase to complete, it immediately begins processing the input data.
  • the output of the front-end logic 12a is available for the pre-charged logic 12b -- front-end logic output is disabled until the pre-charge control logic indicates that the pre-charge phase is complete.
  • the pre-charge control logic switches the PRECHARGE line inactive, indicating the end of the pre-charge phase, and the output of the front-end logic is passed (23) to the pre-charged logic.
  • the pre-charge control logic in the output logic section switches the PRECHARGE line (21) active, initiating both the next pre-charge phase and the next active phase.
  • the PRECHARGE signal (a) switches active, initiating the next active phase, when the current active phase is complete and valid data is available from the output logic section 13, and (b) switches inactive, indicating the end of the pre-charge phase, in synchronism with the rising edge of the system clock.
  • Throughput increase is obtained by initiating the next active phase at the beginning of the current pre-charge phase, passing input data to the non-pre-charged front-end logic while the pre-charged logic is still in the pre-charge phase, so that at least a portion of the pre-charge phase can be hidden in the propagation delay through the front-end.
  • the amount of the pre-charge delay that can be hidden depends upon the relative duration of the front-end propagation delay and the pre-charge phase.
  • FIGURES 1c and 1d illustrate the difference between a pipeline stage that do not use pre-charge triggering, and pipeline stages that do.
  • the increase in throughput obtained by pre-charge triggering will be seen to be the duration of the pre-charge phase (assuming that the entire pre-charge phase can be hidden in the propagation delay through non-pre-charged front-end logic).
  • the period of the clock cycle coincides with the period of the active/pre-charge cycle.
  • a new clock cycle (rising clock edge) begins a new active phase.
  • the active phase ends and the pre-charge phase begins.
  • the pre-charge phase ends, and a new active phase begins at T1 (with the beginning of the next clock cycle).
  • an active phase begins at time TO and ends at time T1, corresponding to the beginning of the pre-charge phase -- at the same time, T1, the next active phase begins (i.e., during the current pre-charge phase).
  • the current pre-charge phase ends.
  • subsequent active phases are initiated at times T2 and T3 corresponding to the beginning of the associated pre-charge phase.
  • pre-charge triggering would allow an active/pre-charge cycle time of 20 ns.
  • the system cycle time will generally be determined by the longest active phase and the longest pre-charge phase (which typically, but not necessarily, occur in the same stage).
  • pre-charge triggering certain portions of the pre-charge phases for at least some of the pipeline stages can be hidden in the initial part of the active phase, i.e., the propagation delay through the non-pre-charged front end logic.
  • the throughput gains available from pre-charge triggering are thus factored in to derive a final- system clock cycle time, and the PRECHARGE signal is synchronized to that clock.
  • FIGURE 2 and 3a illustrate exemplary implementations of the pre-charge triggering technique described in Section 1:
  • FIGURE 2 illustrates a pre-charge triggered register;
  • FIGURE 3a illustrates a pre-charge triggered memory stage of a synchronous pipelined system.
  • the exemplary pre-charge triggered register is implemented from a conventional master/slave register modified to provide pre-charge triggering.
  • the normal register configuration comprises a master pass gate PGM and a master latch M, followed by a slave pass gate PGS and a slave latch S.
  • the clock is applied directly to the slave pass gate and through an invertor to the master pass gate.
  • a rising clock edge closes the master pass gate PGM, latching the input data into the master latch, and opens the slave pass gate, passing the latched data on to the register output (with a propagation delay of one pass gate and one invertor).
  • Pre-charge triggering is implemented by incorporating a pre-charge pass gate PGP in parallel with the slave pass gate PGS.
  • the register output can be triggered by a PRECHARGE signal opening the pre-charge pass gate PGP, passing data in the master latch through the slave latch to the register output even in the absence of a rising clock edge at PGM and PGS.
  • valid data must be in the master latch prior to the receipt of the PRECHARGE signal, and must remain valid at least until the next rising clock edge closes the master pass gate to isolate the register output from logic level changes on the register input.
  • the exemplary pre-charge triggered memory stage of a pipeline system is implemented using a conventional memory stage, which is modified to include a pre-charge triggered input address/data register ADR configured for pre-charge triggering as described in Section 2.1.
  • the pre-charged memory includes an input address register AR that passes addresses from the input to the following memory section, which includes non-pre-charged front-end decoder logic DEC, a memory array MEM, sense amp logic SA, and output driver logic OD.
  • the output driver logic includes pre-charge control logic that controls a PRECHARGE line coupled to the address register AR.
  • FIGURE 3b provides waveforms for the various logic sections that illustrate the operation of the pre-charge triggered memory stage, including pre-charge triggering.
  • the system clock CLK and the PRECHARGE waveform (indicating active and pre-charge phases) are also shown.
  • a valid input address (from an upstream stage) is assumed to be available at the input address register AR (waveform IN) for a time longer than the set up time for the master latch (waveform M), and at a time prior to the PRECHARGE line being driven HI to indicate the start of the pre-charge phase (and the end of the active phase).
  • This input address is held in the input address register because the slave pass gate is closed (waveform S).
  • a PRECHARGE signal triggers the input address register AR (i. e., opens the pre-charge pass gate), and the input address is passed to the front-end decoder logic (waveform DEC), beginning the next active phase.
  • the memory array MEM, the sense amp SA and output driver OD are still in the current pre-charge phase (waveforms MEM, SA, and OD).
  • the decoded address is ready for input to the memory array MEM. If the propagation delay for the front-end decoder logic is less than the pre-charge delay, then the decoded address is held at the output of the decoder logic until the end of the pre-charge phase (i.e., the PRECHARGE signal is also used to enable decoder output to the memory array).
  • the pre-charge control logic pulls the PRECHARGE line LO, signalling the end of the current pre-charge phase. Since the next active phase began with the PRECHARGE signal (PRECHARGE line HI), the decoded address is already available to be applied to the memory array (assuming that the propagation delay through the decoder logic is no longer than the pre-charge phase).
  • the input address activates the appropriate wordlines and bitlines to retrieve the addressed data, which is sensed by the sense amp logic SA and output by the output driver logic OD (waveforms MEM, SA, and OD).
  • the pre-charge control logic drives the PRECHARGE line HI, indicating the end of the active phase, and the beginning of the next pre-charge phase for the memory array, sense amp logic, and output driver logic. This operation, in turn, begins the next active phase by passing the next input address from the input address register to the front-end decoder logic.
  • the pre-charge triggering technique provides an additional design parameter for increasing throughput of a pre-charged pipeline system.
  • initiating the next active phase at the beginning of the current pre-charge phase enables at least a portion of the pre-charge delay to be hidden in the front-end propagation delay.
  • designing the stage to include a non-pre-charged front-end may yield a throughput dividend that offsets any penalty from not pre-charging the front-end.
  • a throughput increase of at least one slave pass gate plus one slave invertor is obtainable by pre-charge triggering the input register so that input data is already available at the register output at the end of the pre-charge phase (i.e., at the beginning of the clock cycle).

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  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)
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EP92305434A 1991-06-12 1992-06-12 Pre-charge triggering to increase throughput by initiating register output at beginning of precharge phase Expired - Lifetime EP0518695B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US71419091A 1991-06-12 1991-06-12
US714190 1991-06-12

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EP0518695A2 EP0518695A2 (en) 1992-12-16
EP0518695A3 EP0518695A3 (enrdf_load_stackoverflow) 1995-02-01
EP0518695B1 true EP0518695B1 (en) 1999-12-29

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US (1) US5471158A (enrdf_load_stackoverflow)
EP (1) EP0518695B1 (enrdf_load_stackoverflow)
JP (1) JPH05258079A (enrdf_load_stackoverflow)
KR (1) KR100356883B1 (enrdf_load_stackoverflow)
DE (1) DE69230484T2 (enrdf_load_stackoverflow)

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Publication number Priority date Publication date Assignee Title
US5684422A (en) * 1995-01-25 1997-11-04 Advanced Micro Devices, Inc. Pipelined microprocessor including a high speed single-clock latch circuit
US5623450A (en) * 1995-09-08 1997-04-22 International Business Machines Corporation Conditional recharge for dynamic logic
US8255748B2 (en) * 2009-03-31 2012-08-28 Freescale Semiconductor, Inc. Soft error and transient error detection device and methods therefor

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US4611133A (en) * 1983-05-12 1986-09-09 Codex Corporation High speed fully precharged programmable logic array
JPH0810751B2 (ja) * 1983-12-23 1996-01-31 株式会社日立製作所 半導体装置
JPS60176277A (ja) * 1984-02-22 1985-09-10 Nec Corp ガリウム砒素集積回路
JPS60183764A (ja) * 1984-03-02 1985-09-19 Oki Electric Ind Co Ltd ＧａＡｓ論理回路装置
JPS62167193A (ja) * 1986-01-17 1987-07-23 住友金属工業株式会社 リフテイングマグネツトの吊荷検知方法
FR2595859B1 (fr) * 1986-03-14 1988-05-13 Radiotechnique Compelec Memoire avec tampon amplificateur
FR2603146B1 (fr) * 1986-08-19 1988-11-10 Thomson Csf Source de courant de type charge active et son procede de realisation
JPS6346779A (ja) * 1986-08-15 1988-02-27 Nec Corp 半導体装置
US4701646A (en) * 1986-11-18 1987-10-20 Northern Telecom Limited Direct coupled FET logic using a photodiode for biasing or level-shifting
JPS63156367A (ja) * 1986-12-20 1988-06-29 Fujitsu Ltd レベル・シフト・ダイオ−ド
JPH0691431B2 (ja) * 1987-03-02 1994-11-14 沖電気工業株式会社 フリツプフロツプ回路用クロツク制御回路
JPH01227478A (ja) * 1988-03-08 1989-09-11 Fujitsu Ltd 半導体装置
JP2969630B2 (ja) * 1988-10-25 1999-11-02 日本電気株式会社 読出し回路
JPH02148740A (ja) * 1988-11-29 1990-06-07 Fujitsu Ltd 半導体装置及びその製造方法

Also Published As

Publication number Publication date
EP0518695A3 (enrdf_load_stackoverflow) 1995-02-01
KR100356883B1 (ko) 2003-01-08
EP0518695A2 (en) 1992-12-16
JPH05258079A (ja) 1993-10-08
DE69230484T2 (de) 2000-07-27
US5471158A (en) 1995-11-28
KR930001058A (ko) 1993-01-16
DE69230484D1 (de) 2000-02-03

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