EP0489757B1 - Unité de commande recevant un signal d'horloge pour une matrice d'affichage sous forme de circuit integré - Google Patents

Unité de commande recevant un signal d'horloge pour une matrice d'affichage sous forme de circuit integré Download PDF

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Publication number
EP0489757B1
EP0489757B1 EP90911990A EP90911990A EP0489757B1 EP 0489757 B1 EP0489757 B1 EP 0489757B1 EP 90911990 A EP90911990 A EP 90911990A EP 90911990 A EP90911990 A EP 90911990A EP 0489757 B1 EP0489757 B1 EP 0489757B1
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EP
European Patent Office
Prior art keywords
shift register
byte
bits
lcd
display matrix
Prior art date
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Expired - Lifetime
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EP90911990A
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German (de)
English (en)
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EP0489757A1 (fr
Inventor
Karl-Heinz Strobel
Max GÖTZ
Robert FÖRSTER
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Siemens AG
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Siemens AG
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/04—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions
    • G09G3/16—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions by control of light from an independent source
    • G09G3/18—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions by control of light from an independent source using liquid crystals

Definitions

  • the invention relates to an improvement of a previously known integrated module with the designation HD44100, which is offered by Hitachi on the market, this known IC primarily serving as a control module of an LCD display.
  • This known IC primarily serving as a control module of an LCD display.
  • the essential features of the known module are defined in the preamble of claim 1.
  • FIG. 1 serves to explain this prior art.
  • a microprocessor ⁇ P calculates e.g. the current speed and the current as well as the average gasoline consumption of a motor vehicle. These values are to be displayed on the LCD display matrix LCD using a chain of control modules 44100/1 ... 44100 / n.
  • the control components 44100/1 .... 44100 / n each have, compared to one another, an identical structure, including a shift register, the input and the output of which are brought out at pins of these control components 44100.
  • These shift registers of the n control modules 44100/1 ... 44100 / n are each connected in series with one another by connecting the corresponding pins connected to the inputs and outputs of these shift registers.
  • the microprocessor ⁇ P controls the display and delivers short codes to an intermediate special module 44780, which only more or less correspond to the content of the characters to be displayed.
  • This special module can e.g. the integrated chip HD44780 manufactured by Hitachi, which among other things contains a character generator, which in turn generates more specific, detailed control signals from the short codes, which are to be supplied to the rows and columns of the display matrix LCD.
  • the character generator of this well-known HD44780 module contains a ROM. It can store the required column signals of characters or combinations of characters. To display a longer text on the display matrix, the microprocessor ⁇ P must supply its own 8-bit code more or less per character: However, this 8-bit code supplied by the microprocessor ⁇ P is still very short compared to the length of the Complete bit pattern formed by the column signals of a single character:
  • the characters to be displayed e.g. Containing 40 pixels each in 8 rows and 5 columns, 8 x 5 column signals S are required per character, because 5 column signals S are to be delivered simultaneously for each activated row.
  • the ROM of the character generator must store 40 line signals, which are to be delivered in 8 series of 5 bits each to the control modules 44100/1 ... ..44100 / n.
  • An 8-bit code of the microprocessor ⁇ P can therefore call up 8 series of 5 column signals S in succession from the ROM of the character generator of the HD44780 module, which the HD44780 (serial) module enters into the input of the shift register of the first IC of the 44100/1 chain. ..44100 / n feeds (- that the block HD44780 can also supply up to 40 columns Sz of the display matrix itself from its character generator is indicated in FIG. 1, but is no longer considered here).
  • That block 44780 thus provides 8 bits for the line signals Z for a one-time (!) Display of this text, which it forwards directly to the lines of the display matrix LCD together for all characters to be displayed.
  • it supplies the many, namely 1600 special column signals S, also generated by its character generator, serially to the input of the first of the n different control modules 44100/1 ... 44100 / n, which in turn generate these column signals S by means of drivers, and thus with corresponding levels , forward to the columns of the LCD display matrix.
  • the display matrix LCD is an LCD display
  • the 8 line signals Z and those 1600 column signals S are cyclically and constantly repeated rapidly - instead of once - to be supplied to the display matrix LCD in order to obtain an optically apparently stationary display.
  • the block 44780 must very often deliver its 8 character signals Z per second for this display and, above all, the same number of times each of its 1600 column signals S.
  • the maximum length of the chain of the control modules 44100/1 .... 44100 / n is limited by the top because the pulse repetition frequency with which the column signals S must be continuously input into the relevant input of the first control module 44100/1 for a display, cannot be increased arbitrarily.
  • the length of the text which can be displayed with a sufficiently calm typeface is therefore very limited in this prior art.
  • the microprocessor ⁇ P and the device 44780 are also heavily loaded because they both emit many bits per second and have to process in order to maintain the calm typeface.
  • Each of these known control modules 44100/1 ... 44100 / n is therefore an IC that serves as a clock-controllable control module of a display matrix LCD, this display matrix LCD also having a long, multi-digit text made up of letters, numbers and / or other characters should be able to display.
  • the display matrix LCD contains columns and rows and thus at least two dimensions, and indeed contains many more columns than rows in order to be able to display the long, often only one-line text.
  • the identically constructed IC's 44100 each form a chain and supply column signals S for controlling the columns of the display matrix LCD, specifically each IC for controlling only a part of those columns.
  • Each IC 44100 contains a shift register, into which bits are shifted, which in turn correspond to the text to be displayed on the display matrix, or at least a section of this text, even in this prior art.
  • the input and the output of the shift register is connected directly - or at most via isolating switches and / or driver stages, which do not change the bit pattern - to pins of the IC, in order to be able to push the bits through the chain one after the other, controlled by the clock, - namely first by the shift register of the first IC of the chain, then by the shift register of the second IC of the chain, and then, if present, by the shift register of the other ICs.
  • the IC is in operation by a control processor ⁇ P, which e.g. Driving speeds and / or other values to be displayed are calculated, controllable, whereby, this control processor ⁇ P - in this prior art only indirectly, namely e.g. about e.g. via the interposed block HD44780 - which supplies bits with which the shift registers of the chain are loaded.
  • a control processor ⁇ P which e.g. Driving speeds and / or other values to be displayed are calculated, controllable, whereby, this control processor ⁇ P - in this prior art only indirectly, namely e.g. about e.g. via the interposed block HD44780 - which supplies bits with which the shift registers of the chain are loaded.
  • control modules for display matrices there are other known control modules for display matrices, - Also those which are used to control the columns if the texts to be displayed are often very long and the number of columns to be controlled is therefore considerably larger than the number of column signal outputs of the relevant display modules.
  • module ⁇ PD7228 which is offered by NEC on the market.
  • This IC has a character generator which converts short codes, which are supplied by a microprocessor, into the concrete column signals of the relevant columns in the IC.
  • each individual control module is to be supplied with the short codes pertaining to this IC via its own lines from the microprocessor, because these ICs have no shift register, which is switched and operated like the control module HD44100.
  • a forwarding of these codes, or a forwarding of the final column signals S from IC to IC, is therefore not provided for the control module ⁇ PD7228, although it serves to control only a part of the columns. If a very long text is to be displayed using this IC ⁇ PD7228, a plurality of such ICs are used, but each of them controls only a part of the columns of the display matrix. The microprocessor therefore has to supply the various ICs with the relevant codes one after the other via their own control lines.
  • control modules SED1503 are described, which have no shift register, which would allow chain connection of such control modules by directly connecting the shift registers of these control modules in series.
  • control modules SED1503 are in a row and together deliver control signals to an LCD display. All of these SED1503 control modules are each directly supplied with the corresponding codes by a microprocessor ⁇ C.
  • the display matrix is subsequently extended - by extending the IC chain using additional control modules, e.g. by the number of column signal outputs from two ICs, then only in the first example, namely the control module HD44100, can the chain be extended without many problems, for the reasons mentioned, namely up to 80 characters with 5 columns.
  • additional wiring measures must be taken so that each of these control blocks is supplied with all the necessary data via its own lines.
  • the intermediate module e.g. HD44780 has to deliver its output signals, namely the column signals S, only to the input of the shift register of the first IC of the chain.
  • the invention is also based on an IC control module which, like module HD44100, can be connected to form a chain such that only the first IC of this chain has to be supplied directly with the bits corresponding to the text.
  • the enormous number of bits corresponding to the column signals S are no longer input into the input of the first shift register of the chain of ICs, but rather only the bits of short codes which approximately correspond in content to the meaning of the characters to be displayed. Only in the relevant ICs are the combinations of column signals associated with the character generated, in each case with the aid of the character generator attached there.
  • the microprocessor is considerably relieved, even if it is to display a very long standard text. Because the codes that are supplied by the microprocessor to the relevant first IC in the chain can often only be formed by a short address.
  • the length of the chain can be practically extended, i.e. that the number of ICs connected in series can be increased practically as desired.
  • this microprocessor can generally supply its data bits directly to the relevant data input of the first IC of the chain without the need to interpose a further module which contains its own character generator, - cf. block 44780 in FIG. 1. Because according to the invention only relatively short codes have to be stored in the shift registers, the shift register of the last IC of this chain can be loaded comparatively quickly with its codes, so that the invention also takes the time required to prepare the display of a new long text is particularly short.
  • the IC according to the invention only shows all of its advantages when several such ICs are connected to form a chain. However, the IC according to the invention can also be used if only a single IC according to the invention is used to display a text which is then always relatively short.
  • FIG. 1 and 2 show that in the invention the IC's IC1 ... ICn also form a chain in that their shift registers are connected in series, so that the short codes supplied by the microprocessor ⁇ P each arrive at the signal input SIN of the shift register of the first IC IC1, and can also be supplied to the signal inputs SIN of the following IC's ... ICn via the signal output SOUT of this shift register.
  • the corresponding signal inputs of the shift registers of the control modules 44100/1 ... 44100 / n were not supplied with the codes, but with much more concrete column signals as very extensive bit patterns with a high expenditure of time.
  • the ICs IC1 ... ICn according to the invention therefore each contain their own character generators, which in turn convert the codes temporarily stored in the shift registers into the many column signals S in the ICs.
  • the microprocessor ⁇ P can directly load the relevant codes - which, for example, each correspond to a single character of the text to be displayed, into the shift register of the first IC of the chain.
  • FIG. 3 and 4 show a further development in which the microprocessor .mu.P can also be operated if necessary in such a way that - apart from possibly also from Microprocessor ⁇ P delivered clock pulses SCK - only extremely few data bits have to deliver to the ROM of a text memory TS additionally installed in the IC, which in turn only loads the shift registers of the chain with - still relatively short - codes, each of which, for example, individual characters or short ones Character combinations of the text correspond.
  • FIG. 3 therefore shows an example of the structure of the circuits in an IC according to the invention.
  • the - e.g. Short codes supplied by the microprocessor ⁇ P can be loaded directly into the input of the shift register SR1 via the data input SIN and directly via the switch S2 (in its position a), which in turn sends short codes supplied by this microprocessor ⁇ P to the data output SOUT via the data output SOUT Data input SIN of the next IC in the chain delivers.
  • FIG. 3 shows schematically that the codes represented by byte 1, byte 2 ... pass through the memory cells of the shift register SR1 one after the other, each byte e.g. eight consecutive memory cells of the shift register SR1 are required. In this case - if no text memory TS is used - the microprocessor ⁇ P immediately delivers all the bits that are loaded into the shift register SR1.
  • the operating mode control BAS determines the position of switches S1 and S2.
  • the operating mode control BAS is in turn symbolically controlled from the outside together with the sequence control AB by a signal SS;
  • FIG. 1 shows a concrete solution for their control. 4 - that is, switch S2 in position a, the data bits supplied by the microprocessor ⁇ P are shifted from the data input SIN directly into and through the shift register SR1 using the clock signal SCK.
  • the data of the shift register SR1 which has already been pushed through appear at the same time and can be delivered there to the data input SIN of a next IC.
  • a particular advantage of the invention results from the fact that the microprocessor ⁇ P - apart from possibly clock pulses SCK also to be supplied by this microprocessor ⁇ P, cf. FIG. 3 and 4a - only have to feed its codes once into the relevant input of the first IC IC1 or master of the chain, even if the character generators CG of all m + 1 ICs have to deliver the column signals S to a display matrix repeatedly, often every second , if the latter, for example is an LCD display!
  • the character generator CG is e.g. a ROM that is addressed by the bytes created. It then successively generates the output signals corresponding to the many concrete column signals S, which in the present example are fed into the further, downstream shift register SR2.
  • the character generator CG thus serves to convert the codes or input data byte 1, byte 2 ... loaded into the shift register SR1 into the column signals S required for the display matrix LCD, in order to generate the desired displays at the corresponding character positions and line positions.
  • the displays and thus the character generator output signals can also be changed during operation of the IC by changing the codes Byte 1, Byte 2 ... are changed from time to time, whereby the displayed texts are changed from time to time.
  • the control effort of the microprocessor ⁇ P, cf. FIG. 2, is particularly small in the invention - even if the text memory TS is not yet used - because the microprocessor ⁇ P only feeds the first IC IC1 of the chain with data, the bits of this data not representing the specific column signals S, but only relatively short codes, which in turn correspond more or less to the content of individual characters to be displayed or to entire groups of characters or combinations of characters to be displayed.
  • the character generators CG of the individual ICs each generate the column signals S to be output by the relevant IC from the codes which are loaded in the shift registers SR1.
  • a special external control signal supplied to the IC can be used, for example by means of the control signal shown in FIG. 3 indicated byte 2, before the display of a (new) text, a special RAM in the character generator CG is also addressed in order to overwrite this RAM, for example with byte 1, what is shown in FIG. 4, which will be explained in more detail later, will be seen even more clearly.
  • This development of the invention allows the special data then stored in the RAM (here, for example, from byte 1) to be used to generate very special column signals S, which are not preprogrammed in the ROM of the character generator CG, but rather are used, for example, for displaying particular rarely used characters that cannot be generated using the ROM of the character generator CG are required - for example for rarely used Greek or Cyrillic characters.
  • the sequence control AB can also take over the clocking for this.
  • the first IC IC1 of the chain can possibly also control the few line signals Z required for the display matrix, specifically for all ICs IC1 ... ICn of the chain, possibly also by means of its sequence control AB, which means that a separate module for controlling the lines the display matrix LCD can be saved.
  • FIG. 3 is additionally connected between the character generator CG and the IC pins, which emit the column signals S to the display matrix LCD, in each case with an output register SR2 and LA, in particular for parallel-serial conversion of the bits.
  • SR2 is also a shift register in terms of structure and operation. As soon as the shift register SR2 is loaded with the corresponding column signal data via the character generator CG, this data is temporarily stored in the further, downstream block “latch and driver output stages” LA and is sent to the column outputs of the IC - i. generally repeated cyclically quickly - output as column signals S. As is already known, an LCD display matrix sometimes needs non-binary column signals S, which therefore have further voltage levels, the output register, cf. LA, and / or assigned output driver stages must then output column signals S which contain more than two voltage levels.
  • the output register can e.g. are formed by a series arrangement of an output shift register SR2 and an output latch register LA. This achieves a particularly reliable, reliable structure of the output register, and in addition the corresponding output latch register in turn considerably reduces the flickering of the text when switching from one line to the next line.
  • FIG. 3 The in FIG.
  • the example of the IC according to the invention shown in FIG. 3 additionally contains the text memory TS, already mentioned several times, with its own ROM, which in each case stores the bits byte 1, byte 2 Start address, which sends the relevant bits byte 1, byte 2 ... to the shift register SR1 of this IC.
  • switch S1 is in its non-conductive state and switch S2 each in its position a.
  • the shift register (s) SR1 of the next further IC / IC's of the chain i.e. in the case of the slaves, is only loaded from the shift register SR1 of the respective previous IC of the chain, but not from the ROM of its own text memory TS Slaves.
  • This operation of the ROM of the text memory TS which is addressable here by way of example by means of a small address shift register ADRL / ADRH, is shown schematically in FIG. 6 shown.
  • the short code supplied by the microprocessor ⁇ P e.g. Bytes can contain 8 bits each, the first byte being one character, but also an almost arbitrarily long character combination of maybe even 100 characters, for which the ROM of the text memory TS only has to be dimensioned large enough - cf. the size of the ROM in the text memory TS in FIG. 4a and 6.
  • the master module IC1 according to the invention - unlike in the prior art, cf. the block 44100/1 in FIG. 1 - for each text to be displayed, only once instead of cyclically, often every second, with input data at the SIN input, even if an LCD display is used as the LCD display matrix.
  • the short e.g.
  • 8-bit code corresponds to e.g. a single character to be displayed or even - in extreme cases even a very long, standardized - word text.
  • a second code supplied by the microprocessor ⁇ P e.g. a second byte can also correspond to an additional numerical value to be displayed.
  • a text memory ROM switched and operated in this way allows the microprocessor ⁇ P to be further relieved.
  • the microprocessor ⁇ P - again apart from clock signals SCK - only delivers very short codes to the ROM of the text memory TS of the master, that is to say the first IC of the chain, but - at least in general - no longer directly to the shift register SR1 of the master IC1.
  • the codes supplied by the microprocessor ⁇ P to the ROM of the text memory TS of the master IC1 can then e.g. also mark a very long standard text, if necessary also contain an associated numerical code, cf. e.g. the text "YOU HAVE EXCEEDED THE MAXIMUM SPEED BY .... km / h!.
  • the text memory TS is e.g. operated as follows:
  • the switches S1 As soon as the switch S1 is closed, the signals of the data input SIN arrive in a special shift register SRZ upstream of the text memory TS and set a counter there a starting address. This start address is used to address the ROM of the text memory TS. In the example shown, the switch S2 can then be switched to position b, for example by means of the operating mode control BAS.
  • the data transmitted with it are first ignored by the shift register SR1 because of the position b of the switch S2 and instead data byte 1, byte 2 ... from the text memory TS , starting from the start address selected by the microprocessor ⁇ P, shifted into the shift register SR1.
  • the counter in the special block of the shift register SRZ is increased, as a result of which the next entry in the ROM of the text memory TS is addressed or prepared.
  • the ROM of the text memory delivers a next byte to the shift register SR2, then the other bytes in a corresponding manner.
  • These bytes supplied in the shift register SR1 can finally be pushed completely through the shift register SR1 and, in the next IC of the chain via its switch S2 in position a, load the shift register SR1 there directly.
  • these bytes byte 1, byte 2 ... correspond more or less to the meaning of individual characters to be displayed or short character combinations, which in turn are only converted into the more specific column signals s by means of the character generators of the individual ICs.
  • FIG. 3 schematically shown example can e.g. according to the much more detailed circuit shown in FIG. 4 shows, set up and operate:
  • the example of an IC according to the invention shown in FIG. 4 has 70 segment lines SEG0 ... SEG69 for 14x5 column signals S which can be output simultaneously.
  • it has 8 backplane lines BPO ; BP7 for 8 line signals Z, here -
  • the multiplex rate is 1: 8 and the line signals Z 4 have voltage levels VO, V1, V3, VLCD, and the column signals 3 voltage levels V0, V2, VLCD.
  • FIGS. 4 and 5 has a latch enable input LE.
  • the values of the shift register contained in SRZ are transferred to the address counter in block SRZ, or the values of shift register SR1 are transferred to latch register LT1.
  • Edge control for example transfer with a rising edge, can be provided.
  • SIN is the data input via which serial, synchronized with the clock pulses SCK, data bits are taken over by the microprocessor, the most significant bit preferably being transmitted first in the example shown.
  • SOUT is the output of the shift register SR1 of the relevant IC, whereby the input SIN of a next IC of the chain can be connected to this output SOUT, cf. also FIGS. 5 and 7.
  • SYNCOUT is an output that is used for synchronization.
  • the output SYNCOUT is connected to the connection SYNCIN.
  • the SYCIN connector is connected to the SYNCOUT output of the master.
  • SYNCIN is therefore an input that is used for synchronization with the master and is set to high in the active state.
  • WRAM is an input which is used to control the transfer of data bits from the shift register SR1 into the RAM of the character generator CG. In the active state, the connection WRAM is set to high, this connection being level-triggerable.
  • CLK is another clock input that can be used to control all internal processes, especially as a "pixel clock" in the example shown.
  • RESETN is a reset connection that is low in the active state and is used to reset internal registers.
  • VDD is used for + 5V logic power supply.
  • VLCD is used to supply positive voltages.
  • V3, V2, V1 are positive auxiliary voltages Voltage divider R shown in FIG. 5 can be generated from VLCD.
  • V0 / GND is the ground connection.
  • connections mentioned are not only shown in FIG. 4, but also in FIG. 5, in order to better illustrate — existing and nonexistent — differences in the power supply and signal supply when comparing the master on the one hand and the slaves on the other hand when using ICs according to the invention according to FIG. 4 can.
  • the sequence control AB consists here, for example, of several divider stages.
  • the first divider stage T / 2 halves the cycle and generates a 4-phase cycle necessary for internal processes.
  • the second divider stage T / 5 reduces the clock rate again to 1/5 and serves to select a column in the 5x8 character matrix of the character generator CG.
  • the third divider stage T / 14 further reduces the clock to 1/14 and is used to select a character position within that section of the display matrix LCD whose columns are controlled by the relevant IC.
  • the fourth sub-stage T / 8 reduces the cycle to 1/8 and serves to select 1 of the 8 lines here.
  • the "Sync. Gen.” level serves for the synchronization of several ICs according to the invention with one another.
  • the IC data input also includes the SIN input for data bits and the SCK input for a clock; these inputs represent a synchronous serial interface.
  • Control signals are thus externally applied to the internal circuit blocks via the inputs C1 and C2.
  • the special shift register "16 bit" in the circuit block SRZ which corresponds to the address shift register ADRL / ADRH in FIG. 6, records the data of the data input SIN in operating mode 2) until a LE pulse follows.
  • the downstream counter ZR can be preset with the word of the shift register "16 bit”. The counter reading is used to address the ROM of the text memory TS.
  • the text memory TS contains a ROM with an 8-bit width here.
  • a multiplexer MUX selects a bit from the 8 bits read from the ROM in each case, which in operating mode 1) is applied to the input of the shift register SR1.
  • a counter Z / 8 in the text memory TS addresses the multiplexer MUX and selects all the bits that are under the relevant ROM address.
  • the counter ZR receives a pulse in block SRZ and addresses the next address in the ROM in order to be able to read the next 8 bits from the ROM.
  • the shift register SR1 is 112 bits long and is divided into 14 groups of 8 bits each. This allows 14 bytes, that is eg control 14 characters via the 70 column lines S or SEGO .... ... SEG69 of the LCD display matrix. The last bit of the shift register SR1 is also fed to the SOUT output.
  • the latch register LT1 is used to store the entire final content of the shift register SR1.
  • the multiplexer MUX1 is used to select an 8-bit group (corresponds to 1 byte) from the 14 bytes stored here in the latch register LT1.
  • the 8-bit output value output by the multiplexer MUX1, i.e. that selected byte, then serves as the address for the memory in the character generator CG.
  • the character generator CG contains a memory which can be addressed by the multiplexer MUX1 and by the sequence control AB and consists here of two parts, cf. ROM and RAM. So part of this memory is ROM and part is RAM. An address decoder ADR.DEC takes over the selection between the RAM and the ROM.
  • each memory entry is 5 bits wide; - This corresponds to the 5 columns, i.e. the number of columns selected here for each character, which is to be displayed in a 5-column x 8-line matrix on the display matrix LCD.
  • the column signals S for rarely needed special characters such as Greek or Cyrillic characters can be written into the RAM of the character generator CG before the text displays begin - eg to the special operating mode for loading this RAM described above.
  • a pulse can be applied to the connection WRAM in order to load the address of the RAM, which can be addressed, for example, with byte 2 of shift register SR1, with the value of byte 1 of shift register SR1.
  • the display matrix LCD is not supplied with column signals S not only by a single IC according to the invention, that is to say alone by the master, so to speak, but if a chain of ICs according to the invention is attached, then the RAM in the character generator CG of each IC of the chain should be Both in the master and in the slave, at least in the case with the desired additional data, if the special character in question is not to be displayed only at those points in the text to be displayed which are supplied with the relevant column signals S by a single IC of the chain .
  • a multiplexer MUX serving as a parallel-series converter at the output of the character generator CG, controlled by the corresponding driver signals of the sequence control AB, selects 1 bit from the 5 bits that are stored by the memory ROM or RAM for the respectively activated line of the character concerned to provide.
  • the 5 bits converted in series in this way therefore serve as an input signal for the further shift register SR2.
  • the coordination of the processes is carried out here by the write / read logic R / W logic of the character generator CG.
  • the further shift register SR2 is 70 bits long here, corresponding to those 14 characters with 5 columns. In this shift register SR2 each bit corresponds to a pixel on one of the lines of the display matrix LCD controlled by the line outputs Z or BP0 ... BP7.
  • the latch register LATCH in the block LA serves as a memory for the content of the shift register SR2, while the further shift register SR2 is already loaded with the column signal data for the next line of the display.
  • the segment driver SEG in block LA is used to generate the necessary here, in some cases, digits of the output voltage profiles which require more than two voltage levels, as are required for controlling LCD display matrices, in particular with a multiplex rate 1: 8, in a manner known per se.
  • the line control ZA here generates from the counter readings of the last divider T / 8 of the sequence control AB the necessary output voltage curves for the lines of the display matrix LCD, which in some cases also have more than 2 levels, as is known per se for controlling an LCD display matrix with a Multiplex rate 1: 8 are required.
  • the master is to emit column signals S to the display matrix, that is to say if no slave is attached, then the IC according to the invention can be operated like the master in FIG. 5. If, on the other hand, one or more slaves are additionally installed, then the ROM of the text memory TS is switched off by a constant high level at C1, cf. FIG 5. All C2 connections from the master and the slaves are connected to one another and controlled jointly by the microprocessor. The SYNCIN inputs of the slaves are each directly connected to the SYNCOUT output of the master.

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  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
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Abstract

Circuit intégré faisant fonction d'élement d'amorçage (IC) synchronisé (CLK, SCK) d'une matrice d'affichage (LCD) servant à l'affichage d'un texte constitué de plusieurs lettres, chiffres et/ou autres signes, dans lequel la matrice d'affichage (LCD) présente un bien plus grand nombre de colonnes que de lignes, de manière à pouvoir afficher au minimum un texte d'une ligne, plusieurs circuits intégrés identiques (IC1...ICn), formant une chaîne, délivrent des signaux de colonne (S) commandant les colonnes de la matrice d'affichage (LCD), chaque circuit intégré commandant une partie des colonnes seulement, le circuit intégré comporte un registre à décalage (SR1) dans lequel sont déplacés les bits (octet 1, octet 2...) qui correspondent au texte à afficher sur la matrice d'affichage ou au moins à une fraction de ce texte, l'entrée (SIN) et la sortie (SOUT) du registre à décalage (SR1) sont reliées directement, ou au plus par l'intermédiaire de sectionneurs (S2) et/ou d'étages excitateurs, à des broches (SIN, SOUT) du circuit intégré pour pouvoir si nécessaire déplacer successivement les bits (octet 1, octet 2) commandés par l'horloge (SCK) à travers les registres à décalage (SR1) de la chaîne (IC1...ICn), le circuit intégré en fonctionnement est commandé par un processeur de commande, sur le circuit intégré un générateur de caractères (CG) possédant sa propre mémoire (ROM) est connecté au registre à décalage (SR1), le générateur de caractères (CG) en fonctionnement transforme au moins une partie des bits (octet 1, octet 2...), qui correspondent chacun pour l'essentiel uniquement à un code court pour la signification intrinsèque des signes concernés, au moyen de la mémoire (ROM/CG) adressée par ces bits (octet 1, octet 2...), en signaux de sortie correspondant aux signaux de sortie (S) du circuit intégré, et en fonctionnement seulement, ces signaux de sortie du circuit intégré sont fournis sous forme de signaux de colonne (S) aux entrées de colonne de la matrice d'affichage (LCD) assignées à ce circuit intégré.

Claims (7)

  1. Unité de commande (IC) pouvant être commandée de façon cadencée (CLK, SCK), réalisée sous la forme d'un circuit intégré, d'une matrice d'affichage (LCD) - par exemple en tant que module de commande (IC) d'un dispositif d'affichage LCD (LCD) dans un calculateur ou ordinateur de bord d'un véhicule automobile, dans laquelle
    - la matrice d'affichage (LCD) doit afficher un texte formé de plusieurs symboles et constitué par des lettres, des chiffres et/ou d'autres signes,
    - la matrice d'affichage (LCD) comporte des colonnes et des lignes, c'est-à-dire est deux dimensions,
    - la matrice d'affichage (LCD) possède beaucoup plus de colonnes que de lignes de manière à permettre l'affichage d'un texte contenant au moins 1 ligne,
    - plusieurs circuits intégrés (IC1...ICn) agencés de façon identique, c'est-à-dire une chaîne de tels circuits intégrés, doivent délivrer des signaux de colonnes (S) pour la commande des colonnes de la matrice d'affichage (LCD), et dans chaque circuit intégré pour la commande respectivement de seulement une partie des colonnes,
    - le circuit intégré comporte un registre à décalage (SR1), dans lequel sont décalés les bits (octet 1, octet 2...), qui correspondent, pour leur part, au texte devant être affiché sur la matrice d'affichage, ou au moins une partie de ce texte,
    - l'entrée (SIN) du registre à décalage (SR1) est raccordée directement, ou tout au plus par des sectionneurs (S2) et/ou des étages d'attaque, à une broche (SIN) du circuit intégré proprement dit, et la sortie (SOUT) du registre à décalage (SR1) est raccordée directement, ou tout au plus par l'intermédiaire de sectionneurs (S2) et/ou d'étage d'attaque, à une broche (SOUT) du circuit intégré proprement dit, de manière à pouvoir transférer le cas échéant les bits (octet 1, octet 2, ...), d'une manière commandée par la cadence (SCK), successivement dans la chaîne,
       -- à savoir dans le registre à décalage (SR1) du premier circuit intégré (IC1) de la chaîne, puis dans le registre à décalage (SR1) du second circuit de la chaîne, et ensuite, dans le cas où ils existent dans les registres à décalage (SR1), d'autres circuits intégrés (ICn), et
    - le circuit intégré peut être commandé en fonctionnement par un processeur de commande,
       qui calcule par exemple des vitesses de déplacement et/ou d'autres valeurs devant être affichées,
    - un générateur de signaux (CG) est branché en aval du registre à décalage (SR1) sur le circuit intégré,
    - le générateur de signaux (CG) comporte une unité particulière de mémoire ROM/CG, et
    - le générateur de signaux (CG) convertit au moins une partie des bits (octet 1, octet 2...) - qui respectivement correspondent essentiellement seulement à un code de courte longueur pour le sens du contenu des signaux considérés - au moyen d'unités de mémoire (ROM/CG), qui est adressée par ces bits (octet 1, octet 2, ...), en des signaux de sortie qui correspondent aux signaux de sortie (S) du circuit intégré,
    - en fonctionnement, seuls ces signaux de sortie du circuit intégré sont envoyés en tant que signaux de colonnes (S) aux entrées de colonnes, associées à ce circuit intégré, de la matrice d'affichage (LCD),
    - le circuit intégré contient une mémoire morte, désignée par ROM (TS),
    -- qui mémorise respectivement les bits (octet 1, octet 2, ...), qui sont nécessaires pour les différents affichages et doivent être chargés dans le/les registres à décalage (SR1), et
    -- qui, lors d'un appel (par l'intermédiaire de S1) d'une adresse concernée ou d'une adresse de démarrage, délivre les bits concernés (octet 1, octet 2, ...) au registre à décalage (SR1) de ce circuit intégré,
    - en fontionnement seule la mémoire ROM (TS) du premier circuit intégré (IC1) de la chaîne envoie au registre à décalage particulier (SR1) de ce premier circuit intégré (IC) - mais pas à la mémoire ROM (TS) du/des autres circuits intégrés suivants (...ICn) de la chaîne - au registre à décalage (SR1) de l'autre circuit intégré immédiatement suivant (...ICn), et
    - en fonctionnement, le/les registres à décalage (SR1) du/des autres circuits intégrés (...ICn) de la chaîne de registres à décalage (SR1) du circuit intégré respectivement précédent de la chaîne est/sont chargés.
  2. Unité de commande suivant la revendication 1, caractérisée par le fait que
       - le premier circuit intégré (IC1) de la chaîne commande également les lignes de la matrice d'affichage (LCD), et ce en commun pour tous les circuits intégrés (IC1...ICn) de la chaîne par le fait qu'il peut également envoyer des signaux de ligne (Z) à la matrice d'affichage (LCD).
  3. Unité de commande suivant l'une des revendications précédentes, caractérisée par le fait que
       - un registre de verrouillage (LT1), qui peut mémoriser temporairement le contenu du registre à décalage (SR1), est branché, en aval, entre le registre à décalage (SR1) et le générateur de signaux (CG).
  4. Unité de commande suivant l'une des revendications précédentes, caractérisée par le fait que
       - dans le circuit intégré, les signaux de colonnes (S) sont envoyés aux broches concernées du circuit intégré par l'intermédiaire d'un registre de sortie (SR2 et LA) branché en aval du générateur de signaux (CG).
  5. Unité de commande suivant la revendication 4, caractérisée par le fait que
       - le registre de sortie (SR2, LA) est formé par le montage série d'un registre à décalage de sortie (SA2) et d'un registre de verrouillage de sortie (LA).
  6. Unité de commande suivant la revendication 4 ou 5, caractérisée par le fait que
       - que le registre de sortie (SR2, LA) et/ou des étages d'attaque de sortie associés délivrent des signaux de colonnes à partir de plus de deux niveaux de tension, c'est-à-dire pas uniquement des bits.
  7. Unité de commande suivant les revendications 2 et 6, caractérisée par le fait que
       - un registre de sortie de lignes et/ou des étages d'attaque associés délivrent des signaux de lignes à partir de deux niveaux de tension, c'est-à-dire pas uniquement des bits.
EP90911990A 1989-08-31 1990-08-01 Unité de commande recevant un signal d'horloge pour une matrice d'affichage sous forme de circuit integré Expired - Lifetime EP0489757B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP89116142 1989-08-31
EP89116142 1989-08-31
PCT/EP1990/001265 WO1991003807A1 (fr) 1989-08-31 1990-08-01 Circuit integre faisant fonction d'element d'amorçage synchronise d'une matrice d'affichage

Publications (2)

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EP0489757A1 EP0489757A1 (fr) 1992-06-17
EP0489757B1 true EP0489757B1 (fr) 1994-10-19

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EP90911990A Expired - Lifetime EP0489757B1 (fr) 1989-08-31 1990-08-01 Unité de commande recevant un signal d'horloge pour une matrice d'affichage sous forme de circuit integré

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EP (1) EP0489757B1 (fr)
AU (1) AU6157090A (fr)
DE (1) DE59007523D1 (fr)
WO (1) WO1991003807A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19625898A1 (de) * 1996-06-27 1998-01-08 Siemens Ag Anzeigesystem und Verfahren zur Versorgung eines Anzeigesystems mit einem Bildsignal

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0533965A1 (fr) * 1991-09-17 1993-03-31 Siemens Aktiengesellschaft Elément semi-conducteur pour contrôler un affichage à matrice, p.e. pour un ordinateur de bord d'un véhicule
FR2732496B1 (fr) * 1995-03-31 1997-06-13 Sgs Thomson Microelectronics Procede d'affichage de symboles sur un ecran

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
E.D.N ELECTRICAL DESIGN NEWS, vol. 30, No. 18, August 1985, (New York, US) pages 83-88; E. Teja: "LCD-driver/controller ICs offer versatility in configuration and function", siehe Seiten 85-86: "Increasing display versatility" see figures 1-3 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19625898A1 (de) * 1996-06-27 1998-01-08 Siemens Ag Anzeigesystem und Verfahren zur Versorgung eines Anzeigesystems mit einem Bildsignal

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AU6157090A (en) 1991-04-08
DE59007523D1 (de) 1994-11-24
WO1991003807A1 (fr) 1991-03-21
EP0489757A1 (fr) 1992-06-17

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