EP0489757A1 - Unité de commande recevant un signal d'horloge pour une matrice d'affichage sous forme de circuit integré. - Google Patents

Unité de commande recevant un signal d'horloge pour une matrice d'affichage sous forme de circuit integré.

Info

Publication number
EP0489757A1
EP0489757A1 EP90911990A EP90911990A EP0489757A1 EP 0489757 A1 EP0489757 A1 EP 0489757A1 EP 90911990 A EP90911990 A EP 90911990A EP 90911990 A EP90911990 A EP 90911990A EP 0489757 A1 EP0489757 A1 EP 0489757A1
Authority
EP
European Patent Office
Prior art keywords
byte
shift register
chain
bits
sri
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP90911990A
Other languages
German (de)
English (en)
Other versions
EP0489757B1 (fr
Inventor
Karl-Heinz Strobel
Max Goetz
Robert Foerster
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0489757A1 publication Critical patent/EP0489757A1/fr
Application granted granted Critical
Publication of EP0489757B1 publication Critical patent/EP0489757B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/04—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions
    • G09G3/16—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions by control of light from an independent source
    • G09G3/18—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions by control of light from an independent source using liquid crystals

Definitions

  • IC as a clock-controllable control component of a display matrix
  • the invention relates to a special integrated module, namely an improvement of the IC defined in the preamble of claim 1, which is known per se.
  • the previously known module has the designation HD44100 and is offered by Hitachi on the market, with this known IC serving primarily as a control module for an LCD display.
  • FIG. 1 serves to explain this prior art.
  • a microprocessor ⁇ P calculates e.g. the current speed and the current as well as the average gasoline consumption of a motor vehicle. These values are to be displayed on the LCD display matrix LCD using a chain of control modules 44100/1 ... 44100 / n.
  • the control modules 44100/1 .... 44100 / n each have, compared to each other, an identical structure, including in each case a shift register, the input and the output of which are brought out at pins of these control modules 44100.
  • These shift registers of the n drive modules 44100/1 ... 44100 / n are each connected in series with one another by connecting the corresponding pins connected to the inputs and outputs of these shift registers. If the many bits of the column signals S, entered in succession by the block 44780, pass through these shift registers, all the shift registers of the control blocks 44100/1 ... 44100 / n are loaded with the column signals S which the control blocks 44100 /1...44100/n via their drivers to the display matrix LCD.
  • the microprocessor ⁇ P controls the display and, for this purpose, delivers short codes to an intermediate special module 44780, which codes only more or less correspond to the content of the characters to be displayed.
  • This special component can be, for example, the integrated component HD44780 manufactured by Hitachi, which contains, inter alia, a character generator which, in turn, generates more specific, detailed control signals from the short codes, which are to be supplied to the rows and columns of the display matrix LCD.
  • the character generator of this well-known HD44780 module includes a ROM. It can store the required column signals of characters or combinations of characters. To display a longer text on the display matrix, the microprocessor ⁇ P has to supply its own 8-bit code more or less per character: However, this 8-bit code supplied by the microprocessor ⁇ P is still very short compared to the length of the Complete bit pattern formed by the column signals of a single character:
  • the characters to be displayed e.g. Containing 40 pixels each in 8 lines and 5 columns, 8 x 5 column signals S are required per character, because 5 column signals S are to be delivered simultaneously per activated line.
  • the ROM of the character generator must store 40 line signals which are sent to the control modules 44100/1 ... in 8 series of 5 bits. , 44100 / n are to be delivered.
  • An 8-bit code of the microprocessor ⁇ P can therefore successively call up 8 series of 5 column signals S each from the ROM of the character generator of the HD44780 module, which the HD44780 (serial) module enters into the input of the shift register of the first IC of the chain 44100 / 1 .. ..44100 / n (- that the HD44780 module can also supply up to 40 columns Sz of the display matrix itself from its character generator is indicated in FIG. 1, but will not be described further here ⁇ respects).
  • 40 characters each consisting of 8 rows and 5 columns, is then not less than 8 series of 40 x 5 bits, i.e. considerably more bits (namely 1600 bits), than the total number of bits in those approx. 40 8-bit codes that are used to control these show from the microprocessor ⁇ P to block 44780 that must be delivered (200 bits).
  • That block 44780 thus provides 8 bits for the line signals Z for a one-time (I) display of this text, which it passes directly to the lines of the display matrix LCD together for all the characters to be displayed.
  • it also supplies the many, namely 1600 special, column signals S, also generated by its character generator, serially to the input of the first of the n different control modules 44100/1. ..44100 / n, which in turn deliver these column signals S to the columns of the display matrix LCD by means of drivers, and thus with corresponding levels.
  • the 8 line signals Z and t each 1600 column signals S are known to be cyclically and constantly repeated repeatedly, instead of once, on the display matrix LCD in order to obtain an optically apparently stationary display .
  • the block 44780 for this display very often has to deliver its 8 character signals Z per second and, above all, its 1600 column signals S the same number of times.
  • the maximum length of the chain of control blocks 44100/1. , , .44100 / n has an upper limit because the pulse repetition frequency with which the column signals S must be continuously input into the relevant input of the first control module 44100/1 for a display cannot be increased as desired.
  • the length of the text that can be displayed with a sufficiently quiet typeface is therefore very limited in this prior art, over which the microprocessor ⁇ P and the block 44780 are also highly loaded because both have to emit and process many bits per second in order to produce the calm typeface to maintain.
  • each of these known control modules 44100/1. ..44100 / is it a. IC, which serves as a clock-controllable control component of a display matrix LCD, this display matrix LCD also having a long, multi-digit text from Buc should be able to display letters, numbers and / or other characters.
  • the display matrix LCD contains columns and rows and therefore at least two dimensions, and indeed contains many more columns than rows in order to be able to display the long, often only one-line text.
  • the identically constructed IC's 44100 each form a chain and supply column signals S for controlling the columns of the display matrix LCD, specifically each IC for controlling only a part of those columns.
  • Each IC 44100 contains a shift register, into which bits are shifted, which in turn correspond to the text to be displayed on the display matrix, or at least a section of this text, even in this prior art.
  • the input and the output of the shift register is connected directly - or at most via isolating switches and / or driver stages, which do not change the bit pattern - to pins of the IC, in order to be able to push the bits through the chain one after the other, controlled by the clock, - namely first by the shift register of the first IC of the chain, then by the shift register of the second IC of the chain, and then, if present, by the shift register of the other ICs.
  • the IC is in operation by a control processor ⁇ P, which e.g. Driving speeds and / or other values to be displayed are calculated, controllable, whereby, this control processor ⁇ P - in this prior art only indirectly, namely e.g. about e.g. via the interposed block HD44780 - which supplies bits with which the shift registers of the chain are loaded.
  • a control processor ⁇ P which e.g. Driving speeds and / or other values to be displayed are calculated, controllable, whereby, this control processor ⁇ P - in this prior art only indirectly, namely e.g. about e.g. via the interposed block HD44780 - which supplies bits with which the shift registers of the chain are loaded.
  • control modules for display matrices including those which are used for controlling the columns when the texts to be displayed are often very long and the number of columns to be controlled is therefore considerably larger than the number of column signal outputs of the the display modules.
  • module ⁇ PD7228 which is offered by the company NEC on the market.
  • This IC has a character generator which converts short codes, which are supplied by a microprocessor, into the concrete column signals of the relevant columns in the IC.
  • each individual control module must be supplied with the short codes pertaining to this IC via its own lines from the microprocessor, because these ICs do not have a shift register that is switched and operated as with the HD4100 control module.
  • a forwarding of these codes, or a forwarding of the final column signals S from IC to IC, is therefore not provided for the control module ⁇ PD7228, although it serves to control only a part of the columns. If a very long text is to be displayed using this IC ⁇ PD7228, a plurality of such ICs are used, but each of them controls only a part of the columns of the display matrix. The microprocessor therefore has to supply the various ICs with the relevant codes one after the other via their own control lines.
  • the display matrix is subsequently extended, e.g. by the number of column signal outputs from two ICs, then only in the first example, namely the drive module HD44100, can the chain of the above-mentioned green be extended up to 80 characters with 5 columns without many problems.
  • the ⁇ PD7228 module however, additional measures must be taken so that each of these control modules is supplied with all the necessary data via its own lines.
  • the intermediate module e.g. HD44780 has to deliver its output signals, namely the column signals S, only to the input of the shift register of the first IC of the chain.
  • the invention is also based on an IC control module which, like the HD44100 s module, can be connected to form a chain that only the first IC of this chain has to be supplied directly with the bits corresponding to the text.
  • the invention also fulfills the following additional task:
  • control effort and the time required to supply the shift register of the first IC in the chain with the data bits corresponding to the text are to be further reduced by the relevant first IC from the outside - not even the enormous number of data bits which correspond to the concrete column signals - or which then even represent cyclically repeated column signals -,
  • a microprocessor should therefore, even with an LCD display, since column signals must be supplied cyclically quickly, at the input of the first control module (IC1) its bytes or data bits - apart from clock signals - only once per text to be displayed have to deliver, instead of being repeated cyclically, often every second.
  • the HD44780 module which has its own character generator for generating the fun signals to be fed into the ICs, should be unnecessary.
  • any number of ICs according to the invention can be arranged in a chain of practically any length, in that their shift registers in question can easily be connected in series so that the relevant shift registers of the first IC entered data, at least as a rule without changing their bit pattern, are pushed through the shift registers of all ICs in the chain.
  • This object is achieved by the measures specified in claim 1.
  • the enormous number of bits corresponding to the column signals S are no longer input into the input of the first shift register of the chain of ICs, but rather only the bits of short codes which approximately correspond in content to the meaning of the characters to be displayed . Only in the relevant ICs are the combinations of column signals associated with the character generated, in each case with the aid of the character generator attached there.
  • Microprocessor is relieved even further, even if it is to display a very long standard text.
  • the codes which are supplied by the microprocessor to the relevant first IC of the chain can often only be formed by a short address, as will be explained in connection with the additional measure mentioned in claim 2 .
  • the length of the chain can be extended practically as desired, ie the number of IC's connected in series can be increased practically as desired.
  • the invention makes it possible to display very long texts with ease, even if only a few bits as short codes are supplied by the microprocessor to the first of these ICs, namely the input of its shift register.
  • this microprocessor can generally supply its data bits directly to the relevant data input of the first IC of the chain without the need for an additional module which contains its own character generator, - cf. d e n block 44780 in FIG. 1.
  • the shift register of the last IC of this chain can also be loaded with its codes comparatively quickly, so that the invention also takes the time required to prepare the display of a new one long text is particularly short.
  • the text displayed by the ICs according to the invention is i. general - to reduce the number of different characters that are stored in the character generator preprogrammed - be only one line. If the text to be displayed is multicellular, it often works for the same reason,
  • the IC according to the invention only shows all of its advantages when several such ICs are connected to form a chain. However, the IC according to the invention can also be used if only a single IC according to the invention is used to display a text which is then always relatively short.
  • FIG. 2 to 7 schematically illustrated exemplary embodiments with several ICs per display matrix are further explained.
  • FIG. 2 to 7 schematically illustrated exemplary embodiments with several ICs per display matrix are further explained.
  • FIG. 2 shows an example of an LCD display matrix which is controlled by a total of n inventive ICs, it being assumed that the first IC IC1 supplies not only column signals S but also line signals Z to the display matrix LCD;
  • FIG. 3 shows an example of circuits which are mounted on an IC according to the invention
  • This FIG serves primarily to illustrate the current and signal supply of a chain of two IC examples according to the invention, namely of a master corresponding to the first IC and a slave corresponding to the second IC, the microprocessor providing the signals not being shown ; - If additional ICs are inserted between the master and the slave, these additional ICs will basically become like the slave provided ;
  • FIG. 1 and 2 show that in the invention the IC's ICl ... ICn also form a chain in that their shift registers are connected in series, so that the short codes supplied by the microprocessor ⁇ P each pass to the signal input SIN of the shift register of the first IC IC1, and also via the signal output SOUT of this shift register to the signal inputs SIN of the following ICs ... ICn.
  • the corresponding signal inputs of the shift registers of the control components 44100/1 ... 44100 / n were each not supplied with codes, but with much more concrete column signals as very extensive bit patterns with a high expenditure of time.
  • the ICs ICl ... ICn according to the invention therefore each contain their own character generators, which in turn convert the codes temporarily stored in the shift registers into the many column signals S in the ICs.
  • the microprocessor ⁇ P can directly use the relevant codes - e.g. each correspond to a single character of the text to be displayed, load into the shift register of the first IC of the chain.
  • FIG. 3 and 4 show a further development in which the microprocessor ⁇ P can also be operated, if necessary, in such a way that - apart from clock pulses SCK possibly also supplied by the microprocessor ⁇ P - only extremely few data bits are left on the ROM of a text memory TS additionally installed in the IC, which in turn only loads the shift registers of the chain with - still relatively short - codes, each of which eg correspond to individual characters or short combinations of characters in the text.
  • FIG. 3 shows an example of the structure of the circuits in an IC according to the invention.
  • the short codes for example supplied by the microprocessor ⁇ P, can be loaded directly into the input of the shift register SRI via the data input SIN and directly via the switch S2 (in its position a), which in turn is short via this data output SOUT and is output by this microprocessor ⁇ P delivers the supplied codes to the data input SIN of the next IC in the chain.
  • FIG. 3 schematically shows that the codes represented by Byte 1, Byte 2, ..., successively through the memory cells of the shift r egisters SRI, wherein for example the byte JE eight consecutive memory cells of the shift register SRI is required. In this case - if one does not use a text memory TS - all the bits that are loaded into the shift register SRI are thus immediately supplied by the microprocessor ⁇ P.
  • the position of the switches S1 and S2 is determined by the operating mode control BAS.
  • the operating mode control BAS is in turn symbolically controlled from the outside together with the sequence control AB by a signal SS;
  • FIG. 1 shows a concrete solution for their control. 4 - that is
  • the operating state after the loading of all m + 1 shift registers with 14 bytes each is indicated schematically in FIG. 7, where the first IC is referred to as "master” and the m subsequent ICs as "slaves".
  • a particular advantage of the invention results from the fact that the microprocessor ⁇ P - apart from possibly clock pulses SCK also to be supplied by this microprocessor ⁇ P, cf. FIG. 3 and 4a - only have to feed its codes once into the relevant input of the first IC IC1 or master of the chain, even if the character generators CG of all m + 1 ICs cyclically repeats the column signals S to a display matrix often every second have to deliver, if the latter, for example is an LCD display!
  • the character generator CG is e.g. a ROM which is addressed by the bytes created. It then successively generates the output signals corresponding to the many concrete column signals S, which in the present example are fed into the further, shift register SR2 connected downstream.
  • the character generator CG thus serves to convert the codes or input data byte 1, byte 2 ... loaded into the shift register SRI into the column signals S required for the display matrix LCD, in order to generate the desired displays at the corresponding character positions and line positions .
  • the displays and thus the character generator output signals can also be used during the operation of the IC. '' Changing the codes byte 1, byte 2 ... are changed from time to time, whereby the displayed texts are changed from time to time.
  • the control effort of the microprocessor ⁇ P, cf. FIG. 2, is particularly small in the invention - even if the text memory TS is not yet used - because the microprocessor ⁇ P only feeds the first IC IC1 of the chain with data, the bits of this data not representing the specific column signals S. , but only relatively short codes, which in turn only show more or less the meaning of the content of individual corresponding characters or of entire character groups or character combinations to be displayed.
  • the character generators * CG of the individual ICs each generate the column signals S to be output from the relevant IC from the codes which are loaded in the shift registers SRI.
  • the shift registers SRI are not immediately controlled by the character generators CG of the ICs, but preferably only after (1) the charging of all shift registers SRI of the ICs has been completed.
  • a special external control signal supplied to the IC can be used, for example by means of the control signal shown in FIG. 3 indicated byte 2, before the display of a (new) text, a special RAM in the character generator CG is additionally addressed in order to overwrite this RAM, for example with byte 1, which is shown in FIG. 4, which will be explained in more detail later, will be seen even more clearly.
  • This development of the invention allows the special data then stored in the RAM (here, for example, from byte 1) to be used to generate very special column signals S, which are not preprogrammed in the ROM of the character generator CG, but rather are used, for example, for displaying particular rarely used characters that cannot be generated by means of the ROM of the character generator CG are required - for example for rarely used Greek or Cyrillic characters.
  • the sequence control AB can also take over the clocking for this.
  • the first IC IC1 of the chain can possibly also control the few line signals Z required for the display matrix, specifically for all ICs IC1 ... ICn of the chain, possibly also by means of its sequence control AB, whereby a separate module for control the rows of the display matrix LCD can be saved.
  • FIG. 3 is additionally followed by an output register SR2 and LA, in particular for a parallel series conversion of the bits, between the character generator CG and the IC pins, which emit the column signals S to the display matrix LCD .
  • SR2 is also a shift register in terms of structure and operation. As soon as the shift register SR2 is loaded with the corresponding column signal data via the character generator CG, this data is temporarily stored in the further, downstream block "latch and driver output stages" LA and is sent to the column outputs of the IC i. generally repeated cyclically quickly - output as column signals S. As is known, an LCD display matrix sometimes needs non-binary column signals S, which therefore have further voltage levels, the output register, cf. LA, and / or assigned output driver stages must then emit column signals S which contain more than two voltage levels.
  • the output register can e.g. are formed by a series arrangement of an output shift register SR2 and an output latch register LA. This results in a particularly reliable, solid structure of the output register, and in addition the corresponding output latch register also considerably reduces the flickering of the text when switching from one line to the next line.
  • FIG. 3 shows an example of the IC according to the invention additionally contains the text memory TS, already mentioned several times, with its own ROM, each of which is for the different Displays require the bits byte 1, byte 2 .. to be stored in the shift registers SRI and which, when a corresponding start address is called up, transfers the relevant bits byte 1, byte 2 ... to the shift register SRI of this IC.
  • the short code supplied by the microprocessor ⁇ P can comprise, for example, 8-bit bytes, whereby the first byte can correspond to one character, but also to an almost arbitrary long character combination of perhaps even 100 characters, for which purpose ROM of the text memory TS only has to be dimensioned sufficiently large - cf. the size of the ROM in the text memory TS in FIG. 4a and 6.
  • the master module IC1 according to the invention - unlike in the prior art, cf. the block 44100/1 in FIG. 1 - only lx per text to be displayed instead of being cyclically supplied with input data at the SIN input repeatedly every second, even if an LCD display is used as the LCD display matrix.
  • the short, for example 8-bit long code then corresponds, for example, to a single character to be displayed or, in an extreme case, even very long, standardized text.
  • a second code supplied by the microprocessor ⁇ P for example a second byte, can then also correspond to an additional numerical value to be displayed.
  • a text memory ROM switched and operated in this way allows the microprocessor ⁇ P to be further relieved.
  • the microprocessor ⁇ P - again apart from clock signals SCK - only delivers very short codes to the ROM of the text memory TS of the master, that is to say the first IC of the chain, but - at least in general - no longer directly to that Shift register SRI of the master IC1.
  • the codes supplied by the microprocessor ⁇ P to the ROM of the text memory TS of the master IC1 can then, for. B. also mark a very long standard text, if necessary. also contain an associated numerical value code, cf. e.g. For example, the text "YOU HAVE EXCEEDED THE MAXIMUM SPEED BY KM / H!.
  • the text memory TS is e.g. operated as follows:
  • the switches S1 As soon as the switch S1 is closed, the signals of the data input SIN arrive in a special shift register SRZ upstream of the text memory TS and set a counter there to a start address. This start address is used to address the ROM of the text memory TS.
  • the switch S2 can then be e.g. can be switched to position b using the BAS operating mode control.
  • the ROM of the text memory delivers a next byte to the shift register SR2, then the other bytes in a corresponding manner.
  • These bytes supplied in the shift register SRI can finally be pushed completely through the shift register SRI and, in the next IC of the chain via its switch S2 in position a, load the shift register SRI there directly.
  • these bytes byte 1, byte 2 correspond more or less to the meaning of individual characters to be displayed or short character combinations, which in turn are only converted into the more specific column signals s by means of the character generators of the individual ICs.
  • FIG. 3 schematically shown example can e.g. according to the much more detailed circuit shown in FIG. 4 • 'shows, builds and operates:
  • the example of an IC according to the invention shown in FIG. 4 has 70 segment lines SEGO .... SEG69 for 14x5 column signals S which can be emitted simultaneously.
  • it has 8 backplane lines BPO BP7 for 8 line signals Z, the multiplexing rate being 1: 8 and the line signals Z 4 having voltage levels VO, VI, V3, VLCD in accordance with the requirements of the special LCD display used here , as well as the column signals 3 voltage levels VO, V2, VLCD.
  • FIGS. 4 and 5 has a latch enable input LE.
  • the values of the shift register contained in SRZ are transferred to the address counter in block SRZ, or the values of the shift register SRI are transferred to the latch register LT1.
  • Edge control e.g. Takeover with a rising edge should be provided.
  • SIN is the data input, via which serial, synchronized with the clock pulses SCK, data bits are taken over by the microprocessor, the most significant bit preferably being transmitted first in the example shown.
  • SOUT is the output of the shift register SRI of the relevant IC, whereby the input SIN of a next IC of the chain can be connected to this output SOUT, cf. also FIGS. 5 and 7.
  • SYNCOUT is an output that is used for synchronization.
  • the output is SYNCOUT with the connector SYNCIN connected.
  • the SYCIN connector is connected to the SYNCOUT output of the master.
  • SYNCIN is therefore an input that is used for synchronization with the master and is set to high in the active state.
  • WRAM is an input which is used to control the transfer of data bits from the shift register SRI into the RAM of the character generator CG. In the active state, the connection WRAM is set to high, this connection being level-triggerable.
  • CLK is a further clock input which can serve to control all internal processes, in the example shown particularly as a "pixel clock".
  • RESETN is a reset connection that is low in the active state and is used to reset internal registers.
  • VDD is used for + 5V logic power supply.
  • VLCD is used to supply positive voltages.
  • V3, V2, VI are positive auxiliary voltages which are generated from VLCD by means of a voltage divider R shown in FIG.
  • VO / GND is the ground connection.
  • connections mentioned are not only shown in FIG. 4, but also in FIG. 5 in order to show - existing and nonexistent - differences in the power supply and signal supply when comparing the master on the one hand and the slaves on the other hand when using ICs according to the invention 4 to better illustrate.
  • the sequence control AB consists here, for example, of several divider stages.
  • the first divider stage T / 2 halves the cycle and generates a 4-phase cycle necessary for internal processes.
  • the second division stage T / 5 reduces the clock to 1/5 and serves to select a column in the 5x8 character matrix of the character generator CG.
  • the third divider stage T / 14 reduces the clock further to 1/14 and serves to select a character position within that section of the display matrix LCD whose columns are controlled by the relevant IC.
  • the fourth sub-stage T / 8 reduces the cycle to 1/8 and serves to select 1 of the 8 lines here.
  • the "Sync. Gen.” level serves for the synchronization of several ICs according to the invention with one another.
  • the inputs C1 and C2 can thus be used - specifically by means of the operating mode control BAS and by means of logic elements or multiplexers which the in FIG. 3 shown switches S1 and S2 correspond - 4 operating modes can be selected, cf. the functions of the inputs Cl and C2 already mentioned above:
  • the IC data input also includes the SIN input for data bits and the SCK input for a clock; these inputs represent a synchronous serial interface.
  • Control signals are thus applied to the internal circuit blocks from the outside via the inputs C1 and C2.
  • the special shift register "16 bit" in the circuit block SRZ which corresponds to the address shift register ADRL / ADRH in FIG. 6, records the data of the data input SIN in operating mode 2) until a LE pulse follows.
  • the downstream counter ZR can be preset with the word of the shift register "16 bit”. The counter reading is used to address the ROM of the text memory TS.
  • the text memory TS contains a ROM with an 8-bit width here.
  • a multiplexer MUX selects a bit from the 8 bits read from the ROM in each case, which in operating mode 1) is applied to the input of the shift register SRI.
  • a counter Z / 8 in the text memory TS addresses the multiplexer MUX and selects all bits in succession that are located under the relevant ROM address.
  • the counter ZR receives a pulse in block SRZ and addresses the next address in the ROM in order to be able to read the next 8 bits from the ROM.
  • the shift register SRI is 112 bits long and is divided into 14 groups of 8 bits each. This allows 14 bytes, e.g. Control 14 characters via the 70 column lines S or SEGO .... ... SEG69 of the LCD display matrix. The last bit of the shift register SRI is also fed to the SOUT output.
  • the latch register LT1 is used to store the entire final content of the shift register SRI.
  • the multiplexer MUX1 is used here to select an 8-bit group (corresponds to 1 byte) from the 14 bytes stored here in the latch register LT1.
  • the 8-bit output value output by the multiplexer MUX1, that is to say that selected byte, then serves as the address for the memory in the character generator CG.
  • the character generator CG contains a memory which can be addressed by the multiplexer MUX1 and by the sequence control AB and consists here of two parts, cf. ROM and RAM. Part of this food So chers is a ROM and part is RAM. An address decoder ADR.DEC takes over the selection between the RAM and the ROM.
  • each memory entry is 5 bits wide; - This corresponds to the 5 columns, ie the number of columns selected here for each character, which is to be displayed in a 5-column x 8-line matrix on the display matrix LCD.
  • the column signals S for rarely required special characters such as Greek or Cyrillic characters can be entered into the RAM of the character generator CG before the start of the Text ads are written - e.g. to the special operating mode for loading this RAM described above.
  • a pulse can be applied to the WRAM connection to change the address of the RAM, e.g. can be addressed with byte 2 of the shift register SRI, with the value of byte 1 of the shift register SRI.
  • the display matrix LCD is not supplied with column signals S not only by a single IC according to the invention, that is to say alone by the master, so to speak, but if a chain of ICs according to the invention is attached, then the RAM in the character generator CG of each IC of the chain should be Both in the master and in the slave, at least in the case with the desired additional data, if the special character in question is not to be displayed only at those points in the text to be displayed which are identified by a single IC of the chain with the relevant column signals S be supplied.
  • the 5 bits converted in series in this way therefore serve as an input signal for the further shift register SR2.
  • the coordination of the processes is carried out here by the write / read logic R / W logic of the character generator CG.
  • the further shift register SR2 is 70 bits long here, corresponding to those 14 characters with 5 columns. In this shift register SR2, each bit corresponds to a pixel to one of the row outputs Z or BPO. BP7 controlled lines of the display matrix LCD.
  • the latch register LATCH in block LA serves as a memory for the content of the shift register SR2, while the further shift register SR2 is already loaded with the column signal data for the next line of the display.
  • the segment driver SEG in block LA is used to generate the necessary digits of the output voltage profiles, which in some cases require more than two voltage levels here, as they are used to control LCD display matrices, in particular with a multiplex rate 1: 8 in themselves known manner are needed.
  • the line control ZA here generates from the counter readings of the last divider T / 8 of the sequence control AB the necessary, also in some cases more than 2 levels, output voltage curves for the lines of the display matrix LCD, as is known in the art for controlling an LCD display ⁇ trix with a multiplex rate of 1: 8 are required.
  • the IC according to the invention can be operated like the master in FIG. 5. If, on the other hand, one or more slaves are attached, the ROM of the
  • Text memory TS all these slaves are each switched off by a constant high level at C1, cf. FIG 5. All C2 connections se from the master and the slaves are connected to each other and controlled together by the microprocessor. The SYNCIN inputs of the slaves are each directly connected to the SYNCOUT output of the master.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

Circuit intégré faisant fonction d'élement d'amorçage (IC) synchronisé (CLK, SCK) d'une matrice d'affichage (LCD) servant à l'affichage d'un texte constitué de plusieurs lettres, chiffres et/ou autres signes, dans lequel la matrice d'affichage (LCD) présente un bien plus grand nombre de colonnes que de lignes, de manière à pouvoir afficher au minimum un texte d'une ligne, plusieurs circuits intégrés identiques (IC1...ICn), formant une chaîne, délivrent des signaux de colonne (S) commandant les colonnes de la matrice d'affichage (LCD), chaque circuit intégré commandant une partie des colonnes seulement, le circuit intégré comporte un registre à décalage (SR1) dans lequel sont déplacés les bits (octet 1, octet 2...) qui correspondent au texte à afficher sur la matrice d'affichage ou au moins à une fraction de ce texte, l'entrée (SIN) et la sortie (SOUT) du registre à décalage (SR1) sont reliées directement, ou au plus par l'intermédiaire de sectionneurs (S2) et/ou d'étages excitateurs, à des broches (SIN, SOUT) du circuit intégré pour pouvoir si nécessaire déplacer successivement les bits (octet 1, octet 2) commandés par l'horloge (SCK) à travers les registres à décalage (SR1) de la chaîne (IC1...ICn), le circuit intégré en fonctionnement est commandé par un processeur de commande, sur le circuit intégré un générateur de caractères (CG) possédant sa propre mémoire (ROM) est connecté au registre à décalage (SR1), le générateur de caractères (CG) en fonctionnement transforme au moins une partie des bits (octet 1, octet 2...), qui correspondent chacun pour l'essentiel uniquement à un code court pour la signification intrinsèque des signes concernés, au moyen de la mémoire (ROM/CG) adressée par ces bits (octet 1, octet 2...), en signaux de sortie correspondant aux signaux de sortie (S) du circuit intégré, et en fonctionnement seulement, ces signaux de sortie du circuit intégré sont fournis sous forme de signaux de colonne (S) aux entrées de colonne de la matrice d'affichage (LCD) assignées à ce circuit intégré.
EP90911990A 1989-08-31 1990-08-01 Unité de commande recevant un signal d'horloge pour une matrice d'affichage sous forme de circuit integré Expired - Lifetime EP0489757B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP89116142 1989-08-31
EP89116142 1989-08-31
PCT/EP1990/001265 WO1991003807A1 (fr) 1989-08-31 1990-08-01 Circuit integre faisant fonction d'element d'amorçage synchronise d'une matrice d'affichage

Publications (2)

Publication Number Publication Date
EP0489757A1 true EP0489757A1 (fr) 1992-06-17
EP0489757B1 EP0489757B1 (fr) 1994-10-19

Family

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EP90911990A Expired - Lifetime EP0489757B1 (fr) 1989-08-31 1990-08-01 Unité de commande recevant un signal d'horloge pour une matrice d'affichage sous forme de circuit integré

Country Status (4)

Country Link
EP (1) EP0489757B1 (fr)
AU (1) AU6157090A (fr)
DE (1) DE59007523D1 (fr)
WO (1) WO1991003807A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0533965A1 (fr) * 1991-09-17 1993-03-31 Siemens Aktiengesellschaft Elément semi-conducteur pour contrôler un affichage à matrice, p.e. pour un ordinateur de bord d'un véhicule
FR2732496B1 (fr) * 1995-03-31 1997-06-13 Sgs Thomson Microelectronics Procede d'affichage de symboles sur un ecran
DE19625898A1 (de) * 1996-06-27 1998-01-08 Siemens Ag Anzeigesystem und Verfahren zur Versorgung eines Anzeigesystems mit einem Bildsignal

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9103807A1 *

Also Published As

Publication number Publication date
AU6157090A (en) 1991-04-08
DE59007523D1 (de) 1994-11-24
WO1991003807A1 (fr) 1991-03-21
EP0489757B1 (fr) 1994-10-19

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