EP0489757B1 - Clocked drive unit for a display matrix in the form of an IC - Google Patents

Abstract

Described is an integrated circuit (IC) serving as a timed drive (CLK, SCK) of a display matrix (LCD) intended for the display of multi-character text comprising letters, numbers and/or other symbols and including the following features: the display matrix (LCD) has very many more columns than lines in order to display at least one line of text; several identical integrated circuits (IC1...ICn), i.e. a series of such circuits, provide column signals (S) for the control of the columns of the display matrix (LCD), each circuit controlling only some of the columns; the integrated circuit includes a shift register (SR1) into which those bits (Byte 1, Byte 2....) are shifted which correspond to the text displayed on the display matrix, or at least a section of this text; the input (SIN) and output (SOUT) of the shift register (SR1) are connected directly, or at the most via isolating switches (S2) and/or driver units, with pins (SIN, SOUT) of the integrated circuit in order to make it possible, when necessary, to shift the bits (Byte 1, Byte 2....), under fixed-cycle control (SCK), successively through the shift registers (SR1) of the series of integrated circuits (IC1...ICn); the integrated circuit is controlled by a control processor when the former is in operation; in the integrated circuit, a character generated (CG) with its own memory unit (ROM) is connected in series with the shift register (SR1); the character generator (CG), when in operation, converts at least some of the bits, each of which basically corresponds only to a short code representing the meaning of the relevant character, by means of the memory unit (ROM/CG) which is addressed by these bits (Byte 1, Byte 2....), into output signals which correspond to the output signals (S) of the integrated circuit and only these output signals are supplied as column signals (S) to the display matrix column inputs associated with said integrated circuit.

Description

The invention relates to an improvement of a previously known integrated module with the designation HD44100, which is offered by Hitachi on the market, this known IC primarily serving as a control module of an LCD display. The essential features of the known module are defined in the preamble of claim 1.

FIG. 1 serves to explain this prior art. A microprocessor µP calculates e.g. the current speed and the current as well as the average gasoline consumption of a motor vehicle. These values are to be displayed on the LCD display matrix LCD using a chain of control modules 44100/1 ... 44100 / n.

The control components 44100/1 .... 44100 / n each have, compared to one another, an identical structure, including a shift register, the input and the output of which are brought out at pins of these control components 44100. These shift registers of the n control modules 44100/1 ... 44100 / n are each connected in series with one another by connecting the corresponding pins connected to the inputs and outputs of these shift registers. When the many bits of the column signals S, entered in succession by the block 44780, pass through these shift registers, all the shift registers of the control blocks 44100/1 ... 44100 / n are loaded with the column signals S which the control blocks 44100/1 ... pass on 44100 / n via their drivers to the LCD display matrix.

The microprocessor µP controls the display and delivers short codes to an intermediate special module 44780, which only more or less correspond to the content of the characters to be displayed. This special module can e.g. the integrated chip HD44780 manufactured by Hitachi, which among other things contains a character generator, which in turn generates more specific, detailed control signals from the short codes, which are to be supplied to the rows and columns of the display matrix LCD.

The character generator of this well-known HD44780 module contains a ROM. It can store the required column signals of characters or combinations of characters. To display a longer text on the display matrix, the microprocessor µP must supply its own 8-bit code more or less per character: However, this 8-bit code supplied by the microprocessor µP is still very short compared to the length of the Complete bit pattern formed by the column signals of a single character:

If the characters to be displayed e.g. Containing 40 pixels each in 8 rows and 5 columns, 8 x 5 column signals S are required per character, because 5 column signals S are to be delivered simultaneously for each activated row. For each 8x5 character, the ROM of the character generator must store 40 line signals, which are to be delivered in 8 series of 5 bits each to the control modules 44100/1 ... ..44100 / n.

An 8-bit code of the microprocessor μP can therefore call up 8 series of 5 column signals S in succession from the ROM of the character generator of the HD44780 module, which the HD44780 (serial) module enters into the input of the shift register of the first IC of the 44100/1 chain. ..44100 / n feeds (- that the block HD44780 can also supply up to 40 columns Sz of the display matrix itself from its character generator is indicated in FIG. 1, but is no longer considered here). The total number of blocks 44780 to be generated Column signals S in order to use the 44100/1. ..44100 / n once (!) To display a longer text consisting of, for example, 40 characters, each consisting of 8 rows and 5 columns, is then no less than 8 series of 40 x 5 bits, i.e. considerably more bits (namely 1600 bits) than the total number of bits in those approx. 40 8-bit codes, which must be supplied by the microprocessor µP to block 44780 to control this display (200 bits).

That block 44780 thus provides 8 bits for the line signals Z for a one-time (!) Display of this text, which it forwards directly to the lines of the display matrix LCD together for all characters to be displayed. In addition, it supplies the many, namely 1600 special column signals S, also generated by its character generator, serially to the input of the first of the n different control modules 44100/1 ... 44100 / n, which in turn generate these column signals S by means of drivers, and thus with corresponding levels , forward to the columns of the LCD display matrix.

If the display matrix LCD is an LCD display, however, it is known that the 8 line signals Z and those 1600 column signals S are cyclically and constantly repeated rapidly - instead of once - to be supplied to the display matrix LCD in order to obtain an optically apparently stationary display. Accordingly, in this prior art, the block 44780 must very often deliver its 8 character signals Z per second for this display and, above all, the same number of times each of its 1600 column signals S. The maximum length of the chain of the control modules 44100/1 .... 44100 / n is limited by the top because the pulse repetition frequency with which the column signals S must be continuously input into the relevant input of the first control module 44100/1 for a display, cannot be increased arbitrarily. The length of the text which can be displayed with a sufficiently calm typeface is therefore very limited in this prior art. In addition, the microprocessor µP and the device 44780 are also heavily loaded because they both emit many bits per second and have to process in order to maintain the calm typeface.

Each of these known control modules 44100/1 ... 44100 / n is therefore an IC that serves as a clock-controllable control module of a display matrix LCD, this display matrix LCD also having a long, multi-digit text made up of letters, numbers and / or other characters should be able to display. The display matrix LCD contains columns and rows and thus at least two dimensions, and indeed contains many more columns than rows in order to be able to display the long, often only one-line text. The identically constructed IC's 44100 each form a chain and supply column signals S for controlling the columns of the display matrix LCD, specifically each IC for controlling only a part of those columns. Each IC 44100 contains a shift register, into which bits are shifted, which in turn correspond to the text to be displayed on the display matrix, or at least a section of this text, even in this prior art. The input and the output of the shift register is connected directly - or at most via isolating switches and / or driver stages, which do not change the bit pattern - to pins of the IC, in order to be able to push the bits through the chain one after the other, controlled by the clock, - namely first by the shift register of the first IC of the chain, then by the shift register of the second IC of the chain, and then, if present, by the shift register of the other ICs.

The IC is in operation by a control processor µP, which e.g. Driving speeds and / or other values to be displayed are calculated, controllable, whereby, this control processor µP - in this prior art only indirectly, namely e.g. about e.g. via the interposed block HD44780 - which supplies bits with which the shift registers of the chain are loaded.

There are other known control modules for display matrices, - Also those which are used to control the columns if the texts to be displayed are often very long and the number of columns to be controlled is therefore considerably larger than the number of column signal outputs of the relevant display modules. For example, there is the module µPD7228, which is offered by NEC on the market. This IC has a character generator which converts short codes, which are supplied by a microprocessor, into the concrete column signals of the relevant columns in the IC. With this IC, however, each individual control module is to be supplied with the short codes pertaining to this IC via its own lines from the microprocessor, because these ICs have no shift register, which is switched and operated like the control module HD44100. A forwarding of these codes, or a forwarding of the final column signals S from IC to IC, is therefore not provided for the control module µPD7228, although it serves to control only a part of the columns. If a very long text is to be displayed using this IC µPD7228, a plurality of such ICs are used, but each of them controls only a part of the columns of the display matrix. The microprocessor therefore has to supply the various ICs with the relevant codes one after the other via their own control lines.

Also in the publication EDN (Electrical Design News) 30 (August 8, 1985) No. 18, Newton, Massachusetts / USA, pages 83 to 88, control modules SED1503 are described, which have no shift register, which would allow chain connection of such control modules by directly connecting the shift registers of these control modules in series. Several such control modules SED1503 are in a row and together deliver control signals to an LCD display. All of these SED1503 control modules are each directly supplied with the corresponding codes by a microprocessor µC. In the absence of correspondingly switched internal shift registers of these control modules, it is not sufficient here for the microprocessor µC only supplies the first control module SED1503 of this series of control modules with input signals because the other control modules in this series cannot be supplied directly from the output of a previous control module in this series. With these SED1503 control modules, chain switching is not possible. Then, however, it is also not possible to extend a chain of such control modules with the low wiring effort between the microprocessor and the control modules aimed at in the invention.

If the display matrix is subsequently extended - by extending the IC chain using additional control modules, e.g. by the number of column signal outputs from two ICs, then only in the first example, namely the control module HD44100, can the chain be extended without many problems, for the reasons mentioned, namely up to 80 characters with 5 columns. With the µPD7228 block and also with the SED1503 block, additional wiring measures must be taken so that each of these control blocks is supplied with all the necessary data via its own lines.

In the case of control modules of the HD44100 type which can be connected in series, the effort is often comparatively low, owing to the omission of corresponding additional data lines or control lines and the associated commands, especially if a very long display matrix is to be used. The intermediate module, e.g. HD44780 has to deliver its output signals, namely the column signals S, only to the input of the shift register of the first IC of the chain.

As already explained, the invention is also based on an IC control module which, like module HD44100, can be connected to form a chain such that only the first IC of this chain has to be supplied directly with the bits corresponding to the text.

• Der Ansteueraufwand und der Zeitaufwand, um das betreffende Schieberegister des ersten IC der Kette mit den dem Text entsprechenden Daten-Bits zu beliefern, soll weiter verringert werden, indem dem betreffenden ersten IC von außen
  • -- nicht einmal mehr die enorm vielen Daten-Bits, die den konkreten Spaltensignalen entsprechen, - oder die dann sogar zyklisch laufend wiederholte Spaltensignale darstellen - ,
  • -- sondern statt dessen nur noch jene relativ kurzen Codes als Daten-Bits, die ihrerseits nur mehr oder weniger dem inhaltlichen Sinn von einzelnen Zeichen oder von einzelnen Zeichenkombinationen entsprechen,
  zugeleitet werden.
• Ein Mikroprozessor soll also auch bei einem LCD-Display, das zyklisch rasch wiederholt mit Spaltensignalen zu beliefern ist, an den Eingang des ersten Ansteuerbausteins (IC1) seine Bytes bzw. Daten-Bits - abgesehen von Taktsignalen - pro anzuzeigendem Text nur ein einziges Mal liefern müssen, statt zyklisch oft pro Sekunde laufend wiederholt.
• Die Zwischenschaltung eines weiteren Bausteins, vgl. den Baustein HD44780, der einen eigenen Zeichengenerator zur Erzeugung der in die IC's einzuspeisenden Spaltensignale aufweist, soll unnötig werden.
• Trotz der Verringerung des Ansteuer- und des Zeitaufwandes sollen praktisch beliebig viele erfindungsgemäße IC's in einer damit praktisch beliebig langen Kette angeordnet werden können, indem ihre betreffenden Schieberegister leicht so in Serie geschaltet werden können, daß die betreffenden, in das Schieberegister des ersten IC eingegebenen Daten, zumindest im Regelfall ohne Änderung ihres Bitmusters, durch die Schieberegister aller IC's der Kette durchgeschoben werden.
• Außerdem soll der Mikroprozessor weiter dadurch entlastet werden, daß nur noch der betreffende ROM eines Textspeichers des ersten IC der Kette mit dann besonders kurzen, besonders rasch lieferbaren Codes vom Mikroprozessor zu versorgen ist (z.B. nur mit einem kurzen, einen langen Standardtext markierenden Code von z.B. 8 Bits und evtl. noch mit einem zugehörenden Zahlenwert-Code von ebenfalls z.B. 8 Bits), wonach der Ausgang des betreffenden ROM seinerseits zwar längere Codes, aber noch immer, verglichen mit der Anzahl der Spaltensignale, recht kurze Codes, abgibt, welche mehr oder weniger nur symbolisch ein einzelnes Zeichen oder kurzen Zeichengruppen entsprechen, wobei diese vom betreffenden ROM des ersten IC der Kette abgegebenen Codes über die in Serie geschalteten Schieberegister der IC's geschoben, anschließend in den Zeichengeneratoren der einzelnen IC's lokal umgesetzt und als konkrete Spaltensignale an die Anzeigematrix abgegeben werden.

In contrast, the invention also fulfills the following additional task:

• The control effort and the time required to supply the relevant shift register of the first IC of the chain with the data bits corresponding to the text are to be further reduced by the relevant first IC from the outside
  • - no longer even the enormous number of data bits that correspond to the specific column signals - or that then even represent cyclically repeated column signals -,
  • - Instead, only those relatively short codes as data bits, which in turn only more or less correspond to the content of individual characters or individual character combinations,
  be forwarded.
• A microprocessor should therefore only deliver its bytes or data bits - apart from clock signals - once per text to be displayed to the input of the first control module (IC1), even with an LCD display that has to be repeatedly supplied with column signals have to be repeated every second instead of cyclically.
• The interposition of another module, cf. The HD44780 module, which has its own character generator for generating the column signals to be fed into the ICs, should be unnecessary.
• Despite the reduction in the drive and the time required, practically any number of ICs according to the invention can be arranged in a chain of practically any length, so that their shift registers can be easily connected in series so that the relevant data entered into the shift register of the first IC , at least as a rule without changing their bit pattern, are pushed through the shift registers of all ICs in the chain.
• In addition, the microprocessor should be further relieved by the fact that only the relevant ROM of a text memory of the first IC of the chain is then to be supplied with particularly short, particularly quickly available codes by the microprocessor (for example only with a short code of 8 bits, for example, marking a long standard text and possibly also with an associated numerical code of 8 bits, for example ), according to which the output of the relevant ROM in turn emits longer codes, but still relatively short codes compared to the number of column signals, which more or less correspond symbolically to a single character or short character groups, these being from the relevant ROM of the The first IC of the chain is pushed over the shift registers of the ICs connected in series, then locally implemented in the character generators of the individual ICs and given as concrete column signals to the display matrix.

This very complex, new task is solved by the measures specified in claim 1.

In the invention, therefore, the enormous number of bits corresponding to the column signals S are no longer input into the input of the first shift register of the chain of ICs, but rather only the bits of short codes which approximately correspond in content to the meaning of the characters to be displayed. Only in the relevant ICs are the combinations of column signals associated with the character generated, in each case with the aid of the character generator attached there.

The microprocessor is considerably relieved, even if it is to display a very long standard text. Because the codes that are supplied by the microprocessor to the relevant first IC in the chain can often only be formed by a short address.

In the invention, the length of the chain can be practically extended, i.e. that the number of ICs connected in series can be increased practically as desired. Thus, very long texts can be easily displayed by the invention, even if only relatively few bits as short codes are only supplied to the first of these ICs, namely the input of its shift register, by the microprocessor. In the case of the invention, this microprocessor can generally supply its data bits directly to the relevant data input of the first IC of the chain without the need to interpose a further module which contains its own character generator, - cf. block 44780 in FIG. 1. Because according to the invention only relatively short codes have to be stored in the shift registers, the shift register of the last IC of this chain can be loaded comparatively quickly with its codes, so that the invention also takes the time required to prepare the display of a new long text is particularly short.

• einerseits mehrere einzeilig anzeigende Anzeigematrizen übereinander anzuordnen, um dem Leser einen mehrzeiligen Text zu bieten,
• aber andererseits jede dieser einzeiligen Anzeigematrizen mittels eigener erfindungsgemäßer IC's zu steuern.

The text displayed by the ICs according to the invention is i. general - to reduce the number of different characters that are stored in the character generator preprogrammed - be only one line. If the text to be displayed has several lines, it is often advisable for the same reason

• on the one hand to arrange several display matrices showing one line on top of each other in order to offer the reader a multi-line text,
• but on the other hand to control each of these one-line display matrices by means of their own ICs according to the invention.

The IC according to the invention only shows all of its advantages when several such ICs are connected to form a chain. However, the IC according to the invention can also be used if only a single IC according to the invention is used to display a text which is then always relatively short.

2,

einen eigenen Baustein zur Steuerung der Zeilen der Anzeigematrix einsparen zu können,

3,

ein unruhiges Flimmern der Anzeigen während der Vorbereitung eines neu anzuzeigenden Textes vermeiden zu können,

4,

eine Parallel-Serien-Umsetzung der vom Zeichengenerator gelieferten Bits zu ermöglichen,

5,

einen besonders betriebssicheren soliden Aufbau des Ausgangsregisters verwenden zu können, wobei überdies das entsprechende Ausgangs-Latchregister seinerseits zusätzlich das Flimmern des Textes bei einem Wechsel des anzuzeigenden Textes erheblich vermindert, sowie

6 und 7,

die Erfindung zur Steuerung von Anzeigematritzen verwenden zu können, wenn die Spaltensignale und/oder Zeilensignale nicht mehr in rein binärer Art stets nur aus zwei Pegeln bestehen sollen, sondern zumindest einzelne von ihnen zeitweise weitere Pegel aufweisen sollen, wie es z.B. für ein LCD-Display als Anzeigematrix oft üblich ist.

The measures specified in the subclaims allow additional advantages to be achieved. Among other things, allow the measures according to claim

2,

to be able to save a separate module for controlling the rows of the display matrix,

3,

to be able to avoid a restless flickering of the displays while preparing a new text to be displayed,

4,

enable parallel-serial conversion of the bits supplied by the character generator,

5,

to be able to use a particularly reliable, solid structure of the output register, in addition the corresponding output latch register in turn considerably reducing the flickering of the text when the text to be displayed is changed, and

6 and 7,

To be able to use the invention to control display matrices when the column signals and / or line signals are no longer to consist of only two levels in a purely binary manner, but rather at least some of them are to have additional levels at times, as is the case, for example, for an LCD display is common as a display matrix.

2

beispielhaft eine LCD-Anzeigematrix, die von insgesamt n erfindungsgemäßen IC's gesteuert wird, wobei angenommen wurde, daß der erste IC IC1 nicht nur Spaltensignale S, sondern auch Zeilensignale Z an die Anzeigematrix LCD liefert;

3

ein Beispiel für Schaltungen, die auf einem erfindungsgemäßen IC angebracht sind;

4

aufgeteilt in die beiden FIG. 4a und 4b in viel detaillierterer Weise das in FIG. 3 gezeigte Beispiel;

5

Ein Beispiel für die Verdrahtungen von dem in FIG. 4 gezeigten IC, falls damit eine Schaltung gemäß FIG. 2 mit n = 2 IC's aufgebaut wird; diese FIG dient vor allem zur Veranschaulichung der Strom- und Signalversorgung einer Kette von zwei erfindungsgemäßen IC-Beispielen, nämlich von einem dem ersten IC entsprechenden Master und einem dem zweiten IC entsprechenden Slave, wobei der die Signale liefernde Mikroprozessor nicht gezeigt ist; - dann, wenn noch weitere IC's zwischen den Master und den Slave eingefügt werden, werden diese weiteren IC's prinzipiell wie der Slave versorgt;

6

Details eines erfindungsgemäßen IC-Beispiels zur Veranschaulichung der Zusammenarbeit zwischen dem Textspeicher und dem Schieberegister; sowie

7

die Serienschaltung der Schieberegister von n = m + 1 IC's.

The invention is based on the in FIG. 2 to 7 schematically illustrated exemplary embodiments with several ICs per display matrix are further explained. The FIG.

2nd

an LCD display matrix, for example, which is controlled by a total of n ICs according to the invention, it being assumed that the first IC IC1 supplies not only column signals S but also line signals Z to the display matrix LCD;

3rd

an example of circuits which are mounted on an IC according to the invention;

4th

divided into the two FIG. 4a and 4b in much more detail that shown in FIG. 3 example shown;

5

An example of the wiring from that shown in FIG. 4 shown IC, if a circuit according to FIG. 2 is built with n = 2 IC's; this FIG serves mainly for Illustration of the power and signal supply of a chain of two IC examples according to the invention, namely of a master corresponding to the first IC and a slave corresponding to the second IC, the microprocessor providing the signals not being shown; - If additional ICs are inserted between the master and the slave, these additional ICs are basically supplied like the slave;

6

Details of an IC example according to the invention to illustrate the cooperation between the text memory and the shift register; such as

7

the series connection of the shift registers of n = m + 1 IC's.

A comparison of FIG. 1 and 2 show that in the invention the IC's IC1 ... ICn also form a chain in that their shift registers are connected in series, so that the short codes supplied by the microprocessor µP each arrive at the signal input SIN of the shift register of the first IC IC1, and can also be supplied to the signal inputs SIN of the following IC's ... ICn via the signal output SOUT of this shift register. In the prior art, cf. FIG. 1, on the other hand, the corresponding signal inputs of the shift registers of the control modules 44100/1 ... 44100 / n were not supplied with the codes, but with much more concrete column signals as very extensive bit patterns with a high expenditure of time. The ICs IC1 ... ICn according to the invention therefore each contain their own character generators, which in turn convert the codes temporarily stored in the shift registers into the many column signals S in the ICs.

As such, the microprocessor µP can directly load the relevant codes - which, for example, each correspond to a single character of the text to be displayed, into the shift register of the first IC of the chain. The FIG. 3 and 4, however, show a further development in which the microprocessor .mu.P can also be operated if necessary in such a way that - apart from possibly also from Microprocessor µP delivered clock pulses SCK - only extremely few data bits have to deliver to the ROM of a text memory TS additionally installed in the IC, which in turn only loads the shift registers of the chain with - still relatively short - codes, each of which, for example, individual characters or short ones Character combinations of the text correspond. First of all, however, an operation of the IC according to the invention in which the text memory TS is not used will be described:

FIG. 3 therefore shows an example of the structure of the circuits in an IC according to the invention. The - e.g. Short codes supplied by the microprocessor µP can be loaded directly into the input of the shift register SR1 via the data input SIN and directly via the switch S2 (in its position a), which in turn sends short codes supplied by this microprocessor µP to the data output SOUT via the data output SOUT Data input SIN of the next IC in the chain delivers. FIG. 3 shows schematically that the codes represented by byte 1, byte 2 ... pass through the memory cells of the shift register SR1 one after the other, each byte e.g. eight consecutive memory cells of the shift register SR1 are required. In this case - if no text memory TS is used - the microprocessor µP immediately delivers all the bits that are loaded into the shift register SR1.

For example, the operating mode control BAS determines the position of switches S1 and S2. The operating mode control BAS is in turn symbolically controlled from the outside together with the sequence control AB by a signal SS; FIG. 1 shows a concrete solution for their control. 4 - that is, switch S2 in position a, the data bits supplied by the microprocessor μP are shifted from the data input SIN directly into and through the shift register SR1 using the clock signal SCK. At the data output SOUT, the data of the shift register SR1 which has already been pushed through appear at the same time and can be delivered there to the data input SIN of a next IC.

At the latest as soon as the shift registers SR1 of all ICs are loaded with the desired data bits, these data bits can be inserted into the latch registers LT1 of each IC, again e.g. by means of a corresponding signal from the BAS operating mode control. E.g. The sequence controller AB can then ensure that 1 byte = 8 bits from the latch register LT1 are applied to the 8 inputs of the character generator CG via the multiplexer MUX1, the multiplexer MUX1, e.g. cyclically, puts all the bytes of the latch register LT1 one after the other at the input of the character generator CG. The operating state after the loading of all m + 1 shift registers with 14 bytes each is indicated schematically in FIG. 7, where the first IC is referred to as "master" and the m subsequent ICs as "slaves".

A particular advantage of the invention results from the fact that the microprocessor µP - apart from possibly clock pulses SCK also to be supplied by this microprocessor µP, cf. FIG. 3 and 4a - only have to feed its codes once into the relevant input of the first IC IC1 or master of the chain, even if the character generators CG of all m + 1 ICs have to deliver the column signals S to a display matrix repeatedly, often every second , if the latter, for example is an LCD display!

The character generator CG is e.g. a ROM that is addressed by the bytes created. It then successively generates the output signals corresponding to the many concrete column signals S, which in the present example are fed into the further, downstream shift register SR2. The character generator CG thus serves to convert the codes or input data byte 1, byte 2 ... loaded into the shift register SR1 into the column signals S required for the display matrix LCD, in order to generate the desired displays at the corresponding character positions and line positions.

The displays and thus the character generator output signals can also be changed during operation of the IC by changing the codes Byte 1, Byte 2 ... are changed from time to time, whereby the displayed texts are changed from time to time.

The control effort of the microprocessor µP, cf. FIG. 2, is particularly small in the invention - even if the text memory TS is not yet used - because the microprocessor μP only feeds the first IC IC1 of the chain with data, the bits of this data not representing the specific column signals S, but only relatively short codes, which in turn correspond more or less to the content of individual characters to be displayed or to entire groups of characters or combinations of characters to be displayed. The character generators CG of the individual ICs each generate the column signals S to be output by the relevant IC from the codes which are loaded in the shift registers SR1. This also means that the time required to transfer the bits from the output of the microprocessor .mu.P to the end of the last shift register of the IC Chain, compare ICn in FIG. 2, particularly low, because only relatively short codes are to be pushed through the shift register SR1 of the IC's IC1 .... ICn instead of the enormous number of specific column signals S.

Because with the one shown in FIG. 3 shown embodiment between the shift register SR1 on the one hand, and the character generator CG, or the signal outputs of the column signals S of the IC's on the other hand, a latch register LT1 is inserted, a restless flickering of the displays is avoided during the preparation of a new text to be displayed, because at (!) Loading the shift register SR1 does not immediately control the character generators CG of the IC's, but preferably only after (!) All charging shift registers SR1 of the IC's have been completed.

Incidentally, in the example shown, a special external control signal supplied to the IC can be used, for example by means of the control signal shown in FIG. 3 indicated byte 2, before the display of a (new) text, a special RAM in the character generator CG is also addressed in order to overwrite this RAM, for example with byte 1, what is shown in FIG. 4, which will be explained in more detail later, will be seen even more clearly. This development of the invention allows the special data then stored in the RAM (here, for example, from byte 1) to be used to generate very special column signals S, which are not preprogrammed in the ROM of the character generator CG, but rather are used, for example, for displaying particular rarely used characters that cannot be generated using the ROM of the character generator CG are required - for example for rarely used Greek or Cyrillic characters. The sequence control AB can also take over the clocking for this.

Incidentally, the first IC IC1 of the chain can possibly also control the few line signals Z required for the display matrix, specifically for all ICs IC1 ... ICn of the chain, possibly also by means of its sequence control AB, which means that a separate module for controlling the lines the display matrix LCD can be saved.

In the case of FIG. The example shown in FIG. 3 is additionally connected between the character generator CG and the IC pins, which emit the column signals S to the display matrix LCD, in each case with an output register SR2 and LA, in particular for parallel-serial conversion of the bits.

SR2 is also a shift register in terms of structure and operation. As soon as the shift register SR2 is loaded with the corresponding column signal data via the character generator CG, this data is temporarily stored in the further, downstream block “latch and driver output stages” LA and is sent to the column outputs of the IC - i. generally repeated cyclically quickly - output as column signals S. As is already known, an LCD display matrix sometimes needs non-binary column signals S, which therefore have further voltage levels, the output register, cf. LA, and / or assigned output driver stages must then output column signals S which contain more than two voltage levels.

The output register can e.g. are formed by a series arrangement of an output shift register SR2 and an output latch register LA. This achieves a particularly reliable, reliable structure of the output register, and in addition the corresponding output latch register in turn considerably reduces the flickering of the text when switching from one line to the next line.

The in FIG. The example of the IC according to the invention shown in FIG. 3 additionally contains the text memory TS, already mentioned several times, with its own ROM, which in each case stores the bits byte 1, byte 2 Start address, which sends the relevant bits byte 1, byte 2 ... to the shift register SR1 of this IC.

In this development of the invention, however, only the ROM of the text memory TS of the first IC of the chain, in FIG. 5 and 7 called "master", to the own shift register SR1 of this first IC the relevant bits, cf. Byte 1, byte 2 .... On the other hand, when the ROM of the text memory TS is in operation, the next, further IC's of the chain, in FIG. 5 and 7 called "slave", no bits to the own shift register SR1 of the next IC's concerned: switch S1 is only at the first IC of the chain, cf. IC1, conductive and switch S2 only in position b for the first IC of the chain - for the other ICs of the chain, i.e. for the slaves, IC1 ... ICn, however, switch S1 is in its non-conductive state and switch S2 each in its position a. In this way, the shift register (s) SR1 of the next further IC / IC's of the chain, i.e. in the case of the slaves, is only loaded from the shift register SR1 of the respective previous IC of the chain, but not from the ROM of its own text memory TS Slaves. This operation of the ROM of the text memory TS, which is addressable here by way of example by means of a small address shift register ADRL / ADRH, is shown schematically in FIG. 6 shown.

Expressed in numbers, this means that the short code supplied by the microprocessor µP e.g. Bytes can contain 8 bits each, the first byte being one character, but also an almost arbitrarily long character combination of maybe even 100 characters, for which the ROM of the text memory TS only has to be dimensioned large enough - cf. the size of the ROM in the text memory TS in FIG. 4a and 6. The master module IC1 according to the invention - unlike in the prior art, cf. the block 44100/1 in FIG. 1 - for each text to be displayed, only once instead of cyclically, often every second, with input data at the SIN input, even if an LCD display is used as the LCD display matrix. The short, e.g. 8-bit code corresponds to e.g. a single character to be displayed or even - in extreme cases even a very long, standardized - word text. A second code supplied by the microprocessor µP, e.g. a second byte can also correspond to an additional numerical value to be displayed.

A text memory ROM switched and operated in this way allows the microprocessor μP to be further relieved. In this case, namely the microprocessor μP - again apart from clock signals SCK - only delivers very short codes to the ROM of the text memory TS of the master, that is to say the first IC of the chain, but - at least in general - no longer directly to the shift register SR1 of the master IC1. The codes supplied by the microprocessor µP to the ROM of the text memory TS of the master IC1 can then e.g. also mark a very long standard text, if necessary also contain an associated numerical code, cf. e.g. the text "YOU HAVE EXCEEDED THE MAXIMUM SPEED BY .... km / h!".

The text memory TS is e.g. operated as follows:

As soon as the switch S1 is closed, the signals of the data input SIN arrive in a special shift register SRZ upstream of the text memory TS and set a counter there a starting address. This start address is used to address the ROM of the text memory TS. In the example shown, the switch S2 can then be switched to position b, for example by means of the operating mode control BAS.

If a bit or byte is now transmitted via the data input SIN with the clock SCK, the data transmitted with it are first ignored by the shift register SR1 because of the position b of the switch S2 and instead data byte 1, byte 2 ... from the text memory TS , starting from the start address selected by the microprocessor µP, shifted into the shift register SR1. After reading a first byte from the text memory TS, the counter in the special block of the shift register SRZ is increased, as a result of which the next entry in the ROM of the text memory TS is addressed or prepared.

Then the ROM of the text memory delivers a next byte to the shift register SR2, then the other bytes in a corresponding manner. These bytes supplied in the shift register SR1 can finally be pushed completely through the shift register SR1 and, in the next IC of the chain via its switch S2 in position a, load the shift register SR1 there directly. In this further development of the invention, these bytes byte 1, byte 2 ... correspond more or less to the meaning of individual characters to be displayed or short character combinations, which in turn are only converted into the more specific column signals s by means of the character generators of the individual ICs.

This in FIG. 3 schematically shown example can e.g. according to the much more detailed circuit shown in FIG. 4 shows, set up and operate:

The example of an IC according to the invention shown in FIG. 4 has 70 segment lines SEG0 ... SEG69 for 14x5 column signals S which can be output simultaneously. In addition, it has 8 backplane lines BPO ..... BP7 for 8 line signals Z, here - According to the needs of the special LCD display used here - the multiplex rate is 1: 8 and the line signals Z 4 have voltage levels VO, V1, V3, VLCD, and the column signals 3 voltage levels V0, V2, VLCD.

• 1) C1 = C2 = 0: - das Schieberegister SR1 wird aus dem Textspeicher TS geladen.
• 2) C1 = 0 ; C2 = 1: - die Daten werden vom Eingang SIN in das Schieberegister SRZ gemäß FIG 3 und 4 (bzw. ADRL/ADRH gemäß FIG 6) geladen.
• 3) C1 = 1 ; C2 = 0: - die Daten werden vom Eingang SIN unmittelbar in das Schieberegister SR1 geladen. Ist das Schiebereregister SR1 des betreffenden IC aber bereits mit allen gewünschten Daten geladen, dann übernimmt ein externer, über den Anschluß LE zugeführter Impuls diese Daten in das Latch-Register LT1, das seinerseits, gesteuert durch die interne Ablaufsteuerung gelesen wird, um die Daten als Adressen zum Adressieren des Zeichengenerators CG zu verwenden.
• 4) C1 = C2 = 1: - der Eingang SIN ist gesperrt.

In addition, this example has the connections C1 and C2, which allow the operating mode of the IC to be selected. If several ICs are connected in a chain, C1 and C2 of the master are connected to the controlling processor, cf. also FIG 5. On the other hand, for all slaves C1 is constantly set to high level and all C2 connections are directly connected to the C2 connection of the master, cf. FIG 5. This results in the following functional options:

• 1) C1 = C2 = 0: - The shift register SR1 is loaded from the text memory TS.
• 2) C1 = 0; C2 = 1: - The data are loaded from the SIN input into the shift register SRZ according to FIGS. 3 and 4 (or ADRL / ADRH according to FIG. 6).
• 3) C1 = 1; C2 = 0: - The data is loaded directly from the SIN input into the shift register SR1. If the shift register SR1 of the relevant IC is already loaded with all the desired data, then an external pulse supplied via the connection LE takes over this data into the latch register LT1, which in turn is read, controlled by the internal sequential control system, to show the data as To use addresses to address the character generator CG.
• 4) C1 = C2 = 1: - the SIN input is blocked.

In addition, the example shown in FIGS. 4 and 5 has a latch enable input LE. Depending on the level of the C2 connection, the values of the shift register contained in SRZ are transferred to the address counter in block SRZ, or the values of shift register SR1 are transferred to latch register LT1. Edge control, for example transfer with a rising edge, can be provided.

The clock already mentioned is entered via the input SCK.

SIN is the data input via which serial, synchronized with the clock pulses SCK, data bits are taken over by the microprocessor, the most significant bit preferably being transmitted first in the example shown.

SOUT is the output of the shift register SR1 of the relevant IC, whereby the input SIN of a next IC of the chain can be connected to this output SOUT, cf. also FIGS. 5 and 7.

SYNCOUT is an output that is used for synchronization. In the master, cf. 5, the output SYNCOUT is connected to the connection SYNCIN. In the slave, however, the SYCIN connector is connected to the SYNCOUT output of the master.

SYNCIN is therefore an input that is used for synchronization with the master and is set to high in the active state. WRAM is an input which is used to control the transfer of data bits from the shift register SR1 into the RAM of the character generator CG. In the active state, the connection WRAM is set to high, this connection being level-triggerable.

CLK is another clock input that can be used to control all internal processes, especially as a "pixel clock" in the example shown. The clock frequency is e.g. 14 x 80 times = 1120 times the refresh rate.

RESETN is a reset connection that is low in the active state and is used to reset internal registers.

VDD is used for + 5V logic power supply.

VLCD is used to supply positive voltages.

V3, V2, V1 are positive auxiliary voltages Voltage divider R shown in FIG. 5 can be generated from VLCD.

V0 / GND is the ground connection.

The connections mentioned are not only shown in FIG. 4, but also in FIG. 5, in order to better illustrate — existing and nonexistent — differences in the power supply and signal supply when comparing the master on the one hand and the slaves on the other hand when using ICs according to the invention according to FIG. 4 can.

The sequence control AB consists here, for example, of several divider stages. The first divider stage T / 2 halves the cycle and generates a 4-phase cycle necessary for internal processes. The second divider stage T / 5 reduces the clock rate again to 1/5 and serves to select a column in the 5x8 character matrix of the character generator CG. The third divider stage T / 14 further reduces the clock to 1/14 and is used to select a character position within that section of the display matrix LCD whose columns are controlled by the relevant IC. The fourth sub-stage T / 8 reduces the cycle to 1/8 and serves to select 1 of the 8 lines here. The "Sync. Gen." level serves for the synchronization of several ICs according to the invention with one another.

• 1) Das Schieberegister SR1 aus Textspeicher TS laden (entspricht: Schalter S2 ist in Stellung b);
• 2) Laden des Schieberegisters in SRZ mit Daten vom Dateneingang SIN (entspricht: Schalter S1 ist leitend);
• 3) Laden des Schieberegisters SR1 mit Daten vom Dateneingang SIN (entspricht. Schalter S2 ist in Stellung a); und
• 4) Deselektion des IC.

The inputs C1 and C2 can thus - by means of the operating mode control BAS and by means of logic elements or multiplexers, which the in FIG. 3 switches S1 and S2 shown correspond - 4 operating modes can be selected, cf. hence the functions of inputs C1 and C2 already mentioned above:

• 1) Load the shift register SR1 from the text memory TS (corresponds to: switch S2 is in position b);
• 2) Load the shift register into SRZ with data from the data input SIN (corresponds to: switch S1 is conductive);
• 3) Loading of the shift register SR1 with data from the data input SIN (corresponds. Switch S2 is in position a); and
• 4) Deselection of the IC.

The IC data input also includes the SIN input for data bits and the SCK input for a clock; these inputs represent a synchronous serial interface.

Control signals are thus externally applied to the internal circuit blocks via the inputs C1 and C2.

The special shift register "16 bit" in the circuit block SRZ, which corresponds to the address shift register ADRL / ADRH in FIG. 6, records the data of the data input SIN in operating mode 2) until a LE pulse follows. The downstream counter ZR can be preset with the word of the shift register "16 bit". The counter reading is used to address the ROM of the text memory TS.

The text memory TS contains a ROM with an 8-bit width here. A multiplexer MUX selects a bit from the 8 bits read from the ROM in each case, which in operating mode 1) is applied to the input of the shift register SR1. A counter Z / 8 in the text memory TS addresses the multiplexer MUX and selects all the bits that are under the relevant ROM address.

If all 8 bits are selected, the counter ZR receives a pulse in block SRZ and addresses the next address in the ROM in order to be able to read the next 8 bits from the ROM.

The shift register SR1 is 112 bits long and is divided into 14 groups of 8 bits each. This allows 14 bytes, that is eg control 14 characters via the 70 column lines S or SEGO .... ... SEG69 of the LCD display matrix. The last bit of the shift register SR1 is also fed to the SOUT output.

The latch register LT1 is used to store the entire final content of the shift register SR1.

The multiplexer MUX1 is used to select an 8-bit group (corresponds to 1 byte) from the 14 bytes stored here in the latch register LT1. The 8-bit output value output by the multiplexer MUX1, i.e. that selected byte, then serves as the address for the memory in the character generator CG.

The character generator CG contains a memory which can be addressed by the multiplexer MUX1 and by the sequence control AB and consists here of two parts, cf. ROM and RAM. So part of this memory is ROM and part is RAM. An address decoder ADR.DEC takes over the selection between the RAM and the ROM.

In the example shown, each memory entry is 5 bits wide; - This corresponds to the 5 columns, i.e. the number of columns selected here for each character, which is to be displayed in a 5-column x 8-line matrix on the display matrix LCD.

Only the content of the RAM of the character generator CG can therefore be easily changed from time to time: As already described, the column signals S for rarely needed special characters such as Greek or Cyrillic characters can be written into the RAM of the character generator CG before the text displays begin - eg to the special operating mode for loading this RAM described above. For this purpose, a pulse can be applied to the connection WRAM in order to load the address of the RAM, which can be addressed, for example, with byte 2 of shift register SR1, with the value of byte 1 of shift register SR1. This makes it possible to define those special additional characters, that is to say special characters, which have not previously been stored in the ROM of the character generator TG. If the display matrix LCD is not supplied with column signals S not only by a single IC according to the invention, that is to say alone by the master, so to speak, but if a chain of ICs according to the invention is attached, then the RAM in the character generator CG of each IC of the chain should be Both in the master and in the slave, at least in the case with the desired additional data, if the special character in question is not to be displayed only at those points in the text to be displayed which are supplied with the relevant column signals S by a single IC of the chain .

A multiplexer MUX serving as a parallel-series converter at the output of the character generator CG, controlled by the corresponding driver signals of the sequence control AB, selects 1 bit from the 5 bits that are stored by the memory ROM or RAM for the respectively activated line of the character concerned to provide. The 5 bits converted in series in this way therefore serve as an input signal for the further shift register SR2. The coordination of the processes is carried out here by the write / read logic R / W logic of the character generator CG.

The further shift register SR2 is 70 bits long here, corresponding to those 14 characters with 5 columns. In this shift register SR2 each bit corresponds to a pixel on one of the lines of the display matrix LCD controlled by the line outputs Z or BP0 ... BP7.

The latch register LATCH in the block LA serves as a memory for the content of the shift register SR2, while the further shift register SR2 is already loaded with the column signal data for the next line of the display.

The segment driver SEG in block LA is used to generate the necessary here, in some cases, digits of the output voltage profiles which require more than two voltage levels, as are required for controlling LCD display matrices, in particular with a multiplex rate 1: 8, in a manner known per se.

The line control ZA here generates from the counter readings of the last divider T / 8 of the sequence control AB the necessary output voltage curves for the lines of the display matrix LCD, which in some cases also have more than 2 levels, as is known per se for controlling an LCD display matrix with a Multiplex rate 1: 8 are required.

If only a single IC according to the invention, the master is to emit column signals S to the display matrix, that is to say if no slave is attached, then the IC according to the invention can be operated like the master in FIG. 5. If, on the other hand, one or more slaves are additionally installed, then the ROM of the text memory TS is switched off by a constant high level at C1, cf. FIG 5. All C2 connections from the master and the slaves are connected to one another and controlled jointly by the microprocessor. The SYNCIN inputs of the slaves are each directly connected to the SYNCOUT output of the master.

Claims (7)

1. Timed (CLK, SCK) drive (IC), constructed as an IC, for a display matrix (LCD) - for example as drive (IC) for an LCD display (LCD) in an on-board computer of a motor vehicle,

   - the display matrix (LCD) being intended to display a multi-place text composed of letters, figures and/or other characters,

   - the display matrix (LCD) containing columns and lines, that is to say two dimensions,

   - the display matrix (LCD) having very many more columns than lines in order to be able to display an at least i-line text,

   - a plurality of in each case identically structured ICs (IC1...ICn), that is to say a chain of such ICs, being intended to supply column signals (S) for controlling the columns of the display matrix (LCD), specifically each IC being intended to control in each case only some of the columns,

   - the IC containing a shift register (SR1) into which those bits (byte 1, byte 2.....) are shifted which themselves correspond to the text to be displayed on the display matrix, or at least to a section of this text,

   - the input (SIN) of the shift register (SR1) being connected directly, or at most via isolating switches (S2) and/or driver stages, to a pin (SIN) of the separate IC, and the output (SOUT) of the shift register (SR1) being connected directly, or at most via isolating switches (S2) and/or driver stages, to a pin (SOUT) of the separate IC, in order, when required, to be able to shift the bits (byte 1, byte 2....), under the control of the clock (SCK), successively through the chain,
      -- namely through the shift register (SR1) of the first IC (IC1) of the chain, then through the shift register (SR1) of the second IC of the chain and then, if present, through the shift registers (SR1) of further ICs (ICn), and the IC

   - being controllable during operation by a control processor,
      which calculates for example driving speeds and/or other values to be displayed,

   - on the IC, a character generator (CG) being connected downstream of the shift register (SR1),

   - the character generator (CG) containing a separate memory unit (ROM/CG), and

   - during operation, the character generator (CG) converting into output signals at least some of the bits (byte 1, byte 2.....) - which correspond essentially in each case to only a short code for the contents of the relevant characters - by means of the memory unit (ROM/CG) which is addressed by these bits (byte 1, byte 2......), the said output signals corresponding to the IC output signals (S),

   - during operation, these IC output signals being first fed as column signals (S) to the column inputs of the display matrix (LCD) which are assigned to this IC,

   - the IC containing a read-only memory, referred to as ROM (TS),

   -- which in each case stores the bits (byte 1, byte 2....) which are required for the different displays and are to be loaded into the shift register or registers (SR1) and

   -- which transmits the relevant bits (byte 1, byte 2.....) to the shift register (SR1) of this IC when (via S1) a relevant address or start address is called up,

   - during operation, only the ROM (TS) of the first IC (IC1) of the chain - but not the ROM (TS) of the next, further IC/ICs (... ICn) of the chain - transmitting to the separate shift register (SR1) of this first IC (IC1) bits (byte 1, byte 2.....) to the shift register (SR1) of the next, further IC (...ICn), and

   - during operation, the shift register or registers (SR1) of the further IC/ICs (...ICn) of the chain being loaded by the shift register (SR1) of the respective preceding IC of the chain.
2. Drive according to Patent Claim 1, characterised in that
      - the first IC (IC1) of the chain also controls the lines of the display matrix (LCD), specifically jointly for all the ICs (IC1...ICn) of the chain by being able also to feed line signals (Z) to the display matrix (LCD).
3. Drive according to one of the preceding patent claims, characterized in that
      - a latch register (LT1) which can buffer the contents of the shift register (SR1) is connected downstream between the shift register (SR1) and the character generator (CG).
4. Drive according to one of the preceding patent claims, characterized in that
      - on the IC, the column signals (S) are fed to the relevant IC pins via an output register (SR2 and LA) connected downstream of the character generator (CG).
5. Drive according to Patent Claim 4, characterized in that
      - the output register (SR2, LA) is formed by the series connection of an output shift register (SR2) and an output latch register (LA).
6. Drive for an LCD display matrix according to Patent Claim 4 or 5, characterized in that
      - the output register (SR2, LA) and/or associated output driver stages transmit column signals consisting of more than two voltage levels, that is to say not only bits.
7. Drive according to Patent Claims 2 and 6, characterized in that
      - a line output register and/or associated driver stages transmit line signals consisting of more than two voltage levels, that is to say not only bits.

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