Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
  • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
  • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
  • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
  • G06F7/52—Multiplying; Dividing
  • G06F7/535—Dividing only
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
  • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
  • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
  • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
  • G06F7/552—Powers or roots, e.g. Pythagorean sums
  • G06F7/5525—Roots or inverse roots of single operands
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
  • G06F2207/535—Indexing scheme relating to groups G06F7/535 - G06F7/5375
  • G06F2207/5355—Using iterative approximation not using digit recurrence, e.g. Newton Raphson or Goldschmidt
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
  • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
  • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
  • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
  • G06F7/487—Multiplying; Dividing
  • G06F7/4873—Dividing

Definitions

• determination of a convergence factor for convergent division generally requires a normalization step, a subtraction operation requiring a carry-propagate step, and another normalization step.
• Determination of a convergence factor for a square root computation requires a scaling computation. Evaluation of a convergence factor for both the convergent division and the square root determination thus requires more computation cycles than a floating-point multiplication computation. Because the convergence factors occur serially in both computations, the inefficiency of the computation of the convergence factors has directly reduced the efficiency of computation within both the convergent division and square root determination algorithms. The need exists for a more efficient method of determining convergence factors for convergent division and for square root determination to facilitate these two over-all processes within a digital platform. Summary of the Invention
• the present invention enhances the efficiency of determining convergence factors for floating-point convergent division and square root determination in a numeric processor, such as a digital signal processor, by expediting the convergence factor determinations via combinational logic and by assuming a limited range for a modified input value for a convergence factor determination.
• This approach avoids a subtraction and carry-propagation operation, thereby allowing both convergent algorithm computations to be limited primarily by a multiplier latency time factor.
• FIG. 1 is a block diagram depicting one embodiment of the invention.
• FIG. 2 is a block diagram depicting one embodiment of a determination of a new normalized significand for enhancing convergence factor determination in a convergent division computation.
• FIG. 3 is a block diagram depicting one embodiment of a determination of a new normalized significand for enhancing convergence factor determination in a square root determination.
• FIG. 4 is block diagram of a computer hardware implementation of the invention.
• FIG. 1 generally depicted by the numeral 100, is a flow chart setting forth one embodiment of the present invention that utilizes determination of a new normalized significand (f ) via an expedient combinational logic, as opposed to multiple operations, to determine a new value for X (116), being X', and obtains a convergence factor utilized in a mathematical determination, being convergent division or square root determination, that is iterated until a solution with a predetermined degree of accuracy is obtained (118, 120).
• a numeric processor (such as a digital signal processor) utilizes a processing platform to check an input X to determine whether or not X is equal to ⁇ ⁇ , ⁇ 0, or Not-a-Number (NaN) (102). If X is equal to ⁇ «», ⁇ 0, or NaN, an error-check mechanism bypasses convergence factor determination according to a rationale that utilizes a range limitation of X to 0.5 ⁇ X ⁇ ⁇ (122, ⁇ being set out more specifically below).
• X is other than ⁇ °°, ⁇ 0, or NaN
• Set X to X 2 C * f, provided that 1 ⁇ f ⁇ 2 (105).
• ⁇ X ⁇ 1.0 If it is not true that 0.5 ⁇ X ⁇ 1.0, then 1.0 ⁇ X ⁇ ⁇ (108), and e is set to 0 (112).
• the platform utilizes X' to compute a convergence factor for the mathematical determination being invoked, being convergent division or square root determination (118). Then a convergence algorithm is computed for the mathematical determination being invoked, convergent division or square root determination, and is iterated until a solution with a predetermined degree of accuracy is obtained (120).
• the processing platform biases the exponent e in accordance with the IEEE 754-1985 floating ⁇ point standard using an odd bias, yielding a biased exponent with a least significant bit (lsb)(206). If the least significant bit of the biased exponent is 1 (214), a binary f value of l.wxyzO is selected (212, 213). If the least significant bit of the biased exponent is 0, a binary f value of l.lvwxy is selected (212, 215).
• the selected value of f to the right of the binary decimal is inverted (216) to yield a binary number of l.Ov'w'x'y' for f if the related least significant bit is 0 and l.w'x'y'z'l for f if the related least significant bit is 1 (218).
• the least significant bit of the biased exponent e is inverted (208) to form a final biased exponent for f (210).
• the processing platform biases the exponent e in accordance with the IEEE 754-1985 floating-point standard using an odd bias, yielding a biased exponent with a least significant bit (306). If the least significant bit of the biased exponent is 1 (314), a binary f value of l.vwxyz is selected (312 , 313). If the least significant bit of the biased exponent is 0 (314), a binary f value of l.l lvwx is selected (312 , 315).
• the selected value of f to the right of the binary decimal is then inverted (316) to yield a binary number of l.OOv'w'x' if the related least significant bit is 0 and l .v'w'x'y'z' if the related least significant bit is 1 (318).
• the least significant bit of the biased exponent e is inverted (308) to form a final biased exponent for f (310). It should be noted that, both in convergent division and square root determination, convergence factor determination will incur one Isb of error. The cause of the one lsb of error is due to the use of the one's complement rather than the two's complement operation.
• the two's complement While the two's complement will not give the one lsb of error, the two's complement requires a carry propagation which slows down the convergence factor determination.
• the one's complement avoids this carry propagation and is preferred because of its speed.
• the one lsb of error is negligible in convergence algorithms since the computation is typically performed using extended precision hardware and is then rounded to a lower precision.
• FIG. 4 depicts a hardware implementation of the present invention, generally depicted by the numeral 400.
• a computer program for implementation of the present invention may be stored in the program memory (404), other memory (412), or may be embodied in hardware in the arithmetic logic unit
• ALU (406) by allocation of data storage means and data manipulation means of a numeric processor.
• a primary selecting means of the ALU selects a value of negative one for e where 0.5 ⁇ X ⁇ 1.0, and a secondary selecting means of the ALU selects a value of zero for e where 1.0 ⁇ X ⁇ 1.5 (406).
• a tertiary selecting means of the ALU selects a value of negative one for e where 0.5 ⁇ X ⁇ 1.0, and a quaternary means of the ALU selects a value of zero for e where 1.0 ⁇ X ⁇ 2.0 (406).
• This exponent e is biased with an odd bias value according to the IEEE 754-1985 floating-point standard.
• f X/2 e provided that 1 ⁇ f ⁇ 2
• f a series of binary bits consisting of a most significant bit, being one, to the left of a point and remaining binary bits to the right of the binary point, generally described here as l.vwxyz (406).
• the ALU selects an output of a most significant binary bit of one to the left of the binary point and of one followed by the binary bits to the right of the binary point for the new binary bits to the right of the binary point (406).
• the ALU selects an output of a most significant binary bit of one to the left of the binary point and of the initially second and all following binary bits to the right of the binary decimal point together with a zero for the new binary bits to the right of the binary point (406).
• the ALU selects an output of a most significant binary bit of one to the left of the binary point and of two ones followed by all bits initially to the right of the binary decimal for the new binary bits to the right of the binary point (406).
• the ALU selects an output of a most significant binary bit of one to the left of the binary point and of all bits initially to the right of the binary point for the new binary bits to the right of the binary point (406).
• the ALU then inverts all bits to the right of the binary decimal point for all mathematical determinations described above, the output being f (406).
• the ALU determines a convergence factor of 2.0 - X' and for square root determination the ALU determines a convergence factor of 1.5 - 0.5X' (406).
• the ALU utilizes one or more data manipulation and storage devices for computing a convergent division algorithm or a square root determination employing a related convergence factor until a solution with a predetermined degree of accuracy is obtained (406).

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• 1990
  • 1990-12-03 CA CA002050353A patent/CA2050353C/en not_active Expired - Fee Related
  • 1990-12-03 EP EP19910901464 patent/EP0461230A4/en not_active Withdrawn
  • 1990-12-03 WO PCT/US1990/007034 patent/WO1991010188A1/en not_active Application Discontinuation
  • 1990-12-03 KR KR1019910701002A patent/KR940008610B1/ko not_active IP Right Cessation
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