EP0454201A2 - Halbleiteranordnung mit einem Thyristor - Google Patents

Halbleiteranordnung mit einem Thyristor Download PDF

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Publication number
EP0454201A2
EP0454201A2 EP19910200798 EP91200798A EP0454201A2 EP 0454201 A2 EP0454201 A2 EP 0454201A2 EP 19910200798 EP19910200798 EP 19910200798 EP 91200798 A EP91200798 A EP 91200798A EP 0454201 A2 EP0454201 A2 EP 0454201A2
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EP
European Patent Office
Prior art keywords
region
thyristor
conductivity type
semiconductor device
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP19910200798
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English (en)
French (fr)
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EP0454201A3 (en
EP0454201B1 (de
Inventor
Paul Arthur Gough
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Electronics UK Ltd
Koninklijke Philips NV
Original Assignee
Philips Electronics UK Ltd
Philips Gloeilampenfabrieken NV
Koninklijke Philips Electronics NV
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Publication date
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Publication of EP0454201A2 publication Critical patent/EP0454201A2/de
Publication of EP0454201A3 publication Critical patent/EP0454201A3/en
Application granted granted Critical
Publication of EP0454201B1 publication Critical patent/EP0454201B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/749—Thyristor-type devices, e.g. having four-zone regenerative action with turn-on by field effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744—Gate-turn-off devices
    • H01L29/745—Gate-turn-off devices with turn-off by field effect
    • H01L29/7455—Gate-turn-off devices with turn-off by field effect produced by an insulated gate structure

Definitions

  • This invention relates to a semiconductor device comprising a thyristor and especially, but not exclusively, to a semiconductor device comprising a so-called MOS-gated thyristor.
  • Semiconductor devices which comprise a semiconductor body having formed therein a thyristor having a first region of one conductivity type provided with a first main electrode, a second region of the opposite conductivity type forming a first pn junction with the first region, a third region of the one conductivity type forming a second pn junction with the second region and provided with a gate electrode, and a fourth region of the opposite conductivity type forming a third pn junction with the third region and having an electrical connection to a second main electrode.
  • semiconductor devices are known in which the gate electrode is in the form of an insulated gate overlying a conduction channel area of the third region for controlling a conductive path between the second region and the fourth region to enable the flow of charge carriers of the opposite conductivity type from the fourth region to the second region to trigger latching and so initiate thyristor action within the device.
  • MOS-gated thyristor is described at page 411 of a review entitled 'Evolution of MOS-bipolar Power Semiconductor Technology by B. Jayant Baliga published in Proceedings of the IEEE Vol. 76, No. 4, April, 1988.
  • MOS turn-off thyristor which differs from the simple MOS-gated thyristor in that it is capable of being both turned-on and turned-off by a signal applied to a MOS gate.
  • the MOS turn-off thyristor consists of an insulated gate field effect transistor (MOST) integrated into the thyristor structure in such a manner that the emitter-base junction of the upper transistor can be short-circuited by the application of a gate voltage to the MOST.
  • MOST insulated gate field effect transistor
  • the device can be switched on either in the same manner as a conventional thyristor or by using a MOS gate in the same manner as for a MOS-gated thyristor.
  • the MOS turn-off thyristor has a fifth region of the one conductivity type formed within and shorted to the fourth region and the contiguous insulated gate overlies channel areas of the fourth and third regions.
  • the MOST defined between the fifth and third regions is turned-on by an appropriate voltage applied to the insulated gate so that charge carriers of the one conductivity type entering the third region have an alternate path to the second main electrode by-passing the pn junction between the fourth and third regions.
  • the resistance of the current path for the charge carriers of the one conductivity type must be so low that, when all such current is diverted via the MOST between the fifth and third regions, the forward biassing of the third pn junction is below 0.7 volts and so insufficient to maintain electron injection and transistor action.
  • a semiconductor device comprising a semiconductor body having formed therein a thyristor having a first region of one conductivity type provided with a first main electrode, a second region of the opposite conductivity type forming a first pn junction with the first region, a third region of the one conductivity type forming a second pn junction with the second region and provided with a gate electrode, and a fourth region of the opposite conductivity type forming a third pn junction with the third region and having an electrical connection to a second main electrode, characterised in that a fifth region of the one conductivity type forms a fourth pn junction with the fourth region, a sixth region of the opposite conductivity type in electrical connection with the second main electrode forms a fifth pn junction with the fifth region and an insulated gate overlies a conduction channel area of the fifth region for defining a conductive path for charge carriers of the opposite conductivity type into the fourth region for initiating thyristor action, the fifth region being electrically connected to provide a
  • electrical connection to the fourth region is provided by an integrated insulated gate field effect transistor (MOST) effectively in series with the fourth region which provides a gateable conductive path for the flow of charge carriers of the opposite conductivity type to the fourth region so enabling the flow of such charge carriers to be stemmed by application of an appropriate gate voltage during turn-off of the thyristor to improve the controllable current capability of the thyristor.
  • MOST integrated insulated gate field effect transistor
  • the control over the flow of the charge carriers of the opposite conductivity type provided by the MOS in series with the fourth region should reduce turn-off times in comparison to the previously described MOS-controlled thyristors described above.
  • the gate electrode of the third region may comprise an insulated gate overlying a channel area of the third region.
  • the insulated gate overlying the third region may be contiguous with the insulated gate overlying the fifth region which may simplify manufacture.
  • the contiguous insulated gates may be defined on the side walls of a groove extending into the semiconductor body.
  • the groove may be in the form of a trench having its side walls covered by an insulating layer and being filled with electrically conductive material forming the gate electrode.
  • the use of a groove or trench technology rather than a planar technology to form the insulated gates reduces the amount of surface area required and should provide better current handling capabilities.
  • the third, fourth, fifth and sixth regions are replaced by a further region of the one conductivity with the insulated gate overlying a conduction channel area of the further region so that the further region defines with the first and second regions a three layer structure arranged in parallel with the structure defined by the first to sixth regions between the first and second main electrodes so that the further region provides a path for extraction of charge carriers of the one conductivity during turn-off of the thyristor.
  • Such a structure enables an increase in the turn-off speed of the device and should, by diverting the current flow of the one conductivity type, also increase the maximum controllable current.
  • the first and second main electrodes may be provided on opposed surfaces of the semiconductor body so forming a vertical device, that is a device which the main current path is between the two opposed major surfaces of the semiconductor body.
  • the fifth region may be electrically connected to the second main electrode so as to form a three terminal device.
  • a separate further electrode may be provided for the fifth region which because of the independent control of the voltages applied to the second and further electrodes should further reduce the possibility of transistor action continuing during turn-off of the thyristor.
  • a semiconductor device comprising a semiconductor body 1 having formed therein a thyristor having a first region 4 of one conductivity type provided with a first main electrode A, a second region 5 of the opposite conductivity type forming a first pn junction 6 with the first region 4, a third region 8 of the one conductivity type forming a second pn junction 7 with the second region 5, and provided with a gate electrode G, and a fourth region 9 of the opposite conductivity type forming a third pn junction 10 with the third region 7 and having an electrical connection to a second main electrode C.
  • a fifth region 11 of the one conductivity type forms a fourth pn junction 12 with the fourth region 9
  • a sixth region 13 of the opposite conductivity type in electrical connection with the second main electrode C forms a fifth pn junction 14 with the fifth region 11 and an insulated gate 15 overlies a conduction channel area 110 of the fifth region for defining a conductive path for charge carriers of the opposite conductivity type into the fourth region 9 for initiating thyristor action, the fifth region 11 being electrically connected to provide a path for extraction of charge carriers of the one conductivity type during turn-off of the thyristor.
  • an insulated gate field effect transistor provided by the fourth, fifth and sixth regions 9,11 and 13 and the insulated gate 15 is provided in series with the fourth region 9 of the thyristor to provide a gateable conductive path via the conduction channel area 110 for the flow of charge carriers of the opposite conductivity type to the fourth region 9 so enabling this flow to be stemmed by application of an appropriate gate voltage during turn-off of the thyristor to allow a greater controllable current capability and in addition to enable the turn-off time of the device to be reduced.
  • MOST insulated gate field effect transistor
  • FIG. 1 there is illustrated an npnp thyristor having a MOS-gated cathode in accordance with the invention.
  • the first or anode region 4 is provided as a monocrystalline silicon substrate doped with impurities of the one conductivity type, in this example boron ions, to provide a resistance of 3 typically 0.01 ohm cm.
  • the second or n-base region 5 is then provided on the first region 4 as a relatively lowly doped epitaxial layer of silicon doped with impurities of the opposite conductivity type, in this case n conductivity type, for example arsenic ions, to a dopant concentration of typically 1014 atom cm ⁇ 3
  • a more highly n-conductivity type doped buffer layer 50 may be provided between the first and second regions 4 and 5 to moderate the hole current from the relatively highly doped first or anode region 4.
  • the dopant concentration and thickness of the epitaxial layer deposited to form the second region 5 will depend on the desired characteristics of the device but may typically be 100 ⁇ m (micrometres) for a 1000 volt device.
  • the third region 8 may be provided as an epitaxial layer doped with impurities of the one conductivity type, p type in this example, or alternatively may be formed by implantation and/or diffusion of impurities into the second region 5.
  • the third region, in this example the p-base region 8, the fourth or cathode region 9, and the fifth region 11 may all be formed either by epitaxial growth of appropriately doped layers of silicon or by implantation and/or diffusion of the appropriate impurities into the second region 5.
  • the p-base region may have a thickness of about 3 ⁇ m and a dopant concentration of about 1016 atoms cm ⁇ 3
  • the cathode region 9 may have a thickness of about 1 ⁇ m and a dopant concentration of about 1016 atom cm ⁇ 3.
  • the fifth regtion 11 may be about 2 ⁇ m thick and have a dopant concentration of about 3 x 1016 atoms cm ⁇ 3.
  • the sixth region 13 is then formed as a planar region within the fifth region 11 by introducing impurities of the opposite conductivity type, n conductivity type in this example, through an appropriate mask (not shown) in conventional manner.
  • the sixth region 13 may have a depth of about 0.5 to 1 ⁇ m.
  • the thyristor shown in Figure 1 is a MOS-gated thyristor so that the gate electrode G of the third region 7 comprises an insulated gate and in the example being described this insulated gate is contiguous with the insulated gate 15 of the MOS-gated cathode.
  • the insulated gate 15 is defined by first etching, using conventional techniques, a trench 16 through the sixth, fifth, fourth and third regions 13,11,9,7 and slightly into the second region 5.
  • the depth of the trench should, as is known in the art, be carefully controlled so as to ensure that the trench 16 extends completely through the third region 8 but does not extend so far into the second region 5 as to adversely effect the desired breakdown voltage of the device.
  • the trench 16 will be about 6 ⁇ m deep.
  • a thin insulating layer 17 is thermally grown by conventional techniques on the side walls of the trench and with the mask used during definition of the trench still in place, electrically conductive material, in this example doped polycrystalline silicon, is deposited into the trench to form an electrically conductive plug 18 providing the gate electrode G of the third region 8 and also the insulated gate 15 overlying the conduction channel area 110 of the fifth region 11.
  • electrically conductive material in this example doped polycrystalline silicon
  • Conventional metallisation 19,20 for example aluminium, is then deposited onto the opposed surfaces 2 and 3 of the semiconductor body 1 to define the first (anode) and second (cathode) main electrodes A and C. Although not shown in Figure 1, contact is made to the gate G at the periphery of the device I.
  • the fifth region 11 is shorted via the cathode metallisation to the second (cathode) main electrode C.
  • the device will have a cellular structure with the trench 16 forming, when viewed in plan (that is looking down onto the surface of the fifth region 11), a grid or mesh structure.
  • the trench 16 may form a rectangular grid pattern or possibly a hexagonal grid pattern.
  • Figure 1 thus shows a cross-section through one strip like section of the grid - like trench 16.
  • the device is turned-on by applying an appropriate positive gate voltage +Ve to the gate electrode G.
  • the positive gate voltage induces an n conductivity type inversion channel in the conduction channel areas 110 and 80 along the edge of the trench 16 allowing the flow of electrons into the second region 5 and thus causing the first pn junction 6 to become forward-biassed.
  • This forward-biassing of the first pn junction 6 causes holes to be injected into the second region 5 which flow into the third regions 8 to form, effectively, a base current for the npn transistor formed by the second, third and fourth regions 5,8,9.
  • the turning-on of this transistor initiates triggering or latching of the thyristor so that the device is now switched on.
  • the thyristor may be turned-off by applying a negative gate voltage -Ve to the gate electrode G causing a p conductivity type inversion channel to be formed in a conduction channel area 90 of the fourth region 9 adjacent the trench 16.
  • This has the effect of preventing or at least inhibiting the flow of electrons from the sixth region 13 to the fourth (cathode) region 9 thus starving the thyristor of electrons and so initiating turn-off of the thyristor.
  • the p conductivity channel thus formed in the conduction channel area 90 of the fourth (cathode) region 9 between the third and fifth region 8 and 11 provides a conductive path for the extraction of holes via the cathode metallisation 20 to which the fifth region 11 is shorted.
  • the lateral extent of the sixth region 13 can be made very small so that the path for holes beneath the sixth region to the cathode metallisation and so the possibility of the pn junction 14 becoming sufficiently forward biassed to initiate transistor action is insignificant.
  • the sixth region 13 could be formed as several discrete subsidiary regions so that when viewed in plan, that is looking down on the major surface 3, the sixth region is formed by separate islands or fingers spaced along and adjoining the edges of the trench.
  • the gate electorde G is continuous, where as described above the device has a cellular structure, the cells at the periphery of the device may have a gate electrode contact which is separate from that of the central cells which may enable better control of the turn off of the device by allowing the turn-off of the central cells to be controlled independently of the peripheral cells.
  • Figure 2 is a cross-sectional similar to Figure 1 of a second embodiment of a device in accordance with the invention.
  • the device shown in Figure 2 differs from that shown in Figure 1 in that a VMOS type MOS gate 160,170,180 rather than a trenchfet type MOS gate is provided and in that a separate electrical contact 21 is provided for the fifth region 11 by definition in conventional manner of an insulating region 22 of, for example silicon dioxide, on the major surface 3 and by appropriate conventional patterning of the subsequently deposited cathode metallisation 20.
  • a VMOS type MOS gate 160,170,180 rather than a trenchfet type MOS gate
  • a separate electrical contact 21 is provided for the fifth region 11 by definition in conventional manner of an insulating region 22 of, for example silicon dioxide, on the major surface 3 and by appropriate conventional patterning of the subsequently deposited cathode metallisation 20.
  • the fifth region can, at the expense of having four terminals, be biassed independently of the sixth region 13 and so further assists in avoiding the possibility of the pn junction 14 becoming sufficiently forward-biassed to initiate transistor action when attempting to turn-off the device.
  • the thyristor shown in Figure 2 operates in the same manner as that shown in Figure 1 although of course holes extracted during turn-off are extracted via the further electrode 22 provided by the metallisation 21 rather than via the cathode C metallisation 20.
  • the device shown in Figure 1 may similarly be provided with a separate electrical contact for the fifth region by appropriate patterning of the cathode metallisation 20.
  • the device shown in Figure 2 may be manufactured using conventional VMOS technology and may have a cellular structure similar to that of the device shown in Figure 1.
  • Figure 3 illustrates a modified version of a device in accordance with the invention.
  • a device in accordance with the invention may have a cellular structure with an array or pattern of sixth region 13 and a grid-like, when viewed looking down on the surface, insulated gate 15 to define a number of parallel-connected MOSTs provided by the fourth, fifth and sixth regions 9,11 and 13 and the insulated gate 15.
  • an area 30 of the semiconductor body 1 bounded by the trench or groove 16 of the insulated gate structure is in the form of a region of the one conductivity type, p conductivity type in this example, which extends from the second region 5 to the surface at which the metallisation 20 is provided to define the cathode contact C.
  • the device defines a three layer, pnp in this example, structure.
  • regions 30 or cells of the one conductivity type may be provided in the cellular structure of the device, for example alternate cells may be formed using the regions 30, by diffusion of an appropriate dopant, such as boron in this example, through a suitable mask after completion of any epitaxial growth of layers.
  • an appropriate dopant such as boron in this example
  • the device shown in Figure 3 operates in a similar manner to those shown in Figures 1 and 2 except that during turn-on with an appropriate positive gate voltage +Ve applied to the gate electrode G, in addition to the n conductivity inversion channels in the conduction channel areas 110 and 80, an n conductivity inversion channel is induced in a conduction channel area 300 defined by the region 30 adjacent the insulated gate 15.
  • the p conductivity type region 30 provides a path to allow holes to be extracted from the device.
  • the structure shown in Figure 3 enables an increase in the speed of turn-off and by diverting the hole current flow should also increase the maximum controllable current.
  • the provision of the p conductivity type region 30 will increase the on-resistance of the device.
  • it should be possible to optimise the device structure for the desired operating characteristics by adjusting the ratio of p conductivity type cells or regions 30 to MOST cells 9,11,13 and so adjusting the trade-off between turn-off speed and on-resistance.
  • the device is a vertical device, that is a device with the main current path between the two opposed major surfaces 2 and 3 of the semiconductor body 1, this need not necessarily be the case and the present invention may be applied to lateral devices, that is devices with current flow in a direction along the major surfaces.
  • the devices described use a grooved technology to define the insulated gate structure, it may be possible, with appropriate geometry adjustment, to apply the present invention to a planar technology where the insulated gate 15 is formed on the one major surface 3 and the regions 8,9 and 11 are like the region 13 formed as planar regions by introducing, using appropriate maskings, impurities into the surface of the second region 5. With such a planar geometry, the channel length at the surface of the device would necessarily be rather long.
  • the insulated gates G, 15 are described above as being contiguous or integral, they may be discrete and may be separately operable.
  • the gates G, 15 may be formed by having separate grooves for the insulated gate G and for the insulated gate 15 or by appropriate patterning where a planar technology is used.
  • the semiconductor conductivity types given above can be reversed to form a pnpn thyristor and that the present invention may be applied to semiconductor materials other than silicon, for example germanium or III-V materials such as gallium arsenide or to devices involving heterojunction structures.
  • the sixth region 13 could be formed by depositing a wider bandgap material such as silicon carbide where the device is a silicon device on the fifth region 11 and then, using apporpriate masking and etching technology, defining the sixth region 13 as a mesa structure on the fifth region 11.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)
EP91200798A 1990-04-09 1991-04-05 Halbleiteranordnung mit einem Thyristor Expired - Lifetime EP0454201B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9008020 1990-04-09
GB9008020A GB2243021A (en) 1990-04-09 1990-04-09 Mos- gated thyristor

Publications (3)

Publication Number Publication Date
EP0454201A2 true EP0454201A2 (de) 1991-10-30
EP0454201A3 EP0454201A3 (en) 1991-11-06
EP0454201B1 EP0454201B1 (de) 1996-10-30

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EP91200798A Expired - Lifetime EP0454201B1 (de) 1990-04-09 1991-04-05 Halbleiteranordnung mit einem Thyristor

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EP (1) EP0454201B1 (de)
JP (1) JPH0793422B2 (de)
DE (1) DE69122902T2 (de)
GB (1) GB2243021A (de)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0487869A1 (de) * 1990-11-29 1992-06-03 Asea Brown Boveri Ag Abschaltbares Leistungshalbleiter-Bauelement
EP0520355A1 (de) * 1991-06-28 1992-12-30 Asea Brown Boveri Ag Mittels Steuerelektrode abschaltbares Leistungshalbleiter-Bauelement sowie Verfahren zu dessen Herstellung
DE4230319A1 (de) * 1991-09-13 1993-03-18 Fuji Electric Co Ltd Leistungsschaltende halbleitereinrichtung mit einem si-thyristor und einem in kaskade angeschlossenen mos-feldeffekttransistor
DE4242578A1 (en) * 1991-12-20 1993-06-24 Mitsubishi Electric Corp Emitter switched thyristor - has transistor zone with alternative diffusion layers and diffusion zone formed above insulating film
DE4244436A1 (de) * 1992-03-16 1993-09-30 Mitsubishi Electric Corp Halbleitervorrichtung und Herstellungsverfahren
EP0565349A2 (de) * 1992-04-07 1993-10-13 Toyo Denki Seizo Kabushiki Kaisha MOS-kontrollierter Thyristor
EP0569116A1 (de) * 1992-05-06 1993-11-10 Mitsubishi Denki Kabushiki Kaisha Emitter-geschalteter Thyristor und Verfahren zu seiner Herstellung
EP0785582A3 (de) * 1996-01-16 1999-08-04 Harris Corporation MOS-gesteuerter Thyristor mit Grabengate
EP1261034A2 (de) * 1992-03-04 2002-11-27 Zaidan Hojin Handotai Kenkyu Shinkokai Statischer Induktionsthyristor
WO2008024636A2 (en) * 2006-08-25 2008-02-28 Hvvi Semiconductors, Inc. Electrical stress protection apparatus and method of manufacture

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5381026A (en) 1990-09-17 1995-01-10 Kabushiki Kaisha Toshiba Insulated-gate thyristor
JP5698302B2 (ja) * 2013-04-25 2015-04-08 株式会社日立製作所 半導体装置

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EP0106059A1 (de) * 1982-08-18 1984-04-25 Siemens Aktiengesellschaft Halbleiterschalter mit einem abschaltbaren Thyristor
EP0159663A2 (de) * 1984-04-26 1985-10-30 General Electric Company Thyristoren, Feldeffekttransistoren mit isoliertem Gate und MOSFETs hoher Dichte gesteuert durch eine in einer V-Nut angebrachte MOS-Struktur und Verfahren zur Herstellung
EP0487869A1 (de) * 1990-11-29 1992-06-03 Asea Brown Boveri Ag Abschaltbares Leistungshalbleiter-Bauelement

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Publication number Priority date Publication date Assignee Title
EP0106059A1 (de) * 1982-08-18 1984-04-25 Siemens Aktiengesellschaft Halbleiterschalter mit einem abschaltbaren Thyristor
EP0159663A2 (de) * 1984-04-26 1985-10-30 General Electric Company Thyristoren, Feldeffekttransistoren mit isoliertem Gate und MOSFETs hoher Dichte gesteuert durch eine in einer V-Nut angebrachte MOS-Struktur und Verfahren zur Herstellung
EP0487869A1 (de) * 1990-11-29 1992-06-03 Asea Brown Boveri Ag Abschaltbares Leistungshalbleiter-Bauelement

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0487869A1 (de) * 1990-11-29 1992-06-03 Asea Brown Boveri Ag Abschaltbares Leistungshalbleiter-Bauelement
US5286981A (en) * 1991-06-28 1994-02-15 Asea Brown Boveri Ltd. Turn-off power semiconductor component, and also process for producing it
EP0520355A1 (de) * 1991-06-28 1992-12-30 Asea Brown Boveri Ag Mittels Steuerelektrode abschaltbares Leistungshalbleiter-Bauelement sowie Verfahren zu dessen Herstellung
DE4121375A1 (de) * 1991-06-28 1993-01-14 Asea Brown Boveri Abschaltbares leistungshalbleiter-bauelement sowie verfahren zu dessen herstellung
DE4230319A1 (de) * 1991-09-13 1993-03-18 Fuji Electric Co Ltd Leistungsschaltende halbleitereinrichtung mit einem si-thyristor und einem in kaskade angeschlossenen mos-feldeffekttransistor
DE4242578A1 (en) * 1991-12-20 1993-06-24 Mitsubishi Electric Corp Emitter switched thyristor - has transistor zone with alternative diffusion layers and diffusion zone formed above insulating film
US5477064A (en) * 1991-12-20 1995-12-19 Mitsubishi Denki Kabushiki Kaisha Thyristor
EP1261034A2 (de) * 1992-03-04 2002-11-27 Zaidan Hojin Handotai Kenkyu Shinkokai Statischer Induktionsthyristor
EP1261034A3 (de) * 1992-03-04 2003-04-16 Zaidan Hojin Handotai Kenkyu Shinkokai Statischer Induktionsthyristor
DE4244436A1 (de) * 1992-03-16 1993-09-30 Mitsubishi Electric Corp Halbleitervorrichtung und Herstellungsverfahren
US5389801A (en) * 1992-03-16 1995-02-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having increased current capacity
DE4244436C2 (de) * 1992-03-16 2001-01-25 Mitsubishi Electric Corp Emitter-geschalteter Thyristor und Verfahren zu seiner Herstellung
EP0565349A3 (de) * 1992-04-07 1994-12-14 Toyo Electric Mfg Co Ltd
EP0565349A2 (de) * 1992-04-07 1993-10-13 Toyo Denki Seizo Kabushiki Kaisha MOS-kontrollierter Thyristor
US5345095A (en) * 1992-05-06 1994-09-06 Mitsubishi Denki Kabushiki Kaisha Self arc-extinguishing thyristor and method of manufacturing the same
EP0569116A1 (de) * 1992-05-06 1993-11-10 Mitsubishi Denki Kabushiki Kaisha Emitter-geschalteter Thyristor und Verfahren zu seiner Herstellung
EP0785582A3 (de) * 1996-01-16 1999-08-04 Harris Corporation MOS-gesteuerter Thyristor mit Grabengate
WO2008024636A2 (en) * 2006-08-25 2008-02-28 Hvvi Semiconductors, Inc. Electrical stress protection apparatus and method of manufacture
WO2008024636A3 (en) * 2006-08-25 2008-08-14 Hvvi Semiconductors Inc Electrical stress protection apparatus and method of manufacture

Also Published As

Publication number Publication date
DE69122902D1 (de) 1996-12-05
EP0454201A3 (en) 1991-11-06
EP0454201B1 (de) 1996-10-30
JPH0793422B2 (ja) 1995-10-09
DE69122902T2 (de) 1997-04-30
GB2243021A (en) 1991-10-16
GB9008020D0 (en) 1990-06-06
JPH04312977A (ja) 1992-11-04

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