EP0374641B1 - Verfahren zur Ausregelung von Amplitudenschwankungen zweier um 90o el. phasenverschobener, alternierender, periodischer Signale beliebiger Phasenfolge und Schaltungsanordnung zur Durchführung des Verfahrens - Google Patents

Verfahren zur Ausregelung von Amplitudenschwankungen zweier um 90o el. phasenverschobener, alternierender, periodischer Signale beliebiger Phasenfolge und Schaltungsanordnung zur Durchführung des Verfahrens Download PDF

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Publication number
EP0374641B1
EP0374641B1 EP89122722A EP89122722A EP0374641B1 EP 0374641 B1 EP0374641 B1 EP 0374641B1 EP 89122722 A EP89122722 A EP 89122722A EP 89122722 A EP89122722 A EP 89122722A EP 0374641 B1 EP0374641 B1 EP 0374641B1
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EP
European Patent Office
Prior art keywords
signals
amplitude
circuit arrangement
positive
negative
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP89122722A
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German (de)
English (en)
French (fr)
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EP0374641A3 (de
EP0374641A2 (de
Inventor
Ralf Dipl.-Ing. Schweigert (Fh)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
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Siemens AG
Siemens Corp
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Publication of EP0374641A3 publication Critical patent/EP0374641A3/de
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Publication of EP0374641B1 publication Critical patent/EP0374641B1/de
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/12—Regulating voltage or current  wherein the variable actually regulated by the final control device is AC
    • G05F1/40—Regulating voltage or current  wherein the variable actually regulated by the final control device is AC using discharge tubes or semiconductor devices as final control devices
    • G05F1/44—Regulating voltage or current  wherein the variable actually regulated by the final control device is AC using discharge tubes or semiconductor devices as final control devices semiconductor devices only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/12—Regulating voltage or current  wherein the variable actually regulated by the final control device is AC
    • G05F1/40—Regulating voltage or current  wherein the variable actually regulated by the final control device is AC using discharge tubes or semiconductor devices as final control devices
    • G05F1/44—Regulating voltage or current  wherein the variable actually regulated by the final control device is AC using discharge tubes or semiconductor devices as final control devices semiconductor devices only
    • G05F1/45—Regulating voltage or current  wherein the variable actually regulated by the final control device is AC using discharge tubes or semiconductor devices as final control devices semiconductor devices only being controlled rectifiers in series with the load
    • G05F1/452—Regulating voltage or current  wherein the variable actually regulated by the final control device is AC using discharge tubes or semiconductor devices as final control devices semiconductor devices only being controlled rectifiers in series with the load with pulse-burst modulation control

Definitions

  • the invention relates to a method for regulating amplitude fluctuations of two, 90 ° el. Phase-shifted, alternating, periodic signals of any phase sequence, each having an amplitude maximum in the middle per half-cycle, and a circuit arrangement for carrying out the method.
  • sensor elements When detecting distances, speeds or angles of rotation, sensor elements are generally used which supply two, alternating, periodic signals which are 90 ° el. Such signals can be sinusoidal, trapezoidal or triangular. The amplitudes of such signals are subject to sample variations and are generally a function of the temperature or the frequency or the supply voltage or of the line length or a combination of the listed parameters. As a result, the positive and negative amplitude values fluctuate evenly. However, it can also happen that the positive and negative amplitudes fluctuate to different extents. In such a case, the signal values are superimposed with an offset voltage, which is also a function of the temperature or the supply voltage. Due to these amplitude fluctuations of sensor elements, the detected distances, speeds or angles of rotation can be faulty when evaluating these signal profiles.
  • US Pat. No. 3,705,980 describes a method for regulating amplitude fluctuations of two phase-shifted, 90 ° el. alternating, periodic signals of any phase sequence. These sinusoidal signals modulate a carrier signal, the two amplitude-modulated carrier signals generated being combined to form a sum signal. This sum signal is rectified and fed to a subtractor, which subtracts a reference signal from the rectified sum signal. A formed error signal is present at the output of this subtractor, which changes the amplitude of the carrier signal. If there are no amplitude fluctuations in the two sinusoidal signals, the error signal is zero. If amplitude fluctuations occur, the amplitude of the carrier signal is changed by means of the generated error signal until the two amplitude-modulated and rectified carrier signals make the error signal zero again.
  • the invention is based on the object of specifying a method and a circuit arrangement for regulating amplitude fluctuations between phase-shifted, alternating, periodic signals which are 90 ° el. And which is independent of the frequency of the signals to be controlled.
  • the signals after passing through associated, the signal amplitude correcting actuators are converted into square wave signals, from which clock pulses are generated by a logic circuit depending on the phase sequence of the signals on the positive or negative edge of the square wave signals that the positive or negative amplitude profile of the amplitude-corrected signals present on the output side of the actuators is monitored for falling below or falling below an upper comparison voltage and that if the clock pulses fall below or exceed a device for changing a predetermined manipulated variable of the respective actuator is activated with the aim , the amplitude of the amplitude corrected signals in the Range between the upper and lower reference voltage.
  • This method ensures that regardless of the phase sequence, even when the phase sequence changes during operation, a clock signal is generated for the device for changing a predetermined manipulated variable of an actuator, whereby the amplitude of the signal is increased or decreased as soon as it is activated Amplitude lies outside a predetermined comparison value range.
  • These clock pulses are generated at the maximum amplitude of the signals.
  • a clock signal is generated at most within one period of the signals if the signals each have an amplitude maximum, as a result of which a one-sided amplitude influence is avoided when the phase sequence changes constantly.
  • the range of comparison values is determined by determining the values of the comparison voltages. The polarity of the comparison voltage determines whether the positive or negative amplitude profile of the signals is monitored in each case.
  • the signals are converted by means of actuators (8, 10) into amplitude-corrected signals (u A1 , u A2 ), each of which is supplied on the one hand to a device for monitoring the positive or negative amplitude profile and on the other hand to a comparator,
  • the outputs of the comparators are each linked to a logic circuit, the manipulated variable of each actuator can be set by means of a device for changing a predetermined manipulated variable, and the two outputs of each device for monitoring the positive or negative amplitude profile of the signal and an output of the logic circuit are each included the device for changing a predetermined gain value.
  • circuit arrangement it is possible to regulate the amplitude fluctuations of two, phase-shifting, alternating, periodic signals of any phase sequence, each phase sequence having an amplitude maximum in the middle of each half-period. Amplitude control is possible even at low signal frequencies.
  • the structure of the circuit arrangement can be easily constructed using circuit elements that are known in some cases.
  • the alternating, periodic signals which are phase-shifted by 90 °, are each fed to a first and a second circuit arrangement according to the invention for carrying out the method according to the invention.
  • the comparison values of the devices for monitoring the amplitude profile are predetermined such that the positive amplitude profile is monitored for this signal by means of the first circuit arrangement and the negative amplitude profile is monitored using the second circuit arrangement.
  • the first and the second circuit arrangement each generate a manipulated variable for the respective actuator.
  • These manipulated variable values are also fed to a differential element with a downstream digital-to-analog converter.
  • the output of the digital-to-analog converter is connected to a voltage divider, the output of which is linked to the two circuit arrangements via an integrator.
  • the offset voltage is thus possible by doubling the circuit arrangement with corresponding comparison values and by means of a simple processing circuit connected downstream to compensate one signal from each of the two signals which are phase-shifted by 90 °.
  • This circuit arrangement for compensating the offset voltage of a signal is recommended if there are high offset values which change greatly in the operating temperature range.
  • FIG. 1 shows a circuit arrangement 2 for carrying out the method according to the invention for regulating amplitude fluctuations of two phase sequences of any phase-shifting, alternating, periodic signals u S1 and u S2 , each of which has an amplitude maximum in the middle per half-cycle.
  • the two signals u S1 and u S2 can be triangular, trapezoidal or sinusoidal and generated by an encoder.
  • Sinusoidal signals u S1 and u S2 with changing phase sequence are shown in FIG. 3 in a diagram over the angular frequency ⁇ t.
  • the circuit arrangement 2 consists of two channels 4 and 6, each of which a signal u S1 and u S2 are supplied.
  • the channel 4 or 6 consists of an actuator 8 or 10, a device 12 or 14 for monitoring the amplitude profile of the signal u S1 or u S2 , a comparator 16 or 18, a device 20 or 22 for changing a predetermined manipulated variable of the actuator 8 or 10 and a logic circuit 24 or 26.
  • the output of the actuator 8 or 10 is linked on the one hand to the device 12 or 14 and on the other hand to the comparator 16 or 18.
  • the output of the comparator 16 or 18 is either connected via an inverter 25 or 27 or directly to the logic circuit 24 or 26, the output of which is linked to the device 20 or 22.
  • a programmable amplifier known for example from "der Elektroniker", 1986, M.9, pages 58 to 62, is provided as actuator 8 or 10 and contains an operational amplifier 28 or 30, the output of which is via a multiplying digital-analog Converter 32 or 34 is fed back to its inverting input.
  • the signal u S1 or u S2 is present at the inverting input and an offset voltage u Off1 or u Off2 can be supplied, the generation of this offset voltage u Off1 ... or u Off2 is explained in more detail with reference to FIG. 14.
  • the multiplying digital-to-analog converter 32 or 34 is a manipulated variable value DV1+ / DV1 ⁇ rang. DV2+ / DV2 ⁇ can be fed from the device 20 or 22.
  • this generated manipulated variable value DV1+ / DV1 ⁇ or DV2+ / DV2 ⁇ can be fed to a data output 36 or 38.
  • This manipulated variable value DV1+ / DV1 ⁇ or DV2+ / DV2 ⁇ can be an 8-bit or 12-bit or 16-bit digital word.
  • the word length depends on the device 20 or 22 for changing a predetermined manipulated variable value of the programmable amplifier 8 or 10 used as an actuator. The increase in the word length also changes the resolution of the comparison value range of the device 12 or 14 for monitoring the amplitude curve.
  • the digital word DV1+ or DV2+ identifies an amplification value which is generated as a function of the monitoring of the positive amplitude profile of the signal u S1 or u S2 , the digital word DV1 ⁇ or DV2 ⁇ identifying an amplification value which is dependent on the monitoring of the negative amplitude profile of the signal u S1 or u S2 is generated.
  • the signal u S1 or u S2 is amplified and fed on the one hand to the comparator 16 or 18 and on the other hand to the device 12 or 14 for amplitude monitoring.
  • the amplitude-corrected signal u AS1 or u AS2 present at the output of the programmable amplifier 8 or 10 is fed to an output 40 or 42 of the circuit arrangement 2.
  • the comparator 16 or 18 converts the amplitude-corrected signal u AS1 or u AS2 into a square-wave signal u RS1 or u RS2 , which is shown in FIG. 4 or 5 in a diagram over the angular frequency ⁇ t.
  • a commercially available component can also be used as the programmable amplifier 8 or 10.
  • a window comparator can be provided as device 12 or 14 for amplitude monitoring.
  • a window comparator is known from Tietze / Schenk "Semiconductor Circuit Technology", 6th edition, page 180.
  • the window comparator compares the signal u AS1 and u AS2 with the reference voltages ⁇ US+ and ⁇ US ⁇ , the define a comparison range.
  • ⁇ US+ denotes an upper and ⁇ US ⁇ a lower comparison voltage.
  • the signs of the comparison voltages + US+, + US ⁇ , -US+ and -US ⁇ indicate whether the positive or the negative amplitude profile of the signal u AS1 or u AS2 is monitored.
  • the following two signals are present at the output of the window comparator 12 or 14: Signal U / D and signal EN .
  • the up-down counter is activated and the signal U / D determines whether the counter increments or decrements at the next clock pulse u CL1 or u CL2 generated by the logic circuit 24 or 26.
  • the second signal generated by the window comparator U / D indicates whether the maximum amplitude of the signal u AS1 or u AS2 is above the upper comparison voltage ⁇ US+ or below the lower comparison voltage ⁇ US ⁇ .
  • the up-down counter 20 or 22 can be set to a predetermined counter reading by means of a digital word DVA1 or DVA2, which digital word DVA1 or DVA2 can be provided by a microprocessor of a higher-level controller.
  • FIG. 2 shows the internal structure of logic circuits 24 and 26.
  • Logic circuits 24 and 26 contain three AND gates 44, 48 and 52 or 46, 50 and 54, an OR gate 56 and 58 and an EXOR gate 60 or 62.
  • the outputs of the three AND gates 44, 48 and 52 or 46, 50 and 54 are linked to the inputs of the OR gate 56 or 58, which is followed by the EXOR gate 60 to 62 .
  • the output signal u01 or u02 of the OR gate 56 or 58 shown in a diagram over the angular frequency ⁇ t in Figure 9, is fed back to a first input of the first and third AND gates 44 and 52nd or 46 and 54, the second input of the first AND gate 44 or 46 being supplied with the square wave signal u RS1 or u RS2 .
  • the square-wave signal u RS1 or u RS2 shown in a diagram over the angular frequency ⁇ t in FIG. 4 or 5, is fed to a second input with negation of the second AND gate 48 or 50, the first input of which is the square-wave signal u RS2 or u RS 1 is supplied.
  • the second input of the third AND gate 52 or 54 is supplied with the square wave signal u RS2 or u RS1 , which is also supplied to the second input of the EXOR gate 60 or 62.
  • the output signals u U11 , u U21 and u UG1 or u U21 , u U22 and u UG2 of the AND gates 44, 48 and 52 or 46, 50 and 54 are each shown in a diagram over the angular frequency ⁇ t in FIGS. 8, 7 and 6.
  • This construction of the logic circuit 24 or 26 generates a clock pulse u CL1 or u CL2 from the square-wave signals u RS1 and u RS2 , which, depending on the phase sequence of the square-wave signals u RS1 and u RS2, on the positive or negative edge of the square-wave signal u RS2 or u RS1 is generated.
  • This ensures that regardless of the phase sequence of the signals u S1 or u S2 , even when the phase sequence changes during operation, characterized by the points P1 or P2 in Figures 3 to 11, a clock pulse u CL1 or u CL2 at the maximum of the signal u S1 or u S2 and thus of course also in the active area of the up-down counter.
  • the third AND gate 52 or 54 of the logic circuit 24 or 26 does not directly contribute to the functionality of the logic circuit 24 or 26, but rather represents a so-called anti-hazard element.
  • This anti-hazard element is intended to prevent so-called Glitches that change multiple input signals almost simultaneously can arise, arise. Since the input signals u U11 and u U21 of the OR gate 56 and the input signals u U21 and u U22 of the OR gate 58, due to the gate delays of the first and second AND gates 44 and 48 or 46 and 50, almost change can change at the same time, the output signal u01 or u02 of the OR gate 56 or 58 can briefly change its state, which can cause malfunction of the subsequent EXOR gate 60 or 62.
  • the third AND gate 52 or 54 of the logic circuit 24 or 26 prevents such malfunction, caused by different gate delays of the AND gates 44 and 48 or 46 and 50, in that it generates a signal u UG1 or u UG2 , which holds the output signal u01 or u02 during the almost simultaneous status change of its input signals u U11 and u U21 or u U21 and u U22 to a high state.
  • FIGS. 10 and 11 show the clock pulses u CL1 and u CL2 generated by the logic circuits 24 and 26 in a diagram over the angular frequency ⁇ t.
  • the clock pulse u CL1 or u CL2 is generated during a period of the signal u S1 or u S2 , wherein the individual periods of the signal u S1 or u S2 are identified by T1, T2 and T3, exactly to the positive amplitude maximum.
  • No clock pulse u CL2 is generated during the second period T2-T1, since the phase sequence of the signals u S1 and u S2 changed at time P1 before the signal u S2 has reached its positive amplitude maximum.
  • the mode of operation of the circuit arrangement 2 according to FIG. 1 is explained in more detail with reference to FIG.
  • the signal U AS 1 and u AS2 is sampled, ie it is determined by means of the window comparator 12 and 14 where the positive amplitude or the positive amplitude maximum is located. It is found that the amplitude maximum is below the lower reference voltage + US ⁇ . This is the signal EN in the low state, whereby the counters 20 and 22 are activated and by the signal U / D is set to count up.
  • the logic circuits 24 and 26 At the time of the maximum amplitude of the signal u AS1 and the Signals u AS2 , the logic circuits 24 and 26 generate a clock pulse u CL1 and u CL2 , as a result of which the count of the active up-down counters 20 and 22, represented by an 8-digit or 16-digit bit combination, is 1 by the least significant bit (LSB) Bit is increased.
  • the value of the gain of the programmable amplifier 8 and 10 changes accordingly, as a result of which the value of the amplitude of the signals u AS1 and u AS2 increases.
  • the signals u AS1 and u AS2 are sampled one after the other and the value of the amplitude of the signals u As1 and u AS2 is changed accordingly depending on this result.
  • the window (+ US+) - (+ US ⁇ ) of the window comparator 12 or 14 has at least a width of two LSB, the amount of the window depending on the up-down counter 20 and 22 used.
  • FIG. 13 shows the signals u AS1 and u AS2 in a diagram over the angular frequency ⁇ t, the gain value of the programmable amplifier 8 and 10 being generated at the time of the negative amplitude maximum.
  • the comparative voltages -US+ and -US ⁇ are fed to the window comparators 12 and 14, respectively, whereby the window comparators 12 and 14+ can monitor the negative amplitude of the signal u AS1 and u AS2 .
  • FIG. 14 shows a circuit arrangement for regulating the offset voltage of the signal u S1 or u S2 .
  • the circuit arrangement consists of the circuit arrangement 2 and a circuit arrangement 2 ', the data outputs of which are fed to a differential element 64.
  • the output of the differential element 64 is linked via a digital-analog converter 66 to a voltage divider 68, the output of which is connected via an integrator 70 with an offset input of the circuit arrangement 2 and 2 'is linked.
  • the circuit arrangement 2 ' corresponds to the structure of the circuit arrangement 2. The difference between these two circuit arrangements 2 and 2' lies in the comparison voltages + US+, + US ⁇ , -US+ and -US ⁇ .
  • the window compensators 12 and 14 of the circuit arrangement 2 are supplied with the comparison voltages + US+ and + US ⁇ and the outputs of the comparators 16 and 18 are directly connected to the logic circuits 24 and 26 connected.
  • the corresponding window comparators of the circuit arrangement 2 ' are supplied with the reference voltages -US+ and -US ⁇ and the outputs of the corresponding comparators are linked to the logic circuits via inverters. For example, since the signal u S1 has an offset voltage U Off1 , the data output of the first channel of the circuit arrangement 2 and 2 ', at which a data word DV1 + or DV1 ⁇ is present, is connected to the differential element 64.
  • This difference element 64 forms the difference DV1 ⁇ - DV1+ or, if the signal u S2 has an offset voltage U Off2 , the difference DV2 ⁇ - DV2+.
  • the difference formed in digital form which corresponds to twice the offset value of the signal u S1 or u S2 , is converted into an analog value.
  • the voltage divider 68 gives the offset voltage value U Off1 or U Off2 of the signal u S1 or u S2 , which is fed via the integrator 70 to an offset input of the programmable amplifier 8 or 10 of the circuit arrangement 2 and a corresponding programmable amplifier of the circuit arrangement 2 ' becomes.
  • the amplifiers then form the difference u S1 -U Off1 or u S2 -U Off2 .
  • This circuit arrangement makes it possible to compensate for high offset voltage values which change significantly as a result of operating temperatures.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Networks Using Active Elements (AREA)
  • Manipulation Of Pulses (AREA)
EP89122722A 1988-12-21 1989-12-08 Verfahren zur Ausregelung von Amplitudenschwankungen zweier um 90o el. phasenverschobener, alternierender, periodischer Signale beliebiger Phasenfolge und Schaltungsanordnung zur Durchführung des Verfahrens Expired - Lifetime EP0374641B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3843108A DE3843108C1 (enrdf_load_stackoverflow) 1988-12-21 1988-12-21
DE3843108 1988-12-21

Publications (3)

Publication Number Publication Date
EP0374641A2 EP0374641A2 (de) 1990-06-27
EP0374641A3 EP0374641A3 (de) 1991-09-18
EP0374641B1 true EP0374641B1 (de) 1995-02-15

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EP89122722A Expired - Lifetime EP0374641B1 (de) 1988-12-21 1989-12-08 Verfahren zur Ausregelung von Amplitudenschwankungen zweier um 90o el. phasenverschobener, alternierender, periodischer Signale beliebiger Phasenfolge und Schaltungsanordnung zur Durchführung des Verfahrens

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EP (1) EP0374641B1 (enrdf_load_stackoverflow)
AT (1) ATE118626T1 (enrdf_load_stackoverflow)
DE (2) DE3843108C1 (enrdf_load_stackoverflow)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0489936B1 (de) * 1990-12-03 1995-08-02 Siemens Aktiengesellschaft Verfahren zum Detektieren einer Amplituden- und Offset-Abweichung zweier etwa 90 elektrisch versetzter siusförmiger Signale sowie Schaltung zur Durchführung dieses Verfahrens und Verwendung dieses Verfahrens für einen Regler
DE59101802D1 (de) * 1991-01-21 1994-07-07 Siemens Ag Verfahren zum Überwachen der Ausgangssignale einer Gebereinrichtung.
DE59201670D1 (de) * 1992-04-30 1995-04-20 Siemens Ag Einrichtung zum Erfassen der Signalamplitude der Erregerspannung eines Resolvers.
DE10056926A1 (de) 2000-11-20 2002-07-18 Optolab Licensing Gmbh Verfahren und Vorrichtung zur Konditionierung eines periodischen Analogsignals

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3705908A (en) * 1971-06-28 1972-12-12 Minnesota Mining & Mfg Process for preparing 2-formyl-2-lower alkyl 1,3-dithiolanes and 1,3-dithianes

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3378786A (en) * 1966-11-14 1968-04-16 Collins Radio Co Digitalized signal gain control circuit
US3464022A (en) * 1967-08-30 1969-08-26 Mandrel Industries Apparatus for controlling the gain of binary gain ranging amplifiers
US3705980A (en) * 1970-01-02 1972-12-12 Sperry Rand Corp Controlled magnitude repeater for synchro and resolver signals
JPH0746788B2 (ja) * 1985-11-05 1995-05-17 日本電気株式会社 自動線路等化器

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3705908A (en) * 1971-06-28 1972-12-12 Minnesota Mining & Mfg Process for preparing 2-formyl-2-lower alkyl 1,3-dithiolanes and 1,3-dithianes

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Der Elektroniker, M.9, 1986 *

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Publication number Publication date
DE58909003D1 (de) 1995-03-23
DE3843108C1 (enrdf_load_stackoverflow) 1990-02-15
EP0374641A3 (de) 1991-09-18
ATE118626T1 (de) 1995-03-15
EP0374641A2 (de) 1990-06-27

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