EP0374641B1 - Method to suppress amplitude variations of two alternating, periodic signals in phase quadrature with a random phase sequence, and circuit arrangement to carry out the method - Google Patents

Abstract

The invention relates to a method of suppressing amplitude variations of two electrical signals (uS1, uS2) in phase quadrature and a circuit arrangement for carrying out the method. According to the invention, the positive or negative amplitude variation of the signals (uS1, uS2) is monitored for undershooting of a lower or overshooting of an upper reference voltage (+/-US- or +/-US+) in such a way that in the event of undershooting or overshooting a device (20, 22) for changing a prescribed manipulated variable of an actuator (8, 10) is activated, and the signals (uS1, uS2) are respectively converted into rectangular signals (uRS1,uRS2), from which clock pulses (uC11 or uC12) are generated by means of a logic circuit (24 or 26) depending upon the phase sequence of the signals (uS1, uS2) at the positive or negative flanks of the rectangular signals (uRS1, uRS2), which vary the prescribed gain as a function of the result of the amplitude monitoring by a prescribed value (LSB). This yields a method of suppressing amplitude variations of two electrical alternating, periodic signals (uS1, uS2) in phase quadrature with a random phase sequence, and a circuit arrangement for carrying out the method that operates independently of frequency. <IMAGE>

Description

Method for regulating amplitude fluctuations of two, 90 ° el. Phase-shifted, alternating, periodic signals of any phase sequence and circuit arrangement for carrying out the method

The invention relates to a method for regulating amplitude fluctuations of two, 90 ° el. Phase-shifted, alternating, periodic signals of any phase sequence, each having an amplitude maximum in the middle per half-cycle, and a circuit arrangement for carrying out the method.

When detecting distances, speeds or angles of rotation, sensor elements are generally used which supply two, alternating, periodic signals which are 90 ° el. Such signals can be sinusoidal, trapezoidal or triangular. The amplitudes of such signals are subject to sample variations and are generally a function of the temperature or the frequency or the supply voltage or of the line length or a combination of the listed parameters. As a result, the positive and negative amplitude values fluctuate evenly. However, it can also happen that the positive and negative amplitudes fluctuate to different extents. In such a case, the signal values are superimposed with an offset voltage, which is also a function of the temperature or the supply voltage. Due to these amplitude fluctuations of sensor elements, the detected distances, speeds or angles of rotation can be faulty when evaluating these signal profiles.

US Pat. No. 3,705,980 describes a method for regulating amplitude fluctuations of two phase-shifted, 90 ° el. alternating, periodic signals of any phase sequence are known. These sinusoidal signals modulate a carrier signal, the two amplitude-modulated carrier signals generated being combined to form a sum signal. This sum signal is rectified and fed to a subtractor, which subtracts a reference signal from the rectified sum signal. A formed error signal is present at the output of this subtractor, which changes the amplitude of the carrier signal. If there are no amplitude fluctuations in the two sinusoidal signals, the error signal is zero. If amplitude fluctuations occur, the amplitude of the carrier signal is changed by means of the generated error signal until the two amplitude-modulated and rectified carrier signals make the error signal zero again.

The invention is based on the object of specifying a method and a circuit arrangement for regulating amplitude fluctuations between phase-shifted, alternating, periodic signals which are 90 ° el. And which is independent of the frequency of the signals to be controlled.

This object is achieved in that the signals after passing through associated, the signal amplitude correcting actuators are converted into square wave signals, from which clock pulses are generated by a logic circuit depending on the phase sequence of the signals on the positive or negative edge of the square wave signals that the positive or negative amplitude profile of the amplitude-corrected signals present on the output side of the actuators is monitored for falling below or falling below an upper comparison voltage and that if the clock pulses fall below or exceed a device for changing a predetermined manipulated variable of the respective actuator is activated with the aim , the amplitude of the amplitude corrected signals in the Range between the upper and lower reference voltage.

This method ensures that regardless of the phase sequence, even when the phase sequence changes during operation, a clock signal is generated for the device for changing a predetermined manipulated variable of an actuator, whereby the amplitude of the signal is increased or decreased as soon as it is activated Amplitude lies outside a predetermined comparison value range. These clock pulses are generated at the maximum amplitude of the signals. In addition, a clock signal is generated at most within one period of the signals if the signals each have an amplitude maximum, as a result of which a one-sided amplitude influence is avoided when the phase sequence changes constantly. The range of comparison values is determined by determining the values of the comparison voltages. The polarity of the comparison voltage determines whether the positive or negative amplitude profile of the signals is monitored in each case. With this method, you can measure the amplitude fluctuations of two by 90 ° el. phase-shifting, alternating, periodic signals of any phase sequence, each of which has an amplitude maximum in the middle of each half-period, regardless of their frequency, so that subsequent analysis of these corrected signals cannot result in errors.

In a circuit arrangement according to the invention for carrying out the method, the signals are converted by means of actuators (8, 10) into amplitude-corrected signals (u _A1 , u _A2 ), each of which is supplied on the one hand to a device for monitoring the positive or negative amplitude profile and on the other hand to a comparator, The outputs of the comparators are each linked to a logic circuit, the manipulated variable of each actuator can be set by means of a device for changing a predetermined manipulated variable, and the two outputs of each device for monitoring the positive or negative amplitude profile of the signal and an output of the logic circuit are each included the device for changing a predetermined gain value.

Advantageous embodiments of the logic circuits, the device for monitoring the amplitude profile and the device for changing a predetermined gain value can be found in claims 4 to 7.

With this circuit arrangement, it is possible to regulate the amplitude fluctuations of two, phase-shifting, alternating, periodic signals of any phase sequence, each phase sequence having an amplitude maximum in the middle of each half-period. Amplitude control is possible even at low signal frequencies. The structure of the circuit arrangement can be easily constructed using circuit elements that are known in some cases.

In a further advantageous circuit arrangement, the alternating, periodic signals, which are phase-shifted by 90 °, are each fed to a first and a second circuit arrangement according to the invention for carrying out the method according to the invention. For a signal of the two signals, the comparison values of the devices for monitoring the amplitude profile are predetermined such that the positive amplitude profile is monitored for this signal by means of the first circuit arrangement and the negative amplitude profile is monitored using the second circuit arrangement. Depending on the positive and negative amplitude fluctuations of a signal, the first and the second circuit arrangement each generate a manipulated variable for the respective actuator. These manipulated variable values are also fed to a differential element with a downstream digital-to-analog converter. The output of the digital-to-analog converter is connected to a voltage divider, the output of which is linked to the two circuit arrangements via an integrator.

As soon as the positive amplitude curve does not correspond in magnitude to the negative amplitude curve in the case of a signal of the two signals which are phase-shifted by 90 °, different manipulated variable values are generated for the respective actuator in the two circuit arrangements. As a result, a value appears at the output of the differential element that corresponds to twice the offset value of the signal. After the analog conversion and halving by means of the voltage divider, the offset voltage value of a signal is obtained, which is integrated and fed to the actuator of the first and second circuit arrangement, whereby the offset voltage value is subtracted from the actual value of a signal.

The offset voltage is thus possible by doubling the circuit arrangement with corresponding comparison values and by means of a simple processing circuit connected downstream to compensate one signal from each of the two signals which are phase-shifted by 90 °. This circuit arrangement for compensating the offset voltage of a signal is recommended if there are high offset values which change greatly in the operating temperature range.

Figur 1

zeigt eine Schaltungsanordnung zur Durchführung des erfindungsgemäßen Verfahrens, in

Figur 2

ist eine Ausführungsform der Logikschaltungen der beiden Kanäle der Schaltungsanordnung nach Figur 1 näher dargestellt, in

Figur 3

sind zwei um 90° el. phasenverschobene Signale beliebiger Phasenfolge in einem Diagramm über der Kreisfrequenz ωt dargestellt, in den

Figuren 4 und 5

ist jeweils ein Rechtecksignal der phasenverschobenen Signale nach Figur 3 in einem Diagramm über der Kreisfrequenz ωt veranschaulicht, die

Figuren 6 bis 9

zeigen Ausgangssignale der einzelnen Gatter der Logikschaltungen nach Figur 2 jeweils in einem Diagramm über der Kreisfrequenz ωt, in den

Figuren 10 und 11

ist jeweils ein Taktimpulse in einem Diagramm über der Kreisfrequenz ωt dargestellt, die

Figuren 12 und 13

zeigen jeweils die amplitudengeregelten phasenverschobenen Signale in einem Diagramm über der Kreisfrequenz ωt, wobei einmal der positive und einmal der negative Amplitudenverlauf geregelt wird, und in

Figur 14

ist eine Schaltungsanordnung zur Kompensation einer Offsetspannung eines Signals veranschaulicht.

To further explain the invention, reference is made to the drawing, in which an exemplary embodiment of the circuit arrangement for carrying out the method for regulating amplitude fluctuations of two signals which are 90 ° el. Phase-shifted is schematically illustrated.

Figure 1

shows a circuit arrangement for performing the method according to the invention, in

Figure 2

is an embodiment of the logic circuits of the two channels of the circuit arrangement shown in Figure 1, in

Figure 3

are shown by 90 ° el. phase-shifted signals of any phase sequence in a diagram over the angular frequency ωt, in the

Figures 4 and 5

a rectangular signal of the phase-shifted signals according to FIG. 3 is illustrated in a diagram over the angular frequency ωt

Figures 6 to 9

show output signals of the individual gates of the logic circuits according to Figure 2 each in a diagram over the angular frequency ωt, in the

Figures 10 and 11

a clock pulse is shown in a diagram over the angular frequency ωt, the

Figures 12 and 13

each show the amplitude-controlled phase-shifted signals in a diagram over the angular frequency ωt, the positive and the negative amplitude profile being regulated once, and in

Figure 14

a circuit arrangement for compensating an offset voltage of a signal is illustrated.

1 shows a circuit arrangement 2 for carrying out the method according to the invention for regulating amplitude fluctuations of two phase sequences of any phase-shifting, alternating, periodic signals u _S1 and u _S2 , each of which has an amplitude maximum in the middle per half-cycle. The two signals u _S1 and u _S2 can be triangular, trapezoidal or sinusoidal and generated by an encoder. Sinusoidal signals u _S1 and u _S2 with changing phase sequence are shown in FIG. 3 in a diagram over the angular frequency ωt. The circuit arrangement 2 consists of two channels 4 and 6, each of which a signal u _S1 and u _{S2 are} supplied.

The channel 4 or 6 consists of an actuator 8 or 10, a device 12 or 14 for monitoring the amplitude profile of the signal u _S1 or u _S2 , a comparator 16 or 18, a device 20 or 22 for changing a predetermined manipulated variable of the actuator 8 or 10 and a logic circuit 24 or 26. The output of the actuator 8 or 10 is linked on the one hand to the device 12 or 14 and on the other hand to the comparator 16 or 18. The output of the comparator 16 or 18 is either connected via an inverter 25 or 27 or directly to the logic circuit 24 or 26, the output of which is linked to the device 20 or 22.

A programmable amplifier, known for example from "der Elektroniker", 1986, M.9, pages 58 to 62, is provided as actuator 8 or 10 and contains an operational amplifier 28 or 30, the output of which is via a multiplying digital-analog Converter 32 or 34 is fed back to its inverting input. The signal u _S1 or u _{S2 is present} at the inverting input and an offset voltage u _Off1 or u _{Off2 can be} supplied, the generation of this offset voltage u _Off1 ... or u _Off2 is explained in more detail with reference to FIG. 14. The multiplying digital-to-analog converter 32 or 34 is a manipulated variable value DV1₊ / DV1₋bzw. DV2₊ / DV2₋ can be fed from the device 20 or 22. In addition, this generated manipulated variable value DV1₊ / DV1₋ or DV2₊ / DV2₋ can be fed to a data output 36 or 38. This manipulated variable value DV1₊ / DV1₋ or DV2₊ / DV2₋ can be an 8-bit or 12-bit or 16-bit digital word. The word length depends on the device 20 or 22 for changing a predetermined manipulated variable value of the programmable amplifier 8 or 10 used as an actuator. The increase in the word length also changes the resolution of the comparison value range of the device 12 or 14 for monitoring the amplitude curve. The digital word DV1₊ or DV2₊ identifies an amplification value which is generated as a function of the monitoring of the positive amplitude profile of the signal u _S1 or u _S2 , the digital word DV1₋ or DV2₋ identifying an amplification value which is dependent on the monitoring of the negative amplitude profile of the signal u _S1 or u _{S2 is} generated. Depending on this value, the signal u _S1 or u _{S2 is} amplified and fed on the one hand to the comparator 16 or 18 and on the other hand to the device 12 or 14 for amplitude monitoring. Likewise, the amplitude-corrected signal u _AS1 or u _AS2 present at the output of the programmable amplifier 8 or 10 is fed to an output 40 or 42 of the circuit arrangement 2. The comparator 16 or 18 converts the amplitude-corrected signal u _AS1 or u _AS2 into a square-wave signal u _RS1 or u _RS2 , which is shown in FIG. 4 or 5 in a diagram over the angular frequency ωt. A commercially available component can also be used as the programmable amplifier 8 or 10.

A window comparator can be provided as device 12 or 14 for amplitude monitoring. A window comparator is known from Tietze / Schenk "Semiconductor Circuit Technology", 6th edition, page 180. The window comparator compares the signal u _AS1 and u _AS2 with the reference voltages ∓US₊ and ∓US₋, the define a comparison range. ∓US₊ denotes an upper and ∓US₋ a lower comparison voltage. The signs of the comparison voltages + US₊, + US₋, -US₊ and -US₋ indicate whether the positive or the negative amplitude profile of the signal u _AS1 or u _{AS2 is} monitored. The following two signals are present at the output of the window comparator 12 or 14: Signal U / D and signal EN . As long as the signal EN is high, the amplitude maximum of the signal u _{AS1 is} within the window predetermined by the comparison voltages ∓ US₊ and ∓US₋, whereby the device 20 or 22, for example an up-down counter, remains blocked. Once the signal EN becomes low, an indication that the maximum amplitude of the signal u _AS ₁ or u _{AS2 has moved} out of the predetermined window, the up-down counter is activated and the signal U / D determines whether the counter increments or decrements at the next clock pulse u _CL1 or u _CL2 generated by the logic circuit 24 or 26. The second signal generated by the window comparator U / D indicates whether the maximum amplitude of the signal u _AS1 or u _{AS2 is} above the upper comparison voltage ∓US₊ or below the lower comparison voltage ∓US₋. The up-down counter 20 or 22 can be set to a predetermined counter reading by means of a digital word DVA₁ or DVA₂, which digital word DVA₁ or DVA₂ can be provided by a microprocessor of a higher-level controller.

FIG. 2 shows the internal structure of logic circuits 24 and 26. Logic circuits 24 and 26 contain three AND gates 44, 48 and 52 or 46, 50 and 54, an OR gate 56 and 58 and an EXOR gate 60 or 62. The outputs of the three AND gates 44, 48 and 52 or 46, 50 and 54 are linked to the inputs of the OR gate 56 or 58, which is followed by the EXOR gate 60 to 62 . The output signal u₀₁ or u₀₂ of the OR gate 56 or 58, shown in a diagram over the angular frequency ωt in Figure 9, is fed back to a first input of the first and third AND gates 44 and 52nd or 46 and 54, the second input of the first AND gate 44 or 46 being supplied with the square wave signal u _RS1 or u _RS2 . In addition, the square-wave signal u _RS1 or u _RS2 , shown in a diagram over the angular frequency ωt in FIG. 4 or 5, is fed to a second input with negation of the second AND gate 48 or 50, the first input of which is the square-wave signal u _RS2 or u _RS ₁ is supplied. The second input of the third AND gate 52 or 54 is supplied with the square wave signal u _RS2 or u _RS1 , which is also supplied to the second input of the EXOR gate 60 or 62. The output _signals u _U11 , u _U21 and u _UG1 or u _U21 , u _U22 and u _{UG2 of} the AND gates 44, 48 and 52 or 46, 50 and 54 are each shown in a diagram over the angular frequency ωt in FIGS. 8, 7 and 6. This construction of the logic circuit 24 or 26 generates a clock pulse u _CL1 or u _CL2 from the square-wave _signals u _RS1 and u _RS2 , which, depending on the phase sequence of the square-wave _signals u _RS1 and u _RS2, on the positive or negative edge of the square-wave signal u _RS2 or u _{RS1 is} generated. This ensures that regardless of the phase sequence of the signals u _S1 or u _S2 , even when the phase sequence changes during operation, characterized by the points P₁ or P₂ in Figures 3 to 11, a clock pulse u _CL1 or u _CL2 at the maximum of the signal u _S1 or u _S2 and thus of course also in the active area of the up-down counter. For the correct functioning of the amplitude control, it is important that with a constant change of the phase sequence only one clock pulse u _CL1 or u _{CL2 is} generated within a period of the signal u _S1 or u _S2 , whereby there can be no one-sided amplitude influence. This ensures that the amplitudes are _sampled alternately for both signals u _S1 and u _S2 .

The third AND gate 52 or 54 of the logic circuit 24 or 26 does not directly contribute to the functionality of the logic circuit 24 or 26, but rather represents a so-called anti-hazard element. This anti-hazard element is intended to prevent so-called Glitches that change multiple input signals almost simultaneously can arise, arise. Since the input signals u _U11 and u _{U21 of} the OR gate 56 and the input signals u _U21 and u _{U22 of} the OR gate 58, due to the gate delays of the first and second AND gates 44 and 48 or 46 and 50, almost change can change at the same time, the output signal u₀₁ or u₀₂ of the OR gate 56 or 58 can briefly change its state, which can cause malfunction of the subsequent EXOR gate 60 or 62. The third AND gate 52 or 54 of the logic circuit 24 or 26 prevents such malfunction, caused by different gate delays of the AND gates 44 and 48 or 46 and 50, in that it generates a signal u _UG1 or u _UG2 , which holds the output signal u₀₁ or u₀₂ during the almost simultaneous status change of its input signals u _U11 and u _U21 or u _U21 and u _U22 to a high state.

FIGS. 10 and 11 show the clock pulses u _CL1 and u _CL2 generated by the logic circuits 24 and 26 in a diagram over the angular frequency ωt. The clock pulse u _CL1 or u _CL2 is generated during a period of the signal u _S1 or u _S2 , wherein the individual periods of the signal u _S1 or u _{S2 are identified} by T1, T2 and T3, exactly to the positive amplitude maximum. No clock pulse u _{CL2 is} generated during the second period T2-T1, since the phase sequence of the signals u _S1 and u _{S2 changed} at time P1 before the signal u _{S2 has reached} its positive amplitude maximum.

The mode of operation of the circuit arrangement 2 according to FIG. 1 is explained in more detail with reference to FIG. During the first period, the signal U _AS ₁ and u _{AS2 is} sampled, ie it is determined by means of the window comparator 12 and 14 where the positive amplitude or the positive amplitude maximum is located. It is found that the amplitude maximum is below the lower reference voltage + US₋. This is the signal EN in the low state, whereby the counters 20 and 22 are activated and by the signal U / D is set to count up. At the time of the maximum amplitude of the signal u _AS1 and the Signals u _AS2 , the logic circuits 24 and 26 generate a clock pulse u _CL1 and u _CL2 , as a result of which the count of the active up-down counters 20 and 22, represented by an 8-digit or 16-digit bit combination, is 1 by the least significant bit (LSB) Bit is increased. As a result, the value of the gain of the programmable amplifier 8 and 10 changes accordingly, as a result of which the value of the amplitude of the signals u _AS1 and u _AS2 increases. In each period, the signals u _AS1 and u _AS2 are sampled one after the other and the value of the amplitude of the signals u _As1 and u _AS2 is changed accordingly depending on this result. The window (+ US₊) - (+ US₋) of the window comparator 12 or 14 has at least a width of two LSB, the amount of the window depending on the up-down counter 20 and 22 used.

13 shows the signals u _AS1 and u _AS2 in a diagram over the angular frequency ωt, the gain value of the programmable amplifier 8 and 10 being generated at the time of the negative amplitude maximum. For this purpose, the comparative voltages -US₊ and -US₋ are fed to the window comparators 12 and 14, respectively, whereby the window comparators 12 and 14⁺ can monitor the negative amplitude of the signal u _AS1 and u _AS2 .

This also _applies to the negative amplitude maxima of the signals u _AS1 and u _AS2 clock pulses u _CL1 and u _{CL2 are} generated, the outputs of the comparators 16 and 18 are each connected to the logic circuit 24 and 26 via an inverter 25 and 27.

FIG. 14 shows a circuit arrangement for regulating the offset voltage of the signal u _S1 or u _S2 . The circuit arrangement consists of the circuit arrangement 2 and a circuit arrangement 2 ', the data outputs of which are fed to a differential element 64. The output of the differential element 64 is linked via a digital-analog converter 66 to a voltage divider 68, the output of which is connected via an integrator 70 with an offset input of the circuit arrangement 2 and 2 'is linked. The circuit arrangement 2 'corresponds to the structure of the circuit arrangement 2. The difference between these two circuit arrangements 2 and 2' lies in the comparison voltages + US₊, + US₋, -US₊ and -US₋. If, for example, the signal u _{S1 is provided} with an offset voltage U _Off1 , the window _compensators 12 and 14 of the circuit arrangement 2 are supplied with the comparison voltages + US₊ and + US₋ and the outputs of the comparators 16 and 18 are directly connected to the logic circuits 24 and 26 connected. The corresponding window comparators of the circuit arrangement 2 'are supplied with the reference voltages -US₊ and -US₋ and the outputs of the corresponding comparators are linked to the logic circuits via inverters. For example, since the signal u _S1 has an offset voltage U _Off1 , the data output of the first channel of the circuit arrangement 2 and 2 ', at which a data word DV1 + or DV1₋ is present, is connected to the differential element 64. This difference element 64 forms the difference DV1₋ - DV1₊ or, if the signal u _S2 has an offset voltage U _Off2 , the difference DV2₋ - DV2₊. The difference formed in digital form, which corresponds to twice the offset value of the signal u _S1 or u _S2 , is converted into an analog value. The voltage divider 68 gives the offset voltage _value U _Off1 or U _{Off2 of} the signal u _S1 or u _S2 , which is fed via the integrator 70 to an offset input of the programmable amplifier 8 or 10 of the circuit arrangement 2 and a corresponding programmable amplifier of the circuit arrangement 2 ' becomes. The amplifiers then form the difference u _{S1 -U Off1} or u _{S2 -U Off2} . This circuit arrangement makes it possible to compensate for high offset voltage values which change significantly as a result of operating temperatures.

Claims (8)

1. Method for correcting amplitude variations of two alternating, periodic signals (u_S1, u_S2) in quadrature with a random phase sequence, each of which has per half period centrally an amplitude maximum, characterized in that the signals (u_S1, u_S2), after passing through appertaining actuators (8, 10) correcting the signal amplitude, are in each case converted into rectangular signals (u_RS1, u_RS2), from which, by means of a logic circuit (24 or 26), clock pulses (u_CL1 or u_CL2) are in each case generated according to the phase sequence of the signals (u_S1, u_S2) at the positive or negative edge of the rectangular signals (u_RS1, u_RS2), in that the positive or negative amplitude characteristic of the amplitude-corrected signals (u_AS1, u_AS2) applied on the output side of the actuators (8, 19) is monitored for falling short of a lower reference voltage (±US₋) or the exceeding of an upper reference voltage (±US₊) and in that upon the falling short or the exceeding a device (20, 22) for changing a predetermined correcting variable of the respective actuator (8, 10) is activated by means of the clock pulses (u_CL1 or u_CL2) with the aim of returning the amplitudes of the amplitude-corrected signals (u_AS1, U_AS2) into the region between the upper and lower reference voltage (±US₋ or ±US₊).
2. Circuit arrangement for carrying out the method according to claim 1, having a circuit arrangement for correcting amplitude variations of two alternating, periodic signals (u_S1, u_S2) in quadrature, each of which has per half period centrally an amplitude maximum, characterized in that the signals (u_S1, u_S2) are converted by means of actuators (8, 11) into amplitude-corrected signals (u_AS1, u_AS2) which are each supplied on the one hand to a device (12, 14) for monitoring the positive or negative amplitude characteristic and on the other hand to a comparator (16, 18), with the outputs of the comparators (16, 18) being linked to a logic circuit (24, 26), in that the correcting variable of each actuator (8, 10) can be adjusted by means of a device (20, 22) for changing a predetermined correcting variable and in that the two outputs of each device (12, 14) for monitoring the positive or negative amplitude characteristic of the signal (U_AS1 or U_AS2) and an output of the logic circuit (24, 26) are in each case linked to a device (20, 22) for changing a predetermined correcting variable.
3. Circuit arrangement according to claim 2 having a second circuit arrangement (2′) for correcting amplitude variations of two alternating, periodic signals (u_S1, u_S2) in quadrature, each of which has per half period centrally an amplitude maximum, with the amplitude-corrected signals (u_AS1, U_AS2) in each case being supplied on the one hand to a device for monitoring the negative or the positive amplitude characteristic and on the other hand to a comparator, the outputs of which are linked to a logic circuit, and with the correcting variable of each actuator being adjustable by means of a device for changing a predetermined correcting variable, the inputs of which are connected to the outputs of the device for monitoring the negative or positive amplitude characteristic of the signals (u_S1, u_S2) and to an output of the logic circuit, characterized in that to control the offset voltage (u_off1, U_off2) of the signals (u_S1, u_S2) the positive correcting variable value (DV1₊ or DV2₊) of the device (20 or 22) for changing a predetermined correcting variable of the first circuit arrangement (2) and the negative correcting variable value (DV1₋ or DV2₋) of the device of the second circuit arrangement (2′) for correcting amplitude variations are supplied to a differential element (64), the output of which is connected by way of a digital-to-analog converter (66) to a voltage divider (68), the output of which is connected by way of an integrator (70) to offset inputs of said circuit arrangement (2, 2′).
4. Circuit arrangement according to claim 2 or 3, characterized in that the logic circuit (24 or 26) contains three AND gates (44, 48, 50 or 46, 50, 54), the outputs of which are connected to an OR gate (56 or 58), the output of which is connected on one side to an EX.OR gate (60 or 62) and on the other side to the first and third AND gate (44, 52 or 46, 54), in that the first input of the logic circuit (24 or 26) is connected to an input of the first AND gate (44 or 46) and to an input with negation of the second AND gate (48 or 50) and in that the second input of the logic circuit (24 or 26) is connected to an input of the second AND gate (48 or 50), the third AND gate (50 or 52) and the EX.OR gate (60 or 62), with the output of the EX.OR gate (60 or 62) forming the output of the logic circuit (24 or 26).
5. Circuit arrangement according to claim 2 or 3, characterized in that in each case a window comparator is provided as device (12, 14) for monitoring the positive or negative amplitude characteristic, whereby the values of the reference voltages (US₊, US₋) can be positive or negative.
6. Circuit arrangement according to claim 2 or 3, characterized in that in each case an up-down counter is provided as device (20, 22) for changing a predetermined correcting variable.
7. Circuit arrangement according to claim 2 or 3, characterized in that in each case a programmable amplifier is provided as actuator (8, 10).
8. Circuit arrangement according to claim 3, characterized in that the positive and negative correcting variable value (DV1₊, DV1₋ or DV2₊, DV₋) of the signal (u_S1 or u_S2) can be supplied to a multiplexer, the output of which is linked by way of a digital-to-analog converter (66) to the voltage divider (68).

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