EP0282631A2 - Appareil de jeu de hasard avec payement de gain - Google Patents

Appareil de jeu de hasard avec payement de gain Download PDF

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Publication number
EP0282631A2
EP0282631A2 EP87113449A EP87113449A EP0282631A2 EP 0282631 A2 EP0282631 A2 EP 0282631A2 EP 87113449 A EP87113449 A EP 87113449A EP 87113449 A EP87113449 A EP 87113449A EP 0282631 A2 EP0282631 A2 EP 0282631A2
Authority
EP
European Patent Office
Prior art keywords
symbols
random
winning
probability
win
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP87113449A
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German (de)
English (en)
Other versions
EP0282631A3 (fr
Inventor
Hans Kloss
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bally Wulff Automaten GmbH
Original Assignee
Bally Wulff Automaten GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bally Wulff Automaten GmbH filed Critical Bally Wulff Automaten GmbH
Priority to AU83164/87A priority Critical patent/AU8316487A/en
Publication of EP0282631A2 publication Critical patent/EP0282631A2/fr
Publication of EP0282631A3 publication Critical patent/EP0282631A3/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F17/00—Coin-freed apparatus for hiring articles; Coin-freed facilities or services
    • G07F17/32—Coin-freed apparatus for hiring articles; Coin-freed facilities or services for games, toys, sports, or amusements
    • G07F17/326—Game play aspects of gaming systems
    • G07F17/3262—Player actions which determine the course of the game, e.g. selecting a prize to be won, outcome to be achieved, game to be played
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F17/00—Coin-freed apparatus for hiring articles; Coin-freed facilities or services
    • G07F17/32—Coin-freed apparatus for hiring articles; Coin-freed facilities or services for games, toys, sports, or amusements
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F17/00—Coin-freed apparatus for hiring articles; Coin-freed facilities or services
    • G07F17/32—Coin-freed apparatus for hiring articles; Coin-freed facilities or services for games, toys, sports, or amusements
    • G07F17/3286—Type of games
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F17/00—Coin-freed apparatus for hiring articles; Coin-freed facilities or services
    • G07F17/32—Coin-freed apparatus for hiring articles; Coin-freed facilities or services for games, toys, sports, or amusements
    • G07F17/3286—Type of games
    • G07F17/329—Regular and instant lottery, e.g. electronic scratch cards

Definitions

  • the invention relates to a gaming device with profit output, in which, according to a random function determined by a random generator from a predetermined supply of n symbols, a combination of m symbols representing a profit in at least one of several profit classes with a predetermined probability of winning is playable (drawable) and for the player can choose from the set of symbols a number of m symbols as his game combination, where m is less than n and the higher probability of winning are predetermined multiples of the lowest probability of winning.
  • the probability of winning is too low according to the legal regulations.
  • the legislation in the Federal Republic of Germany prescribes 1: 34000 for the lowest probability of winning.
  • the winnings spent may not exceed DM 3, for example, according to legal regulations.
  • the conventional games of chance can therefore not be transferred identically to a coin-operated device with a profit.
  • the invention has for its object to provide a coin-operated gaming device of the generic type by which a conventional game of chance, e.g. Lotto, can be simulated largely identically, but there are still higher odds of winning.
  • a conventional game of chance e.g. Lotto
  • this object is achieved in that the number increased by 1 (a shortage ("rivet")) Number of symbols forming the game combination automatically a number x can be played out according to a random function as a winning class with a higher probability of winning than corresponds to a probability of 1 to "n over m" for the winning class with the lowest winning probability, taking into account the predetermined multiples for the higher winning probabilities .
  • the game is allocated in advance to the winning class and thus the amount of the win according to a random function, without taking into account the symbols set for him by the player and / or the gaming device.
  • the probability of winning in the individual winning classes is in a ratio predetermined by the multiples mentioned.
  • the random function can be chosen so that the probability of winning is greater in all classes, but the ratio is retained.
  • the higher probability of winning can be determined in a ratio other than the "normal" ratio to the lowest probability of winning.
  • a row of at least m display spaces are provided for displaying the symbols played out on a display field and that a number x of the symbols set in a self-determined random sequence on the display spaces corresponding to the played profit class and on the other display spaces other than set symbols from the symbol set can be displayed.
  • symbols which have been automatically played out from the set symbols can be displayed on the display spaces which are automatically determined in the random sequence according to a random function.
  • symbols played out from the unset symbols of the symbol set according to a random function can be displayed on the remaining display spaces. This also ensures that the same "wrong" symbols are not always used for the display.
  • the random generator has a first random number generator, by means of which the winning class can be played out as the number x of the symbols set and the associated probability of winning, and a second random number generator, by means of which the order in which the first random generator generates it can be played out played number x from the set symbols is to be displayed on the display, and identifies a third random number generator, from the set symbols the number x of symbols set by the first random number generator and a number of mx symbols can be played out from the unset symbols in the order determined by the second random number generator for display.
  • the random generator as a microprocessor.
  • the coin-operated lottery game device shown in FIG. 1 has a housing with a front part and side and back parts and at least one circuit board 6 arranged in the housing with circuit elements fixed thereon, connected by electrical lines to one another and to external operating and display devices, as they are 2 and 3 are shown.
  • a display field 1 is embedded in the front part, which consists of light bulbs marked with numbers and / or symbols - but expediently as a TV monitor, if necessary in the form of an LC display on which groups of numbers and / or symbols can be depicted.
  • a selection device 3 is attached to the front part, by means of which the numbers "1" to "49" shown on the display field 1 are used to select six numbers in any order can also be set, display devices 4 for the start and the amount accrued during a game of chance and for the contents of a coin store 5.
  • the gaming device is operated with mains power or from a built-in voltage-stabilized power supply.
  • circuit elements 8 to 11 are connected to the power supply 7, namely a first random number generator 8, a second random number generator 9, a comparator 10 in the form of a microprocessor and a further random number generator 11.
  • the circuit elements can, however also be designed as a whole or each individually as appropriately programmed microprocessors.
  • a lottery ticket with numbers and symbols is shown on display field 1, a TV monitor or an LC display.
  • the player is then asked by a light signal, for example on the display field 1, to use the dialing device 3 to select a limited number of the numbers from "1" to "49" shown on the lottery ticket Number, here six, to choose.
  • the random number generator 8 is then activated, which determines the probability of winning for a specific winning class and plays out the latter, e.g. winning class "3" for three correct numbers with a probability of 20%, winning class "4" for four correct numbers with a probability of 10 % etc.
  • the random number generator 9 is then started up, which generates the winning numbers and their position in the drawing sequence, e.g. the first, second and sixth number in the "3 correct" winning class or the first, second, third and fifth in the "4 correct” winning class etc.
  • the comparator 10 now compares the numbers set with the winning numbers played out by the random generator 9 and assigned to a specific drawing position.
  • the numbers set match the random numbers played these are temporarily stored and the number of symbols or sample size is reduced by the corresponding number.
  • the sample with "3 correct” is reduced to 46 (49 minus 3).
  • Numbers are again played out from the number of numbers - possibly reduced as above - with the subsequent random number generator 11 and these are in turn compared with the other numbers set, in this case 6 minus 3, and the "correct numbers" are stored again.
  • FIGS. 1 and 2 The structure of the lottery game apparatus according to FIGS. 1 and 2 is described in somewhat more detail below with reference to FIG. 3, the same reference numbers being used for identical or equivalent components. Furthermore, lines of the same designation are connected to one another in FIG. 3.
  • a clock pulse generator 50 generates high-frequency clock pulses C and feeds them to a clock counter 51.
  • the clock counter 51 generates successive clock signals T1 to T9 at predetermined intervals after each predetermined number of clock pulses C.
  • the clock pulses C are also fed to a random pulse generator 52 which generates 0 to 9999 pulses during the duration of the clock signal T1 according to a random function. These pulses are fed via an AND gate 53 which is gated during the duration of the clock signal T1 to the counting input of a counter 54 which, when the prescribed number of coins is input into the coin input and output device 2, is reset by a reset signal R of the coin input and output device 0 has been reset.
  • the counter 54 has a counting capacity of 0 to 9999 and, at the end of the clock signal T1, represents the random number of the pulses of the random pulse generator 52 supplied to it during the duration of the clock signal T1 in binary form at its outputs.
  • a code converter 55 connected, which represents the count of counter 54 with a count in the range from 0 to 5000 in the number 0 put by six zeros at its six exits; with a count value in the range from 5001 to 7000 in the number 1, represented by a binary "1" at its last output, shown on the far right in FIG.
  • the number at the exit of the code converter 55 corresponds to the winning class in the respective game, ie 0 or 1 or 2 ... or 6 correct numbers.
  • the probability with which the individual winning classes occur therefore corresponds to the ratio of the range of the count values of the counter 54 assigned to the respective winning class by the code converter 55 to the maximum number of pulses of the random pulse generator 52 during the clock signal T1, that is to say 50% in the present example. for 0 correct, 20% for one correct, 15% for two correct, 10% for three correct, 3.5% for four correct, about 1.5% for five correct and 0.01% for six correct.
  • the number appearing at the output of the code converter 55 as a winning class is transmitted in parallel in a ring or circulation shift register 56 consisting of six binary stages, the clock signal T2 being fed to a position input L of the shift register 56.
  • the clock signal T2 loads two further shift registers 57 and 58, each consisting of six binary stages with the number 0, via a charging input L, i.e. deleted.
  • the third clock signal T3 occurs, which gates two AND gates 59 and 60.
  • the AND gate 59 then allows clock pulses C via an OR gate 61 to the shift input S of the shift register 56 and the AND gate 60 output pulses of a further random pulse generator 62 via an OR gate 63 to the data input D of the shift register 57 and to one input each AND gate 64 and an INHIBIT gate 65 through.
  • the output of the last stage of the shift register 57 is connected to the inhibit input of the INHIBIT gate 65 and to the other input of the OR gate 63.
  • the outputs of all the binary stages of the shift register 57 are linked by a NAND gate 66, the output of which is connected to the stage of the clock counter 51 emitting the clock signal T3 and blocks or interrupts the clock signal T3 as soon as all inputs of the NAND gate 66 are connected by 1 Signals of the shift register 57 are occupied.
  • the random pulse generator 62 is designed in such a way that it generates a pulse according to a random function after each clock pulse C supplied to it, the duration of the pulses of the random pulse generator 62 being shorter than the duration of the pause between two clock pulses C and approximately in the middle , ie occur at a distance from two successive clock pulses, as shown in the pulse diagram of FIG. 2 in the line "62" for the pulses of the random pulse generator 62 and in the line "C" above for the clock pulses C.
  • the output of the OR gate 61 is also connected to the shift input S of the shift register 57 and via an OR gate 67 to the shift input S of the shift register 58.
  • the output of the last stage of the shift register 58 is connected via one input of an OR gate 68 and the output of the AND gate 64 via the other input of the OR gate 68 to the data input D of the shift register 58.
  • the AND gate 64 is therefore sampled by the 1 signal emitted by the last stage of the shift register 56, so that during the clock signal T3 clock pulses C via the AND gate 59 and the OR gate 61 to the shift input S of the shift register 56 and pulses of the random pulse generator 62 via the AND gate 60, the AND gate 64 and the OR gate 68 can reach the data input D of the shift register 58.
  • the first clock pulse C during the clock signal T3 the content of the shift register 56 is then shifted by one stage, so that now the first and the last stage of the shift register 56 each contain a binary "1" and the remaining stages contain a binary "0".
  • the clock pulse C passed through the OR gate 61 also shifts the content of the shift registers 57 and 58.
  • the pulse From the output of the OR gate 61, the pulse also reaches the shift input S of the shift register 57 and via the OR gate 67 to the shift input S of the shift register 58.
  • the output pulse of the random pulse generator 62 therefore causes an additional shift in the content of the shift register 56 by one stage and loading the first stage of shift registers 57 and 58 with a binary "1" so that the two binary ones in shift register 56 are now in the first two stages and also the two shift registers 57 and 58 each with a binary "1" in the first stage are loaded.
  • the next clock pulse C causes a further shift in the content of all three shift registers 56, 57 and 58 by one stage, so that only the second and third stages of shift register 56 and in each case only the second stage of shift registers 57 and 58 with a binary "1" are loaded. If, after the second clock pulse C, the random pulse generator 62 generates a further pulse, it is not let through by the AND gate 64 and the OR gate 68, which is now blocked by the 0 signal of the last stage of the shift register 56, but only by the AND gate 65 via the OR gates 61 and 67 to the shift inputs S of all three shift registers 56, 57 and 58 and via the OR gate 63 to the data input D of the shift register 57.
  • the content of the shift registers 56 and 58 is only shifted by one step and a binary "1" is shifted into the shift register 57.
  • the shift register 57 like the shift register 56, now contains two binary ones, whereas the shift register 58 still only contains a binary "1".
  • the random pulse generator 62 does not generate any further pulses, the clock pulses C merely shift the contents of all shift registers 56 to 58 further, and each time with each further output pulse from the random pulse generator 62 one becomes Binary "1" is shifted into shift register 57 when INHIBIT element 65 is gated by a 0 signal of the last stage of shift register 57. These processes are repeated until all stages of the shift register 57 are loaded with a binary "1".
  • the NAND gate 66 blocks or interrupts the clock signal T3, so that no further clock pulses C or pulses from the random pulse generator 62 can be fed to the shift inputs S of the shift registers 56 to 58 .
  • the shift registers 56 and 58 then contain two binary ones, the binary ones in the shift register 58 being distributed over any two stages depending on the number of pulses generated by the random pulse generator 62 until the NAND gate 66 responds each with 1 signals in the last stages of the shift register or not.
  • the distribution of the two ones in the shift register 58 then deviates from the distribution of the ones in the shift register 56 and, as will be explained below, determines the sequence in which two numbers set by means of the selector device 3 are correct in the course of the following clock signals T4 to T9 "and four unset numbers are played out as" wrong "numbers.
  • the device for playing out the "correct” and “incorrect” numbers as a function of the sequence and number of incorrect and correct numbers determined by the content of the shift register 58 and the numbers set by the player using the selection device 3 contains a selection switch 69 as the selection device 3 with forty-nine fixed contacts and a rotary contact, with a key switch 70, via which the root of the rotary contact is a one-sign nal can be fed, and a memory register 71 with forty-nine binary memory elements, each of which is assigned the numbers "1" to "49” in this order and whose memory inputs are each connected to one of the fixed contacts of the selector switch 69.
  • the player sets the rotary contact of the selector switch 69 to one of the fixed contacts, which is connected to that memory element of the register 71 to which the number desired by the player is assigned, and then the player actuates the key switch 70 so that A binary "1" is set in the relevant memory element.
  • a 1 signal then occurs at the output of the memory elements assigned to the set numbers, and a 0 signal at the outputs of the other memory elements.
  • the player has selected the numbers "2" and "5", so that a 1 signal occurs at the outputs of the second and fifth memory elements.
  • the output signal of each memory element of the register 71 is compared with the output signal of the last stage of the shift register 58 by means of a coincidence element 72 (an EXOR element with a subsequent NOT element). If both signals match, the COINCIDENCE gate generates a 1 signal and otherwise a 0 signal.
  • the output signals of the COINCIDENCE elements 72 are each fed to an INHIBIT element 73.
  • the INHIBIT gates 73 also link the output signal to one stage of a circulation or ring shift register 74 of forty-nine Stages, a memory register 75 of forty-nine stages and the output signal inverted by a NOT gate 76 of an OR gate 77 linking the clock signals T4 to T9, the output signals of the memory register 75 being fed to the inverting input of the INHIBIT gates 73, respectively.
  • the output signals of the INHIBIT elements 73 are supplied on the one hand to the one reset input of a flip-flop 78 which responds to a 1-0 transition and on the other hand to a set input of one memory element of the memory register 75.
  • the output signals of the memory register 75 are also fed to a display controller 80, which links these output signals to the clock signals T4 to T9 and controls the display on six display locations 81 of the display field 1.
  • the output signal of the OR gate 77 is also fed to a set input of the flip-flop 78 which responds to a 1-0 transition.
  • the output of the flip-flop 78 assigned to this set input is connected to an input of an AND gate 82 that supplies the clock pulses C via an OR gate 83 as a function of the output signal of the flip-flop 78.
  • the output of the OR gate 77 is connected to an input of an AND gate 84, which passes the output signals of a further random pulse generator 85 as a function of the output signal of the OR gate 77 and feeds the shift input S of the shift register 74 via the OR gate 83 .
  • the output lines of the COINCIDENCE elements 72 are not connected to the registers 74 and 75, but cross them, as indicated by dashed lines.
  • the output lines of the shift register 74 are also not connected to the shift register 75, but cross it as it is is indicated by the dashed lines in register 75).
  • the random pulse generator 85 generates a number from zero to at least forty-nine pulses according to a random function.
  • the shift register 74 becomes a binary "1" in all stages, for example the first stage, and all other stages of the shift register 74 set a binary "0".
  • the player After the player has set the numbers he wants in the memory register 71 and the number and sequence of correct numbers in the shift register 58 at the end of the clock signal T3 is below the numbers set by the player, the first of the numbers to be played out by the gaming device is played out during the action signal T4 .
  • the shift register 58 a binary "1" (for "two right") in the first and fifth stages and a binary "0" (for "four wrong") (“rivets”) ) stands.
  • the content of the shift register 58 is shifted by one stage, so that a 1 signal occurs at the output of the last stage of the shift register 58.
  • the flip-flop 78 was also reset when the coin was input, so that a 0 signal occurs at its assigned output.
  • the content of the shift register 74 initially remains unchanged, so that, because of the 1 signal from the output of the last stage of the shift register 58, all have an unset memory element (indicated by a binary "0" at the output) connected COINCIDENCE elements 72 generate a 0 signal, whereas the COINCENCE elements 72 connected to a set memory element of the shift register 71 generate a 1 signal. Since the clock signal T4 gates the AND gate 84, the pulses of the random pulse generator 85 are passed to the shift input S of the shift register 74, so that they shift the binary "1" stored in the shift register 74 by one stage with each pulse.
  • the binary "1" remains at any stage of the shift register 74 after the last pulse of the random pulse generator 85, so that this stage is the only one to emit a 1 signal .
  • This 1 signal is linked by the INHIBIT element 73 connected to this stage with the output signal of a corresponding COINCIDENCE element 72 and a memory element of the memory register 75. Since all memory elements of the memory register 75 contain a binary "0" and the NOT element 76 generates a 1 signal at the end of the clock signal T4, only that INHIBIT element 73 emits a 1 signal that has a 1 signal from the shift register 74 and receives a 1 signal from one of the coincidence gates 72.
  • the second INHIBIT element 73 which is connected to the second stage of the shift register 74, generates at the end of the clock signal T4 a 1 signal, through which in the second memory element of the memory register 75 a binary "1" is set.
  • the NOT gate 76 With the trailing edge of the clock signal T4, the NOT gate 76 not only switched the output signal of the second INHIBIT gate 73 to the aforementioned 1 signal, but also set the flip-flop 78 so that a 1 signal occurs at its occupied output. with which the AND gate 82 is scanned.
  • the clock signals C occur with a delay compared to the trailing edges of the clock signals T4 to T9. Since the 1 signal of the second INHIBIT gate 73 is also switched through the OR gate 79 to the reset input of the flip-flop 78, the flip-flop 78 is immediately reset, so that the AND gate 82 is also immediately blocked again before a Clock pulse C can be switched through.
  • the 1 signal occurring at the output of the second memory element of the memory register 75 is decoded by the display controller 80 as a decimal number "2", since the second memory element is assigned to the decimal number "2”, and at the end of the clock signal T4 in the first display space 81 of the display field 1 displayed as "2".
  • clock pulses C are now transmitted from the AND gate 82 via the OR gate 83 to the shift input S of the shift register 74 passed, so that the binary "1" contained in the shift register 74 is shifted by one stage with each clock pulse C, and until the binary "1" in the shift register 74 meets such a memory element of the shift register 71 (so to speak at the same level) stands) in which a binary "1" is stored.
  • this is the fifth stage of the shift register 74 because a binary "1" is stored in the fifth memory element of the memory register 71.
  • the fifth coincidence element 72 therefore generates, since it is occupied by a 1 signal at both inputs, a 1 signal which is associated with the 1 signal of the fifth stage of the shift register 74 and the 0 signal of the fifth stage of the storage register 75 is linked by the fifth INHIBIT element 73 when the 1 signal occurs at the output of the NOT element 76, that is to say at the end of the clock signal T4, to form a 1 signal, by means of which, on the one hand, a binary " 1 "and the flip-flop 78 is reset.
  • the 0 signal now occurring at the output of the flip-flop 78 blocks the transmission of further clock pulses C by the AND gate 82, so that no further displacement of the binary "1" stored in the shift register 74 is effected. In this case, display controller 1 would therefore trigger the display of decimal number "5" in the first display position 81 of display field 1.
  • the clock counter 51 ensures that the next clock signal T5 only occurs after at least 43 clock pulses C after the end of the clock signal T4. The same applies to the time intervals of the following clock signals T5 to T9.
  • the fourth INHIBIT element 73 is gated at the end of the clock signal T5, so that it emits a 1 signal at the output and blocks the further supply of clock pulses C to the shift input S of the shift register 74 by resetting the flip-flop 78.
  • the binary "1" simultaneously set in the fourth memory element of the memory register 75 by the 1 signal generated by the fourth INHIBIT element 73 has the effect via the display control 80 that the decimal number "4" in the second display space 81 of the display field 1 assigned to the clock signal T5. is shown.
  • clock signal T6 the same process is repeated as with clock signal T5, i.e. it is played out from the non-set decimal numbers during the clock signal T6 and displayed in the third display position of the display field 1, because during the clock signal T6 a binary "0" occurs at the output of the shift register 58, which causes a non-set decimal number to be played out.
  • Modifications to the described exemplary embodiment can consist, for example, in that instead of the display locations 81 or in addition to these 49 indicator lamps are provided, each of which is assigned one of the 49 decimal numbers for display and which are each connected to one of the output lines of the memory elements of the memory register 75, so that each time after playing out a decimal number, the relevant indicator lamp and thus the decimal number assigned to it light up.
  • the illustrated embodiment can be modified accordingly without further ado.
  • the counter 54 can have a different counting capacity and the code converter 55 can be modified accordingly.
EP87113449A 1987-03-17 1987-09-15 Appareil de jeu de hasard avec payement de gain Withdrawn EP0282631A3 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU83164/87A AU8316487A (en) 1987-03-17 1987-12-31 Dividend-paying gaming machine

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE8703997U 1987-03-17
DE8703997U DE8703997U1 (fr) 1987-03-17 1987-03-17

Publications (2)

Publication Number Publication Date
EP0282631A2 true EP0282631A2 (fr) 1988-09-21
EP0282631A3 EP0282631A3 (fr) 1990-03-07

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EP87113449A Withdrawn EP0282631A3 (fr) 1987-03-17 1987-09-15 Appareil de jeu de hasard avec payement de gain

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EP (1) EP0282631A3 (fr)
JP (1) JPS63230188A (fr)
DE (1) DE8703997U1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0444932A2 (fr) * 1990-03-01 1991-09-04 Stewart Milton Lamle Appareil pour attribuer un grin jackpot
US5074559A (en) * 1989-04-03 1991-12-24 Kabushiki Kaisha Universal Slot machine
DE102010007021A1 (de) * 2010-02-05 2011-08-11 Nsm-Löwen Entertainment Gmbh, 55411 Verfahren zur Ansteuerung von Segmenten einer Sieben-Segment-Anzeige und Verfahren zum Betreiben eines Unterhaltungsspielgerätes dazu

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Publication number Priority date Publication date Assignee Title
EP0507435A3 (en) * 1991-04-02 1993-04-07 Elton Fabrications Limited Improvements relating to machines for gaming, amusement and the like

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FR2518289A1 (fr) * 1981-12-10 1983-06-17 Prominov Sa Tableau d'affichage de chiffres aleatoires
CH651219A5 (en) * 1982-12-08 1985-09-13 Newlift S A Electric device for selecting and displaying p random numbers among n numbers
EP0180676A2 (fr) * 1984-09-28 1986-05-14 William Kreisner Ordinateur de loterie aléatoire
EP0194395A2 (fr) * 1985-03-12 1986-09-17 Alex P. Moosz Appareil électronique de génération de séries de valeurs numériques pour jeux de loterie

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JPS5149147A (ja) * 1974-10-25 1976-04-28 Tamura Kaken Co Ltd Fuirumujofuratsukusu
CA1100635A (fr) * 1976-05-17 1981-05-05 Andres R. Lucero Traduction non-disponible
JPS5940883A (ja) * 1982-08-31 1984-03-06 株式会社・エル・アイ・シ− スロツトマシンのリ−ル停止機構
CA1265870A (fr) * 1986-02-10 1990-02-13 Felix M. Dire Jeu

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
FR2518289A1 (fr) * 1981-12-10 1983-06-17 Prominov Sa Tableau d'affichage de chiffres aleatoires
CH651219A5 (en) * 1982-12-08 1985-09-13 Newlift S A Electric device for selecting and displaying p random numbers among n numbers
EP0180676A2 (fr) * 1984-09-28 1986-05-14 William Kreisner Ordinateur de loterie aléatoire
EP0194395A2 (fr) * 1985-03-12 1986-09-17 Alex P. Moosz Appareil électronique de génération de séries de valeurs numériques pour jeux de loterie

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5074559A (en) * 1989-04-03 1991-12-24 Kabushiki Kaisha Universal Slot machine
EP0444932A2 (fr) * 1990-03-01 1991-09-04 Stewart Milton Lamle Appareil pour attribuer un grin jackpot
EP0444932A3 (en) * 1990-03-01 1992-01-22 Stewart Milton Lamle Apparatus for awarding a jackpot win
DE102010007021A1 (de) * 2010-02-05 2011-08-11 Nsm-Löwen Entertainment Gmbh, 55411 Verfahren zur Ansteuerung von Segmenten einer Sieben-Segment-Anzeige und Verfahren zum Betreiben eines Unterhaltungsspielgerätes dazu
DE102010007021B4 (de) * 2010-02-05 2013-03-28 Nsm-Löwen Entertainment Gmbh Verfahren zur Ansteuerung von Segmenten einer Sieben-Segment-Anzeige und Verfahren zum Betreiben eines Unterhaltungsspielgerätes dazu

Also Published As

Publication number Publication date
EP0282631A3 (fr) 1990-03-07
JPS63230188A (ja) 1988-09-26
DE8703997U1 (fr) 1987-04-30

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