EP0255837A1 - Procede epitaxial liquide pour la fabrication de structures semi-conductrices en trois dimensions - Google Patents

Procede epitaxial liquide pour la fabrication de structures semi-conductrices en trois dimensions

Info

Publication number
EP0255837A1
EP0255837A1 EP19870902458 EP87902458A EP0255837A1 EP 0255837 A1 EP0255837 A1 EP 0255837A1 EP 19870902458 EP19870902458 EP 19870902458 EP 87902458 A EP87902458 A EP 87902458A EP 0255837 A1 EP0255837 A1 EP 0255837A1
Authority
EP
European Patent Office
Prior art keywords
substrate
layer
epitaxial
silicon
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP19870902458
Other languages
German (de)
English (en)
Inventor
Elisabeth Bauser
Horst Paul Strunk
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Max Planck Gesellschaft zur Foerderung der Wissenschaften eV
Original Assignee
Max Planck Gesellschaft zur Foerderung der Wissenschaften eV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Max Planck Gesellschaft zur Foerderung der Wissenschaften eV filed Critical Max Planck Gesellschaft zur Foerderung der Wissenschaften eV
Publication of EP0255837A1 publication Critical patent/EP0255837A1/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02623—Liquid deposition
    • H01L21/02625—Liquid deposition using melted materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02623—Liquid deposition
    • H01L21/02628—Liquid deposition using solutions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition

Definitions

  • the present invention relates to new applications of the liquid epitaxy method, in particular the production of epitaxial single-crystalline semiconductor layers of high crystalline perfection in a multilayer arrangement on intermediate layers of insulating material and / or carbon and / or metal for the production of three-dimensional semiconductor structures in which low mechanical stresses prevail and the charge carrier densities between 10 14 and 10 21 per cm 3 , with very low manufacturing temperatures, e.g. B. between 300 and 900 ° C.
  • the germ specification for the respective epitaxial layer takes place in the openings of the intermediate layer, where monocrystalline material is exposed. From the openings, the intermediate layers are overgrown laterally and in single crystals.
  • the repeated application of the liquid epitaxy in the manner described allows a three-dimensional integration in single-crystal, largely defect-free multilayer structures.
  • the invention also relates to semiconductor devices and structures which are obtained by the described methods.
  • the invention relates primarily to the production of single-crystalline semiconductor materials in a multilayer structure for three-dimensional integrated circuits, in which at least one further component layer with active components is applied over a largely complete component layer.
  • three-dimensional integrated circuits limitations of the currently practiced planar technology are to be lifted, which are conditional, among other things.
  • the invention relates to the production of certain, in particular (but not necessarily) highly conductive epitaxial layers which form parts of three-dimensional structures, but which can also be used instead of conventional contacting layers in semiconductor components.
  • an interrupted layered pattern made of at least one of the materials insulating material, carbon, is formed on a surface of a predetermined crystallographic orientation of a single-crystalline substrate , Metal, and on areas of the surface that are not covered by the pattern, liquid epitaxy forms at least one single-crystalline epitaxial layer that extends laterally over at least part of the pattern.
  • an epitaxial transition layer made of a germanium-silicon alloy and then an epitaxial layer made of germanium or a compound semiconductor, in particular a compound which comprises at least one element from III. Contains group and at least one element from the V group of the periodic table, deposited by liquid epitaxy.
  • the germanium content of the transition layer preferably increases with increasing distance from the silicon substrate.
  • the layer of the compound semiconductor can also be deposited on the silicon substrate without a transition layer.
  • a polycrystalline substrate e.g. B. polysilicon, at least one layer of the substrate material or a crystallographically compatible material applied by liquid epitaxy.
  • an epitaxial layer is applied to a substrate with defined localized crystal defects, in particular dislocations, preferably by a liquid epitaxy method.
  • the substrate can be a twin crystal or a twin plane with a very small angular displacement of the crystal planes of the two crystal parts included, the angle is preferably less than one minute of angle.
  • FIG. 1 is a greatly enlarged sectional view of a three-dimensional semiconductor structure according to an embodiment of the invention during various stages of its manufacture
  • FIG. 2 shows a further three-dimensional semiconductor structure according to a further embodiment of the invention
  • FIGS. 3A to 3C consisting of FIGS. 3A to 3C, a three-dimensional semiconductor structure according to an embodiment of the invention during various stages of its manufacture;
  • FIG. 5 shows a schematic illustration of the production of a crystal body from which substrates of the type shown in FIG. 4 can be formed;
  • FIG. 6 shows a partial view of a further semiconductor structure according to an embodiment of the invention
  • FIG. 7 shows a sectional view of a structure with a polycrystalline substrate produced according to an embodiment of the invention
  • FIGS. 8A to 8D sectional views of a further three-dimensional semiconductor structure according to FIG. an embodiment of the invention.
  • 1 shows an example of how a three-dimensional semiconductor structure or generally a crystal structure with a single crystal character and very low mechanical stresses and low defect density can be produced between the different parts by means of a liquid epitaxy method.
  • 1 contains a monocrystalline substrate (10) which, for. B. can consist of a semiconductor material such as silicon and has a main surface (12) which is oriented crystallographically so that the crystal growth rate perpendicular to the main area (12) is small in relation to the crystal growth rate parallel to the main area (12).
  • the main surface (12) z. B. lie in the crystallographic ⁇ 111 ⁇ plane.
  • the surface (12) can have a slight misorientation by significantly less than 1 degree of angle, e.g. B. by 20 'to the (110) pole.
  • the ⁇ 111 ⁇ and ⁇ 100 ⁇ planes are suitable for gallium arsenide as substrate material.
  • the layers (14) can of course also form any other pattern that is required for the given three-dimensional structure, which is z. B. can be an integrated opto-electronic circuit arrangement or a "multi-storey" integrated circuit arrangement.
  • the layers (14) can consist of silicon dioxide, which has been produced, for example, by oxidation of the silicon substrate in a water vapor atmosphere and has obtained its final structure by a conventional photolithographic etching process.
  • the production of the layer pattern (14a 7) can be done by any tes, suitable for the layer material in question, such as oxidation in situ, sputtering, vapor deposition and the like .
  • the layered pattern can also consist of different materials, e.g. B. insulating layers and metal layers.
  • the substrate can contain zones of different conductivity types, which have been formed, for example, by diffusion in planar technology or in any other suitable manner and form an integrated circuit together with the layer pattern.
  • This integrated circuit can be contacted by contact areas at the edge and / or by etched holes and represents a first circuit level in the finished process product, which is separated from the subsequently applied semiconductor material, if necessary, by insulating parts of the intermediate layer.
  • an epitaxial layer is then each grown by liquid epitaxy.
  • a molten metal that contains indium, gallium, bismuth, lead, tin or antimony as the solvent and silicon as the solute.
  • the solvent generally determines the conduction type of the epitaxially growing layer, i.e. H. that a p-type layer grows in the case of indium and gallium and an n-type layer in the case of antimony and bismuth.
  • An n-type layer can also be produced with indium, tin or lead as a solvent if phosphorus or arsenic is additionally dissolved in the solvent as a dopant, since the incorporation coefficients of phosphorus or arsenic are significantly higher than those of indium or lead and the conductivity type is determined accordingly by the phosphorus or arsenic.
  • indium as solvent temperatures between about 550 and 1000 ° C will generally be used, the indium doping of the epitaxially growing silicon layer increasing with increasing temperature.
  • Dopant concentrations of up to over 10 20 donors per cm 3 can be achieved.
  • gallium as the solvent, it is preferred to work in the temperature range between about 300 and 800 ° C. In this case,
  • the formation of the epitaxial layers on the exposed areas of the main surface (12) is preferably carried out by passing the melt used by centrifugal force over the substrate, as described in the patents mentioned at the beginning.
  • the epitaxial growth begins in the spaces (16a %) and the epitaxial layers then grow laterally over the layers (14a, 14b %), as shown by the dashed areas (18a, 18b etc.). If the epitaxial deposition of the silicon from the melt is continued, the areas (18a, 18b) eventually grow together to form a coherent, monocrystalline layer (20) and a very smooth surface (22) is then formed very quickly.
  • a substrate (10) that has a predetermined basic conductivity type (and can contain an integrated circuit with zones of opposite conductivity type and zones with different amounts of conductivity) and that has an epitaxially grown layer ( 24) carries.
  • the pattern of the layers (14a, 14b %) is located between the substrate (10) and the layer (24).
  • the method can now be continued in a corresponding manner, as shown in FIG. 2. It is therefore possible to produce a further integrated circuit level in the epitaxial layer (24) by diffusion and photolithography and another one on the surface (22) Apply layer patterns (14aa, 14bb etc.). Another epitaxial layer (26) can then be grown, etc.
  • the substrate (10) and the layers (24, 26) can have desired conductivity types and also, for. B. form an npn structure or the like. By etching out trenches, as is shown in FIG. 2 at (28), the structure can be subdivided in the desired manner and, if necessary, deeper areas or zones can be contacted. Lower areas can be z. B. contact by epitaxial filling with highly doped semiconductor material.
  • the substrate and the epitaxial layers (24) and (26) consist of the same material, for example silicon.
  • this is not necessary, rather three-dimensional heterostructures are also known.
  • An example of this is shown in FIGS. 3A to 3C. In this example it is assumed that a heterostructure consisting of an element semiconductor such as silicon and one
  • a III B V compound such as GaAs
  • GaAsP, GaAlP, etc. is to be produced.
  • a substrate (10) which consists of monocrystalline silicon and has a main surface (12) which lies in the crystallographic ⁇ 111 ⁇ plane or the der100 ⁇ plane.
  • the epi tactical layer is said to. B. consist of gallium arsenide, so that the finished three-dimensional structure can be used, for example, for an integrated opto-electronic circuit, in which a purely electronic part of the integrated circuit is formed in the silicon substrate (10) and a regionally opto-electronic part in the epitaxial gallium arsenide layer.
  • Adaptation layer z. B. can grow from a silicon-germanium alloy, the germanium content of which preferably increases with increasing distance from the surface (12), which is achieved by temperature control in liquid epitaxy or by forming several superimposed epitaxial layers with solutions containing different proportions of silicon and germanium contain, can be achieved.
  • the adaptation layer (30) thus becomes richer in germanium with increasing distance from the main surface (12) and since germanium has a lattice constant that fits well with that of gallium arsenide, the adaptation layer (s) (30) in the 1 described way now apply an epitaxial Gal lium arsenide layer (32) by liquid epitaxy. If necessary, the silicon substrate (10) can now be separated from the monocrystalline, epitaxial gallium arsenide layer (32) by an etched trench (34), as shown in FIG. 3C.
  • An increase in germanium concentration with increasing distance from the main surface (12) can be achieved, for example, by using an indium melt saturated with silicon and germanium and starting the epitaxial growth at a temperature of about 700 ° C and then gradually lowering the temperature to about 500 ° C .
  • Fig. 4 shows a substrate crystal (100), which consists of two crystals that adjoin each other at a grain boundary (102) so that there the crystal planes represented by dashes of the two crystal regions form a very small angle with each other, e.g. B. an angle on the order of an angular minute or less, e.g. B. 20 arc seconds.
  • Step dislocations then form at the grain boundary, the penetration points of which are represented by points (104) in FIG. 4.
  • These step dislocation puncture points represent preferred starting points for the epitaxial growing crystal and when using a substrate of the type shown in FIG. 4 then a very uniform crystallization front (106) grows from the grain boundary (102) with steps of atomic height above the substrate surface, one extraordinarily homogeneous epitaxial layer with a very even distribution of the built-in doping atoms and a very smooth surface is created. This is of great importance for highly integrated circuits with extreme component density.
  • Substrate crystals of the type shown in FIG. 4 can be produced by crystal growth using a modified Czochralski method, as shown in FIG. 5.
  • Two seed or seed crystals (108a, 108b) are used, which are attached to a rotatable pulling or holding rod (140) with an orientation offset by fractions of an angular minute.
  • Separate single crystals initially grow on the seed crystals (108a, 108b), but soon grow together and form a coherent twin or bicrystal (142), from which substrates of the type shown in FIG. 4 are then cut out, the grain boundary (102 ) may lie on an edge of the substrate or in the middle of the substrate. 4 and 5 substrates can of course also be used advantageously for other epitaxial processes.
  • liquid epitaxy is the production of so-called superlattices with mechanical spanning (strained superlattices), which, for. B. 50 to 100 layers of alternating silicon and a silicon-germanium alloy (z. B. with 30 to 50% germanium), as shown in Fig. 6th is shown schematically.
  • the layers can be 1 to 1000 atomic layers thick, which can be achieved by liquid epitaxy with transport of the solution by centrifugal force.
  • Liquid epitaxy can also produce silicon-germanium mixed crystals with a predetermined band gap and produce them in a suitable layer sequence, e.g. B. to realize so-called direct semiconductors, in which the charge carrier transition between the conduction band and the valence band takes place without phonon interaction, with element semiconductor materials.
  • a suitable layer sequence e.g. B.
  • liquid epitaxy method is the production of polycrystalline epitaxial layers on a polycrystalline substrate, e.g. B. poly-silicon.
  • Polysilicon is widely used in the manufacture of solar cells.
  • FIG. 7 shows, when using liquid epitaxy for the production of polycrystalline pn structures, a substrate (200) made of polysilicon is used, which has a surface 212, to which a multiplicity of crystal regions (202) adjoin.
  • a layer (204) is now generated on the surface (212) by liquid epitaxy, which contains corresponding epitaxial crystal regions (206a, 206b, 206c etc.).
  • the substrate can e.g. B. consist of p-type polysilicon and the layer (204) can be 0.3 to 10 ⁇ m thick, consist of n-Si licium, for example 10 18th
  • Donors / cm contain and are made by an indium-phosphorus alloy.
  • phosphorus as an alloy component or dopant has the advantage that oxide layers which, despite the surface cleaning usually carried out before the epitaxial coating, by chemical etching with hydrofluoric acid and subsequent plasma etching in a hydrogen atmosphere of 1% Do not interfere with the torr pressure or remain on the surface as phosphorus has a greater affinity for oxygen than silicon and therefore reduces the oxide.
  • Strips (314) of silicon dioxide are formed on the surface (312) by thermal oxidation and photolithographic etching.
  • the edges of the strips (314), which run perpendicular to the plane of the drawing, are positioned so that they run parallel to the line of intersection of the growth surface with a ⁇ 110 ⁇ grating plane.
  • the exposed silicon is then dissolved in the recesses between the oxide strips (314) with gallium at about 500 ° C to a depth of about 60 ⁇ m. Because of the low temperature during the dissolving process, trenches with distinct crystallographically oriented edges are formed.
  • the substrate is then cleaned and the oxide layers (314) are removed.
  • An approximately 20 ⁇ m thick base layer (320) made of silicon is then first grown on the strips (316; FIG. 8C) freed from the oxide layers (314) and alternately 25 p-type and 25 n-type, each 300 nm thick Individual layers (324) are deposited using the epitaxial centrifuge described in the aforementioned patents. A remarkable result is that the epitaxial growth takes place almost exclusively on the raised areas of the strip-shaped profiled crystal. The selective epitaxial coating therefore takes place without a masking layer.
  • the process described enables the production of monocrystalline semiconductor layers hav- ing a high degree of crystal perfection in a multi-layer arrangement on intermediate layers of an insulating material and / or carbone and / or metal, in order to produce three -dimensional semiconductor structures which offer low mechanical stresses and load-bearing densities of between 10 14 and 10 21 per cm 3 .
  • Very low manufacturing temperatures can be used, for examples between 300 and 900 ° C.
  • the seeding for each epitaxial layer is performed in the openings the intermediate layer where a monocrystalline material is located in a free state. From these openings, the lateral a monocrystalline growth of the intermediate layers takes place.
  • the repeated application of the liquid epitaxial process d scribed allows three-dimensional integration in monocrystalline multilayer structures which are extremely devoid of d fects.
  • Liquid epitaxy produces epitaxial, single-crystalline semiconductor layers of high crystalline perfection.Multi-layer arrangement on intermediate layers of insulating material and / or carbon and / or metal for the production of three-dimensional semiconductor structures which have low mechanical stresses, charge carrier densities between 10 14 and 10 21 per cm 3 , with very low ones Manufacturing temperatures, e.g. B. between 300 and 900 ° C, gea can be processed.
  • the germ specification for the respective epitaxial layer takes place in the openings of the intermediate layer, monocrystalline material is exposed. From the openings, the intermediate layers will grow laterally and monocrystalline.
  • the repeated application of liquid epitaxy in the manner described allows three-dimensional integration in single-crystalline, largely defect-free multilayer structures.

Abstract

Le procédé ci-décrit permet de produire des couches semi-conductrices monocristallines d'une haute perfection cristalline dans une configuration multicouche sur des couches intermédiaires en matériau isolant et/ou en carbone et/ou en métal, en vue de fabriquer des structures semi-conductrices en trois dimensions, lesquelles présentent de faibles contraintes mécaniques et des densités de porteur de charge comprises entre 1014 et 1021 ou cm3. On peut travailler avec des températures de fabrication très faibles, comprises par ex. entre 300 et 900°C. L'ensemencement pour chaque couche épitaxiale s'effectue dans les ouvertures de la couche intermédiaire où se trouve à l'état libre une matière monocristalline. A partir de ces ouvertures s'opère la croissance latérale et monocristalline des couches intermédiaires. L'application répétée du procédé épitaxial liquide ci-décrit permet une intégration en trois dimensions dans des structures multicouches monocristallines très largement exemptes de défauts.
EP19870902458 1986-02-11 1987-02-11 Procede epitaxial liquide pour la fabrication de structures semi-conductrices en trois dimensions Ceased EP0255837A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19863604260 DE3604260A1 (de) 1986-02-11 1986-02-11 Fluessigkeitsepitaxieverfahren
DE3604260 1986-02-11

Publications (1)

Publication Number Publication Date
EP0255837A1 true EP0255837A1 (fr) 1988-02-17

Family

ID=6293866

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19870902458 Ceased EP0255837A1 (fr) 1986-02-11 1987-02-11 Procede epitaxial liquide pour la fabrication de structures semi-conductrices en trois dimensions

Country Status (4)

Country Link
EP (1) EP0255837A1 (fr)
JP (1) JPS63502472A (fr)
DE (1) DE3604260A1 (fr)
WO (1) WO1987004854A2 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4863877A (en) * 1987-11-13 1989-09-05 Kopin Corporation Ion implantation and annealing of compound semiconductor layers
US5453153A (en) * 1987-11-13 1995-09-26 Kopin Corporation Zone-melting recrystallization process
FR2629636B1 (fr) * 1988-04-05 1990-11-16 Thomson Csf Procede de realisation d'une alternance de couches de materiau semiconducteur monocristallin et de couches de materiau isolant
JP3016432B2 (ja) * 1989-09-21 2000-03-06 沖電気工業株式会社 半導体基板の製造方法
US5796119A (en) * 1993-10-29 1998-08-18 Texas Instruments Incorporated Silicon resonant tunneling

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4028147A (en) * 1974-12-06 1977-06-07 Hughes Aircraft Company Liquid phase epitaxial process for growing semi-insulating GaAs layers
JPS51126048A (en) * 1975-01-31 1976-11-02 Hitachi Ltd Hetero epitaxial growth method of iii-v group semi-conductors
JPS51138180A (en) * 1975-05-26 1976-11-29 Nippon Telegr & Teleph Corp <Ntt> Distributed feedback type semi-conductor laser and the method of manuf acturing it
JPS6040719B2 (ja) * 1979-03-30 1985-09-12 松下電器産業株式会社 半導体レ−ザ装置
DE3339272A1 (de) * 1983-10-28 1985-05-09 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung von a(pfeil abwaerts)3(pfeil abwaerts)b(pfeil abwaerts)5(pfeil abwaerts)-lumineszenzdioden
US4551394A (en) * 1984-11-26 1985-11-05 Honeywell Inc. Integrated three-dimensional localized epitaxial growth of Si with localized overgrowth of GaAs

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8704854A2 *

Also Published As

Publication number Publication date
DE3604260A1 (de) 1987-08-13
WO1987004854A3 (fr) 1988-03-24
WO1987004854A2 (fr) 1987-08-13
JPS63502472A (ja) 1988-09-14

Similar Documents

Publication Publication Date Title
DE60101069T2 (de) Siliziumkarbid und Verfahren zu seiner Herstellung
DE2416550C2 (de) Verfahren zum Herstellen eines Halbleiterbauelements mit versetzungsfreiem Übergitterstrukturkristall
EP1739210B1 (fr) Procédé pour la production d&#39;un monocristal semiconductor dopé, et III-V monocristal semiconductor.
DE602004003910T2 (de) Pufferstruktur für Heteroepitaxie auf einem Siliciumsubstrat
DE2030805A1 (de) Verfahren zur Ausbildung epitaxialer Kristalle oder Plattchen in ausgewählten Bereichen von Substraten
DE4138121C2 (de) Verfahren zur Herstellung einer Solarzelle
DE3446961A1 (de) Verfahren zur herstellung einer sic-halbleitervorrichtung
DE19510922A1 (de) Verfahren zur Herstellung eines Halbleiterbauelements, Verfahren zur Reinigung einer Kristalloberfläche eines Halbleiters sowie Halbleiterbauelement
DE10247017A1 (de) SiC-Einkristall, Verfahren zur Herstellung eines SiC-Einkristalls, SiC-Wafer mit einem Epitaxiefilm, Verfahren zur Herstellung eines SiC-Wafers, der einen Epitaxiefilm aufweist und eine elektronische Vorrichtung aus SiC
DE1803731C3 (de) Verfahren zum Kristallisieren einer binären Halbleiterverbindung
DE1223951B (de) Verfahren zur Herstellung von Halbleiter-bauelementen mit einem oder mehreren PN-UEbergaengen
DE1564191B2 (de) Verfahren zum herstellen einer integrierten halbleiterschaltung mit verschiedenen, gegeneinander und gegen ein gemeinsames siliziumsubstrat elektrisch isolierten schaltungselementen
DE3116268A1 (de) Verfahren zur herstellung einer halbleiteranordnung
DE1489258B1 (de) Verfahren zum Herstellen einer duennen leitenden Zone unter der Oberflaeche eines Siliciumkoerpers
DE2207056A1 (de) Verfahren zum selektiven epitaxialen Aufwachsen aus der flüssigen Phase
DE3514294A1 (de) Mit indium dotierte halbisolierende galliumarsenideinkristalle und verfahren zu ihrer herstellung
DE4427715C1 (de) Komposit-Struktur mit auf einer Diamantschicht und/oder einer diamantähnlichen Schicht angeordneter Halbleiterschicht sowie ein Verfahren zu deren Herstellung
EP0255837A1 (fr) Procede epitaxial liquide pour la fabrication de structures semi-conductrices en trois dimensions
EP1701386B1 (fr) Méthode pour l&#39;intégration de deux transistors bipolaires sur un substrat semi-conducteur, structure semi-conductrice dans un semi-conducteur et circuit cascode
DE3300716A1 (de) Verfahren zum bilden von monokristallinem silicium auf einer maskenschicht
DE2154386A1 (de) Verfahren zum Herstellen einer epitaktischen Schicht auf einem Halbleitersubstrat, bei dem das Selbstdotieren beim Aufwachsen der Schicht auf ein Mindestmaß verringert wird
DE2163075C2 (de) Verfahren zur Herstellung von elektrolumineszierenden Halbleiterbauelementen
DE3124456A1 (de) Halbleiterbauelement sowie verfahren zu dessen herstellung
DE3334236C2 (de) Verfahren zum Herstellen einer Halbleiteranordnung
DE19705516C2 (de) Halbleiter-Anordnung aus Siliziumcarbid und Verfahren zu ihrer Herstellung

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): BE DE FR GB IT NL

D17D Deferred search report published (deleted)
17P Request for examination filed

Effective date: 19880502

17Q First examination report despatched

Effective date: 19900726

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED

18R Application refused

Effective date: 19910526

RIN1 Information on inventor provided before grant (corrected)

Inventor name: BAUSER, ELISABETH

Inventor name: STRUNK, HORST, PAUL