EP0245290A1 - Dielectrique intermetallique en verre - Google Patents

Dielectrique intermetallique en verre

Info

Publication number
EP0245290A1
EP0245290A1 EP19860905550 EP86905550A EP0245290A1 EP 0245290 A1 EP0245290 A1 EP 0245290A1 EP 19860905550 EP19860905550 EP 19860905550 EP 86905550 A EP86905550 A EP 86905550A EP 0245290 A1 EP0245290 A1 EP 0245290A1
Authority
EP
European Patent Office
Prior art keywords
layer
dielectric
conductor
spun
glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP19860905550
Other languages
German (de)
English (en)
Inventor
John F. Teodorski
Terri Jewett-Enzmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of EP0245290A1 publication Critical patent/EP0245290A1/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates, in general, to means and methods for improved electronic devices, especially semiconductor devices and integrated circuits, and more particularly to improved manufacturing processes and structures involving multiple conductor layers and circuits made therewith.
  • interlayer dielectric serves to passivate the first conductor as well as to insulate and separate it from the overlying second conductor. Interlayer connection points are provided through openings formed for that purpose in the interlayer dielectric.
  • a primary dielectric layer is also required between the substrate and any conductive layers. This dielectric serves to passivate the substrate surface as well as insulate it from the overlying conductors. Openings are provided in the primary dielectric layer so that the various conductors may make contact with the device structures in the semiconductor substrate.
  • the surface topography of the device may be highly irregular. This creates step coverage problems with respect to the various layers, e.g., voids or cracks may occur in the conductor layers where they pass over abrupt steps in the surface topography. Further, the substrate and its various dielectric and conductor layers typically undergo substantial heating and cooling during manufacture and use. Because the coefficients of thermal expansion of the various materials are different, substantial stresses are created in the films. This can result in the formation of voids or the delamination of some or all of the various conductor and dielectric layers.
  • the word “device” is intended to include both individual devices, portions of devices, and collections of devices, as for example in integrated circuits and the like.
  • a structure comprising: a first conductor layer, a first dielectric adhesion layer on the first conductor layer, of for example, a plasma oxide or low pressure chemical vapor deposited (LPCVD) oxide, a second dielectric layer on the first dielectric layer formed from a spun-on glass layer, a third dielectric layer on the second dielectric layer and which is several times thicker than the first or second dielectric layers and which is formed from a plasma oxide or chemical vapor deposited (CVD) oxide, and a second conductor layer overlying the third dielectric layer.
  • LPCVD low pressure chemical vapor deposited
  • the spun-on glass layer be arsenic doped and that the third dielectric layer be phosphorous doped.
  • a semiconductor substrate covering the semiconductor substrate with an insulating layer, providing a first conductor layer on the insulating layer, providing a second conductor layer superposed above the first conductor layer and separated therefrom by a three part insulating layer, wherein the three part insulating layer is formed by first providing a dielectric adhesion layer on the first conductor layer, then providing a spun-on glass layer on the first dielectric adhesion layer, and finally providing a second dielectric layer on the spun-on glass layer and in contact with the second conductive layer.
  • the step of providing the first dielectric adhesion layer comprise providing that layer by plasma assisted oxide deposition or low pressure chemical vapor oxide deposition.
  • the step of providing the spun-on glass comprise providing an arsenic doped spun-on glass. It is further desirable that the step of providing the second dielectric layer comprise providing a plasma deposited oxide, a low pressure chemical vapor deposited oxide, and/or a phosphorous doped chemical vapor deposited oxide.
  • FIGS. 1-3 are cross-sectional views in simplified schematic form of a cross-over portion of a multi- conductor electronic device during different stages of fabrication and showing the arrangements of the various layers.
  • FIG. 1 is a cross-sectional view in simplified schematic form of portion 10 of an electronic device, for instance a semiconductor integrated circuit, comprising substrate 11 (e.g. silicon) covered by dielectric layer 12 (e.g. silicon oxide or nitride) and first conductor layer 13.
  • substrate 11 e.g. silicon
  • dielectric layer 12 e.g. silicon oxide or nitride
  • first conductor layer 13 is made of metal, semiconductor, semi-metal, intermetallic, or other conductive means. The means and method of the present invention are particularly useful when conductor 13 is of metal, e.g., aluminum or an aluminum (98%) - copper (1%) - silicon (1%) alloy.
  • Conductor layer 13 is patterned using means well known in the art to remove all except conductor portion 13a (FIG. 2).
  • FIG. 2 FIG.
  • conductor 13a which, in this example, has -its long dimension running perpendicular to the plane of the drawing.
  • interlayer dielectric 18 composed of a sandwich of three dielectric layers 14-16.
  • Second conductor layer 17 lies on top of interlayer dielectric 18.
  • conductor 17 may be thought of as a conductive stripe having its long dimension running parallel to the plane of the drawing.
  • conductors 13a and 17 form a multi-conductor insulated cross-over. Such cross-overs are commonly desired in the art.
  • the multi-conductor structure need not be limited merely to two conductors. By repetition of the basic conductor-insulator sandwich, the final structure can be composed of three, four, five or more conductor layers.
  • the present invention is concerned particularly with the construction and formation of interlayer dielectric 18. It has been found, that when conventional oxides or nitrides are used to form a dielectric region between two conductors, that substantial loss in manufacturing yield is encountered due to breaks in layer 17 where it passes over conductor 13a and/or adhesion failures between interlayer dielectric 18 and conductors 13a and/or 17. These effects result in opens or shorts in the finished circuit.
  • First dielectric layer 14 is chosen to be a material which adheres tightly to first conductor 13a. Silicon oxide formed by plasma assisted deposition or by low pressure chemical vapor deposition has been found to be suitable. A Plasma-I type deposition reactor made by Applied Materials, Inc. of Santa Clara, California is a suitable plasma assisted oxide deposition apparatus. Typical depositions were performed with the substrate wafer support heated to about 300°C. Thickness 14a of layer 14 in the range 0.05-0.4 microns is useful with 0.1-0.2 microns being preferred. When thickness 14a was above about 0.4 microns, cracking of dielectric layer 14 was observed following a 400°C to room temperature thermal shock test.
  • Second dielectric layer 15 is formed by a different method and material.
  • Dielectric layer 15 is formed using a spun-on glass material.
  • Spun-on glasses consist, typically, of silica bearing glass materials which are suspended in an organic carrier.
  • substrate 11 is, for example, a semiconductor or other wafer
  • a drop of the glass-carrier mixture having a predetermined viscosity is placed on the center of the wafer and the wafer rotated at high speed. This causes the glass-carrier mixture to spread out in a thin film.
  • one of the properties of such spun-on materials is that where the surface topography of the substrate is irregular, the spun-on material does not conformally coat the surface, that is, the thickness of the spun-on layer is not uniform. As illustrated in FIG.
  • spun-on glass layer 15 tends to accumulate in regions 15b at the edges of surface discontinuities so that the slope of layer 15 over such surface steps or discontinuities is substantially reduced. This provides a smoothing action which contributes to improved planarization of the surface.
  • the spun-on glass be arsenic doped, however phosphorous doped or undoped spun-on glasses can also be used.
  • the arsenic doped glass shows greater resistance to cracking and better survives thermal shock.
  • a small quantity of the arsenic doped glass-carrier mixture was placed, on a silicon semiconductor wafer and spun at approximately 3000 RPM to form a thin layer. The spun- on layer was baked at about 450°C for one hour to form glass layer 15.
  • spun-on layer 15 provides a substantial smoothing action in regions 15b even though it amounts to only a relatively small fraction of the total thickness of interlayer 18.
  • Dielectric layer 16 is preferably formed by plasma assisted deposition or chemical vapor deposition. It has been found that deposited silicon dioxide is suitable. Layer 16, when formed of deposited silicon dioxide may be doped with 0-4 percent phosphorous. It is desirable that layer 16 be formed at a temperature less than that used in the formation of layer 15. A four percent phosphorous doped silicon dioxide layer was typically deposited by LPCVD from a mixture of silane and oxygen at 360°C. Other higher or lower temperatures may be used provided they are less than th-e temperature used for the formation of layer 15.
  • Thickness 16a of layer 16 is desirably several times greater than either thickness 14a or 15a, being adjusted so that total thickness 18a of layer 18 is sufficient to provide the desired degree of electrical isolation.
  • thickness 18a is conveniently in the range of about 0.8 to 1.6 microns and thickness 16a is typically in the range 0.6-1.0 microns.
  • Conductor 17 is then applied over the top of dielectric 16.
  • Conductor 17 may be of any suitable conductor material such as, but not limited to, metals, semiconductors, semi-metals, intermetallics, or composites thereof. Aluminum and/or aluminum (98%) - Copper (1%) - Silicon (1%) alloy were used with excellent results.
  • adhesion layer 14 is essential to obtaining a high manufacturing yield in forming multi-layer conductor structures employing spun- on glasses. If layer 14 is not used, and spun-on glass layer 15 is located directly on conductor 13a, then a significant manufacturing yield loss due to delamination between conductor 13a and spun-on glass 15 is found to occur. This is particularly severe when conductor 13a is formed of aluminum or Al-Cu-Si alloy.
  • dielectric layer 14 formed for example, by plasma deposition or low pressure chemical vapor deposition of silicon oxide, excellent adhesion both to conductor layer 13a and spun-on glass layer 15 is obtained.
  • the completed structure showed no delamination when thermally shocked by heating the wafer to 400°C and then quickly placing it on a room temperature metal block to provide rapid cooling. The delamination effect is entirely overcome and the manufacturing yield is substantially improved.
  • Layer 16 is also essential. If layer 16 is omitted, then delamination is observed between spun-on glass layer 15 and second conductor layer 17. While dielectric layer 16 may be formed by the same general methods as used for layer 14, it has been found particularly convenient to use low temperature, low pressure chemical vapor deposition (LPCVD) of a phosphorous doped silicon oxide for layer 16. Typical conditions are deposition of a 0-4 percent phosphorous doped silicon oxide at temperatures in the range 300- 400°C from a mixture of silane and oxygen at low pressure. LPCVD is a technique well known in the art. The phosphorous doped silicon oxide may be readily etched using means well known in the art to provide through-holes with tapered sides.
  • LPCVD low temperature chemical vapor deposition
  • layers 14-15 are substantially thinner than layer 16, undercutting of layers 14-15 during etching of through-holes through layer 18 is reduced.
  • Reactive ion etching using a thickness tapered resist mask is a preferred method for achieving tapered through-holes.
  • the above-described means and methods provide structures which exhibit excellent step coverage, which are substantially free of delamination between the conductors and the dielectric interlayer, and which permit etching of tapered through- holes.
  • plasma deposited oxide or “plasma oxide” refer to formation methods for dielectric passivation layers which use gas plasma and/or gas discharge reactions to form dielectric films such as, for example, but not limited to, plasma assisted chemical vapor deposition.
  • the invention has been illustrated for the situation where aluminum or aluminum alloy has been used as the metallization. It will be readily apparent to those of skill in the art, that other conductors can also be used. Accordingly it is intended to include these and other variations that are within the spirit and scope of the present invention in the claims which follow.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

Organes et procédés améliorés de production de dispositifs éléctroniques métalliques multicouches (10) dans lesquels le diélectrique intermétallique (18) se compose d'un sandwich comportant trois couches. La première couche métallique (13) est recouverte d'une couche diélectrique (14) obtenue par dépôt d'oxyde au plasma ou par dépôt de vapeur chimique à basse pression. Cette première couche diélectrique (14) est recouverte d'une deuxième couche diélectrique (15) obtenue par filage de verre sur la première couche. La troisième couche diélectrique (16) est formée par dépôt de vapeur chimique ou par dépôt au plasma et est ensuite recouverte de la deuxième couche métallique (17). Ce procédé permet d'améliorer sensiblement le revêtement par étape et d'empêcher le décollement interlaminaire entre la couche diélectrique intermétallique (18) et les couches métalliques (13, 17). La couche diélectrique peut être usinée de manière à présenter des trous de contact côniques.
EP19860905550 1985-11-04 1986-08-25 Dielectrique intermetallique en verre Pending EP0245290A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US79480485A 1985-11-04 1985-11-04
US794804 1997-02-04

Publications (1)

Publication Number Publication Date
EP0245290A1 true EP0245290A1 (fr) 1987-11-19

Family

ID=25163729

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19860905550 Pending EP0245290A1 (fr) 1985-11-04 1986-08-25 Dielectrique intermetallique en verre

Country Status (2)

Country Link
EP (1) EP0245290A1 (fr)
WO (1) WO1987002828A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6388751B1 (en) 1996-09-11 2002-05-14 John Ernest Foster Holley Apparatus for determining optical properties of liquid samples

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JPH088265B2 (ja) * 1988-09-13 1996-01-29 株式会社東芝 化合物半導体装置とその製造方法
CA2006174A1 (fr) * 1989-12-20 1991-06-20 Luc Ouellet Methode de fabrication de films isolants sans craquelures au moyen de couches intermediaires de verre de spin
KR940005723B1 (ko) * 1990-05-08 1994-06-23 니뽄 덴끼 가부시끼가이샤 반도체 장치
KR920015542A (ko) * 1991-01-14 1992-08-27 김광호 반도체장치의 다층배선형성법
US5317192A (en) * 1992-05-06 1994-05-31 Sgs-Thomson Microelectronics, Inc. Semiconductor contact via structure having amorphous silicon side walls
JPH07297276A (ja) * 1992-09-22 1995-11-10 At & T Corp 半導体集積回路の形成方法
KR19980055721A (ko) * 1996-12-28 1998-09-25 김영환 반도체 소자의 보호막 형성 방법

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JPS542070B2 (fr) * 1971-10-01 1979-02-01
JPS4879987A (fr) * 1972-01-28 1973-10-26
JPS5121753B2 (fr) * 1972-02-09 1976-07-05
JPS5425178A (en) * 1977-07-27 1979-02-24 Fujitsu Ltd Manufacture for semiconductor device
JPS5747711A (en) * 1980-08-08 1982-03-18 Fujitsu Ltd Chemical plasma growing method in vapor phase
JPS57176746A (en) * 1981-04-21 1982-10-30 Nippon Telegr & Teleph Corp <Ntt> Semiconductor integrated circuit and manufacture thereof
DE3228399A1 (de) * 1982-07-29 1984-02-02 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen einer monolithisch integrierten schaltung
US4451326A (en) * 1983-09-07 1984-05-29 Advanced Micro Devices, Inc. Method for interconnecting metallic layers
US4499653A (en) * 1983-11-03 1985-02-19 Westinghouse Electric Corp. Small dimension field effect transistor using phosphorous doped silicon glass reflow process
US4535528A (en) * 1983-12-02 1985-08-20 Hewlett-Packard Company Method for improving reflow of phosphosilicate glass by arsenic implantation
JPS60132344A (ja) * 1983-12-20 1985-07-15 Nec Corp 半導体装置
CA1213075A (fr) * 1984-06-15 1986-10-21 Jacques S. Mercier Methode simplifiant les etapes de fabrication des couches dielectriques dans les circuits integres a tres grande echelle

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6388751B1 (en) 1996-09-11 2002-05-14 John Ernest Foster Holley Apparatus for determining optical properties of liquid samples

Also Published As

Publication number Publication date
WO1987002828A1 (fr) 1987-05-07

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