CA2006174A1 - Methode de fabrication de films isolants sans craquelures au moyen de couches intermediaires de verre de spin - Google Patents

Methode de fabrication de films isolants sans craquelures au moyen de couches intermediaires de verre de spin

Info

Publication number
CA2006174A1
CA2006174A1 CA 2006174 CA2006174A CA2006174A1 CA 2006174 A1 CA2006174 A1 CA 2006174A1 CA 2006174 CA2006174 CA 2006174 CA 2006174 A CA2006174 A CA 2006174A CA 2006174 A1 CA2006174 A1 CA 2006174A1
Authority
CA
Canada
Prior art keywords
layer
deposited
sog
dielectric
spin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA 2006174
Other languages
English (en)
Inventor
Luc Ouellet
Abdellah Azelmad
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsemi Semiconductor ULC
Original Assignee
Mitel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitel Corp filed Critical Mitel Corp
Priority to CA 2006174 priority Critical patent/CA2006174A1/fr
Priority to PCT/CA1990/000448 priority patent/WO1991009422A1/fr
Publication of CA2006174A1 publication Critical patent/CA2006174A1/fr
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/02—Optical fibres with cladding with or without a coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
CA 2006174 1989-12-20 1989-12-20 Methode de fabrication de films isolants sans craquelures au moyen de couches intermediaires de verre de spin Abandoned CA2006174A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CA 2006174 CA2006174A1 (fr) 1989-12-20 1989-12-20 Methode de fabrication de films isolants sans craquelures au moyen de couches intermediaires de verre de spin
PCT/CA1990/000448 WO1991009422A1 (fr) 1989-12-20 1990-12-19 Procede de fabrication de films isolants sans craquelures avec couche intermediaire en verre sog

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA 2006174 CA2006174A1 (fr) 1989-12-20 1989-12-20 Methode de fabrication de films isolants sans craquelures au moyen de couches intermediaires de verre de spin

Publications (1)

Publication Number Publication Date
CA2006174A1 true CA2006174A1 (fr) 1991-06-20

Family

ID=4143846

Family Applications (1)

Application Number Title Priority Date Filing Date
CA 2006174 Abandoned CA2006174A1 (fr) 1989-12-20 1989-12-20 Methode de fabrication de films isolants sans craquelures au moyen de couches intermediaires de verre de spin

Country Status (2)

Country Link
CA (1) CA2006174A1 (fr)
WO (1) WO1991009422A1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2017720C (fr) * 1990-05-29 1999-01-19 Luc Ouellet Verre centrifuge comprenant une couche de finition protectrice resistante a l'humidite.
CA2056456C (fr) * 1991-08-14 2001-05-08 Luc Ouellet Passivation haute performance pour la fabrication de dispositifs a semiconducteur
US5371046A (en) * 1993-07-22 1994-12-06 Taiwan Semiconductor Manufacturing Company Method to solve sog non-uniformity in the VLSI process
EP0655776A1 (fr) * 1993-11-30 1995-05-31 STMicroelectronics S.r.l. Procédé d'autoplanarisation pour la passivation d'un circuit intégré
US5503882A (en) * 1994-04-18 1996-04-02 Advanced Micro Devices, Inc. Method for planarizing an integrated circuit topography
JP3226816B2 (ja) * 1996-12-25 2001-11-05 キヤノン販売株式会社 層間絶縁膜の形成方法、半導体装置及びその製造方法
KR100914443B1 (ko) * 2007-09-04 2009-08-28 후지쯔 마이크로일렉트로닉스 가부시키가이샤 반도체 장치 및 그 제조 방법
JP6323278B2 (ja) * 2014-09-19 2018-05-16 株式会社デンソー 半導体物理量センサおよびその製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5747711A (en) * 1980-08-08 1982-03-18 Fujitsu Ltd Chemical plasma growing method in vapor phase
WO1987002828A1 (fr) * 1985-11-04 1987-05-07 Motorola, Inc. Dielectrique intermetallique en verre

Also Published As

Publication number Publication date
WO1991009422A1 (fr) 1991-06-27

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