CA2006174A1 - Method of making crack-free insulating films with sog interlayer - Google Patents

Method of making crack-free insulating films with sog interlayer

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Publication number
CA2006174A1
CA2006174A1 CA 2006174 CA2006174A CA2006174A1 CA 2006174 A1 CA2006174 A1 CA 2006174A1 CA 2006174 CA2006174 CA 2006174 CA 2006174 A CA2006174 A CA 2006174A CA 2006174 A1 CA2006174 A1 CA 2006174A1
Authority
CA
Grant status
Application
Patent type
Prior art keywords
layer
method
deposited
sog
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA 2006174
Other languages
French (fr)
Inventor
Luc Ouellet
Abdellah Azelmad
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsemi Semiconductor ULC
Original Assignee
Microsemi Semiconductor ULC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS, OR APPARATUS
    • G02B6/00Light guides
    • G02B6/02Optical fibre with cladding with or without a coating
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819Smoothing of the dielectric
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

ABSTRACT OF THE DISCLOSURE

A method of fabricating a semiconductor device is disclosed wherein a first dielectric layer is applied over an interconnect layer having tracks defining a conductive pattern, the first dielectric layer forming valleys between the tracks of the interconnect layer, spin-on glass is applied over said first layer to planarize it by forming spin-on glass zones in the valleys defined by the first dielectric layer, and a second layer is applied to the planarized first layer, whereby the first and second layers and said spin-on glass zones form a composite multi-layer film. The first layer is formed such that it has compressive stress at room temperature to prevent cracking in the composite multi-layer film during subsequent heat treatment.
The second layer can be another dielectric layer or a further interconnect layer applied directly to the first layer and SOG planarization layer. The method can also be applied to other fields, such as the manufacture of optical fibers, emission diodes and the like.

Description

This invention relates to method of making crack-free insulating films comprising a Spin-on glass (SOG) layer, and insulating films made thereby.

Spin-on glasses (SOG) are proprietary liquid solutions containing siloxane or silicate based monomers diluted in various kinds of solvents or alcohols. During coating and curing, monomers are polymerized by condensation and release water, solvent, and alcohol. The condensed material is a thin solid film having mechanical, chemical and electrical properties which depend on the starting composition, and the coating and curing process. A good starting solution can give bad results if the coating and curing sequence is not optimized.

There are more than one hundred different SOG solutions on the market. They are classified into two major families:
~;, 1) Siloxanes (methyl-, ethyl-, phenyl-, butyl-, doped or undopedl. ti 2) Silicates (doped or undoped).
`~' Planarization is the filling in of the trenches and crevices formed when a plurality~of layers, some of which might be subsequently etched back, are deposited on a substrate.
, . .
Planarization is used over polysilicon, refractory metals, polycides, silicides, aluminum and aluminum alloys, copper, and gold or otehr conduc~tive materials. The main goal is to smooth/eliminate steps and enhance step coverage by the dielectrics and interconnects. Planarization technology becomes increasingly important when the scale of integrated circuits is in the micron and submicron region. Of the many dielectric planarization techniques, SOG planarization is a particularly attractive~method; it i5 relatively simple, economical and is capable of high throughput.

.~

20~617~

Unfortunately, the purely inorganic silicate SOGs are prone to cracking, which has limited their usefulness in semiconductor and similar applications, especially where they have to undergo subsequent heat treatment. While the quasi-inorganic siloxane SOGs have a more ~lexible structure due tothe presence of organic radicals, which prevent complete cross-linking of the SioxCyHz matrix under condensation, the organic radicals are not stable at high temperatures and are not compatible with oxygen plasma photoresist strippers (which tend to transform the quasi-inorganic SOG to a purely inorganic SOG by burning the organic bonds and producing volatile species like H20, CXOyHz, and silanol Si-oH). These two drawbacks, among others, limit the use of the quasi-inorganic siloxanes as an alternative to the silicates.

SOG planarization can take three forms:

1) Complete etchback.
2) Partial etchback.

3) Non etchback.

Total etchback and partial etchback processes for planarization of dielectrics over aluminum use photoresist, polyimide, or flexible quasi-inorganic SOGs. In those two cases, cracking of the dielectric sandwich does not occur since most of the planarizing material is removed from the wafer. `;

Major manufacturing restrictions of the complete/partial etchback techniques impose the non-etchback approach as the preferred technique in a production environment. In this approach, SOG becomes a permanent part of the dielectric.
Non-etchback silicate SOG planarization of dielectrics over polysilicon, polycides, refractory metals or silicides has been used for about three years. This technique is not particularly demanding f~or the dielectric sandwich because the coefficient of thermal expansion of the materials is much 20C3~17~

lower than for aluminum and aluminum alloys. The dielectric sandwich does not normally crack over those materials.

Non-etchback SOG planarization of dielectrics over aluminum alloys is an extremely new process in the semiconductor industry. Unfortunately, the use of purely inorganic SOG
forms dielectric sandwiches which are prone to very bad cracking. Consequently, more flexible quasi-organic SOGs have been tried for this application, but this approach has proved to be questionable because of an important field inversion problem due to the effect of the hydrogen contained in the organic bonds of the quasi-inorganic SOGs on the characteristics of CMOS semiconductor devices.

SOG film properties arelof prime importance. Since SOG is generally a more porous~material, when compared to LPCVD, APCVD, LACVD, PACVD or PECV~ oxides, it is more prone to water absorption. This~,water absorption reduces the bulk resistivity of the SOG and increases the power consumption of the semiconductor device due to current leakage between adjacent tracks of interconnect. For this reason, among others, SOG must not come into direct contact with the tracks and must be sandwiched between two denser LPCVD, APCVD, LACVD, PACVD or PECVD dielectric films.

Interconnections betwe~n upper and lower tracks by the use of contacts or vias are ne~essary, and the SOG is then in direct contact with the interc~nnects at those locations. If too much water is present in the SOG (or if water is generated in the quasi-inorganic SOGIlduring photoresist stripping, after vias/contact patterningl, problems such as via poisoning can occur. One way to prevent via poisoning is to use a dense and purely inorganic SOG, which is not degraded by photoresist strippers. ~j~For this reason as well silicate SOGs are preferred, but the formation of microcracks discussed above, especially during subsequent heat treatments, has limited their usefulness.

20~)61~4 It has previously been thought that the formation of microcracks in the SOG layer was an unavoidable consequence of the brittle nature of the SOG material. For example.
Japanese patent publication no. 63-021837 seeks to avoid the cracking that occurs in the SOG film during the vitrifying step by coating with SOG under reduced pressure. JP 62-046533 seeks to avoid cracking in the SOG film by pressing the SOG solution with a heating plate during solidification of the SOG layer. There has thus been a tendency to abandon altogether SOGs for planarization purposes despite their otherwise attractive properties in terms of simplicity, economy and high throughput.
:j~
It has now been discovered in accordance with the invention that the cracking that occurs in insulating films with SOG
planarization interlayers is not mainly due to cracking in the SOG layer, as previously thought, but rather primarily due to the different coefficients of expansion of the SOG, dielectric layers, and interconnect materials..
~,...
Accordingly the present~invention provides in a method of fabricating a composite~insulating film comprising first and second layers with intermediate spin-on glass zones acting as a planarization interlayer for said first layer, at least said first layer being a dielectric layer, the improvement wherein the first layerlis formed under compression to prevent cracking in the?composite film during subsequent heat treatment.
. ., The second layer can either be a second dielectric layer, or where, in the case of semiconductor fabrication, an interconnect layer is applied directly over the first and SOG
layers, the second layer can be the interconnect layer.
i The method may be applied to the fabrication of a semiconductor device wherein a f irst dielectric layer is applied over an interconnect layer having tracks defining a ~ Z006174 conductive pattern and made of material having a high coeffic:ient of expansion, the first dielectric layer forming valleys between the tracks of the interconnect layer, spin-on glass is applied over said first layer to planarize it by formincJ spin-on glass zones in the valleys defined by the first dielectric layer, and a second layer is applied to the planarized first layer, whereby said first and second layers and said spin-on glass zones form a composite multi-layer film. In the method the~first layer is formed under compression to prevent cracking in the composite multi-layer film during subsequent heat treatment.
, The invention will now be described in more detail, by way of example only, with reference to the accompanying drawings in which:-Figures la to lh illustrate the steps in the manufacture of acomposite insulating film with a SOG interlayer.

First a layer of aluminùm interconnect material 1 (Fig. la) is deposited on the substrate and then patterned using photolithography (Fig. lb). A first layer of dielectric 2 is deposited over the etched interconnect tracks (Fig. lc) and a spin-on glass (SOG) layer 3 applied (with or without etchback) to fill the valleys and crevices (Fig. ld). The SOG is a proprietary composition and can be obtained from a number of sources such as Allied Signal Inc, Milpitas, California. Being liquid, the SOG is almost absent over the peaks la and provides good planarization for the first dielectric layer 2. ,' A second dielectric layer 4 is applied over the first layer 2 and SOG interlayer 3 (Fig. le). Contacts holes are then etched away to reach the tracks of the first layer of interconnect material lr(fig. lf). A second level of interconnect material 5-jis deposited over the etched second ,' r .~ .

ZO~174 layer 4 (fig lf) and is patterned using photolithography to form the desired conductive tracks 5a (Fig. lh).
!l Such dielectric sandwiches containing dense purely inorganic (silicate) SOG crack during the heat treatments which are needed to cure and stabilize the SOG and the aluminum alloys.

These cracks in the dielectric sandwiches cause the device to fail due to electrical shorts between adjacent tracks of the same level of interconnect (intralevel short), or between tracks of two independent levels of interconnect (interlevel shorts). This property has limited the use of the purely inorganic SOGs (silicates) and some quasi-inorganic SOGs (siloxanes) for dielectric planarization applications.

Thin film stress can be compressive or tensile. A
compressive stress, when too excessive, results in delamination, formationtf waves and ripples. A film in compression does not crack. In fact, a film in compression stops the propagation of cracks. A tensile stress, when too excessive, results in crack formation and propagation.

When a stressed film is deposited on a substrate, it induces a mechanical bow of th ~ substrate. The bow direction and its magnitude is related to the stress type (tensile or compressive), and its intensity. If the film is in tension, the substrate bows in stch a way that the film is present on the concave face. Similarly, if the film is under compression the substrate bows in such a way that the film is present on the convex face. The stress nature of a given thin film can then be measured by the change of curvature induced in a (100) Si slngle crystal wafer, due to the deposited film.
h~
Using a laser optical lever, the wafer is scanned before and after the deposition to~,lobtain the net change or wafer radius ~00~174 of curvature. The film stress "a" is calculated using the following expression:

a = [Et2]/[6(1-~)rr]

where "E" is the Young's modulus of Si (100~ wafer, "~" is its Poisson's ratio, "t" is the wafer thickness, "r" is the measured net radius of curvature, and "r" is the film thickness.

Such stress measurements were performed on various purely inorganic (silicates) SOGs. A (6-8) x 108 dyne/cm2 tensile stress was measured. This tensile stress is the result of the solid phase volumetric shrink of the SOG during its condensation:

siot(oc2H5)u~oH)v + WH20 -> sioXHy + ZH20 + bC2H50H
Water (H2O) and ethanol (C2H5OH) by-products are released and contribute to an increase of the internal stress.

The SOG stress obtained is not excessively high but the obtained material is very rigid. Although it was not possible to measure the actual coefficient of thermal expansion of the obtained SOG, the appearance of cracks at high temperature in the dielectric sandwich PSG/SOG/PSG (PSG
stands for a 4.0 wt% phosphorus doped LPCVD sio2 film which is under a tensile stress of 0.5 - 3.0 x 109 dyne/cm2, up to four times higher than SOG), deposited over metal tracks of the first level of interconnect, and the absence of cracks in the dielectric sandwich PSG/PSG deposited over equivalent metal tracks, indicates that the SOG has a much smaller coefficient of thermal expansion than PSG.
.:
It is not, as previously thought, a high stress in the SOG
which causes the appearance of cracks, but rather its lower coefficient of thermal expansion. The cracks appear in the .,~ .

2006174`

dielectric sandwich around and over the metal I tracks and propagate easily through the dielectric layers, which are already in tensile stress. Since aluminum inherently has a very high coefficient of thermal expansion, when compared to PSG and particularly SOG, the problem is important, especially in view of the subsequent heat treatments that are required.

The dielectric sandwich cracking has been substantially eliminated with a special combination of film stresses.

The first dielectric layer 1 deposited over the aluminum and under the SOG film must be under compressive stress. In that case, the heat treatments that cause expansion of the aluminum will tend to bring the dielectric under tension.
But since the dielectric is already in compression, its stress will stabilize at an almost negligible value. A
stress of about 5 x 108 to 3 x 109 dyne/cm2 is preferred and its exact value depends on the difference of the coefficient of thermal expansion between the aluminum alloy and the dielectrics used in the sandwich.

The SOG layer has a stress that is slightly tensile at about 6 - 8 x 108 dynes/cm2. IThe last dielectric layer 4 deposited over the SOG layer 3 and under the second interconnect layer 5 can be under compressive or tensile stress, but a tensile stress is preferred to compensate for the wafer bow generated by the first dielectric. A stress of about 5 x 108 to 3 x 109 dyne/cm2 is preferred.

Stress measurements have been performed on various different dielectrics to find one that has the needed compressive stress. A specially designed undoped LPCVD SioXHv (SG) gives the desired behaviour, namely a compressive stress of 2 x 109 dyne/cm2. A sandwich composed of 600 nm SG/200 nm SOG/600 nm PSG can theoretically be crack free.

- Z0C)6i74 Example An experiment was performed to compare the standard PSG/SOG/PSG sandwich with the designed SG/SOG/PSG sandwich.
For the experiment, an equal number of blanket aluminum deposited wafers and real patterned device wafers were used to deposit 600 nm of PSG or 600 nm of the special SG. Then, all the wafers were coated with SOG and heat treated.
Finally, another 600 nm of PSG was deposited on the top of the SOG, and heat treatments were performed to check for cracking.

All wafers with PSG/SOG/PSG sandwich were completely cracked.
The PSG/SOG/PSG covered blanket aluminum deposited silicon wafers were randomly cracked. The PSG/SOG/PSG covered wafers with patterns showed cracks that were limited to the area over the aluminum lines of the first level of interconnect, indicating that the coefficient of thermal expansion of SOG
is really the underlying cause of the dielectric sandwich cracking.

All wafers with SG/SOG/PSG sandwich were completely crack-free. Even the SG/SOG/PSG covered blanket aluminum deposited silicon wafers were absolutely crack-free. This proves the effectiveness of having a compressive pre-stressed film under the SOG to compensate for its low coefficient of thermal expansion.

The described method is very important because it permits a non-etchback high quality purely inorganic SOG process to be applied to high coefficient of thermal expansion materials, such as aluminum alloys.

There are a number of ways of achieving the desired compressive stress. Examples are as follows: ;~
' Low Pressure Chemical Vapour Deposition (LPCVD) Plasma Enhanced Chemical Vapour Deposition (PECVD) Laser Assisted Chemical Vapour Deposition (LACVD) Photochemical Chemical Vapour Deposition (PhCVD) Atmospheric Pressure Chemical Vapour Deposition ~APCVD) ~ Bias Sputtering (BS) Thermal oxidation Spin-on deposition Electron Cyclotron Resonance (ECR), biased or otherwise.

The deposited compressive material under the SOG can be:

Silicon nitride, stochiometric or not, with or without H, Cl, F
Polyimide or other mechanically deposited organic dielectric Silicon dioxide, oxynitride, stochiometric or not, with or without H, Cl, F
Above-mentioned materials doped/alloyed with As, P, B, Pb, or other metallic elements, or their combinations.

The layer 4 over the SOG layer 3 need not be under tension but also can be under compression.

The SOG can be of many types. The crack prevention effect is much more pronounced with low coefficient of thermal expansion inorganic (silicates) SOGs.

The interconnsct material under the SOG can be other than aluminum or aluminum alloy. For example, it can be a metal such as W, Mo, Ta, Co, Ti; or a reacted metal such as TiXNyl TiXWy, TixovZz, TixWvNz. It can also be a silicide of W, Mo, Ta, Co, Ti, Pt.

~:0(~61~4 ~`

The upper part of the dielectric sandwich can be omitted and the second metal layer 5 directly deposited over the SOG
layer 3 and first dielectric layer 2.

The described process has many applications. In particular, it can be applied to other steps in the manufacture of integrated circuits, such as:

Planarization Diffusion source Dielectric layer Diffusion barrier Encapsulation Adhesion layer Buffer layer Antireflective layer Corrosion protection layer Etc.

It can also be applied to other semiconductor devices, such as: ;
. .
Emission diodes Liquid crystal displays Electro chromic displays `
Photodetectors Solar batteries Sensors In other fields, the process may be useful in the fabrication of: .

Optical fibers `
Corrosion protection :~
Adhesion promoters ~i Friction reduction coatings Optical/thermal reflectance adjustment coatings .:

Claims (35)

1. In a method of fabricating a composite insulating film comprising first and second layers with intermediate spin-on glass zones acting as a planarization SOG interlayer for said first layer, at least said first layer being a dielectric layer, the improvement wherein the first layer is formed under compression to prevent cracking in the composite film during subsequent heat treatment.
2. A method as claimed in claim 1, wherein said first layer is formed under a compressive stress of about 5 x 108 to 5 x 109 dynes/cm2.
3. A method as claimed in claim 2, wherein said SOG
interlayer is formed under a slightly tensile stress of about 3 x 108 dynes/cm2.
4. A method as claimed in claim 3, wherein said second layer is formed under a compressive stress of about 5 x 108 to 5 x 109 dynes/cm2.
5. A method as claimed in claim 4, wherein said first layer comprises siOxHy (SG).
6. A method as claimed in claim 5, wherein said second layer comprises PSG.
7. A method as claimed in claim 6, wherein said first layer and/or second layer is deposited by LPCVD (Low Pressure Chemical Vapour Deposition).
8. A method as claimed in claim 6, wherein said first layer and/or second layer is deposited by Plasma Enhanced Chemical Vapour Deposition (PECVD).
9. A method as claimed in claim 6, wherein said first layer and/or second layer is deposited by Laser Assisted Chemical Vapour Deposition (LACVD).
10. A method as claimed in claim 6, wherein said first layer and/or second layer is deposited by Photochemical Chemical Vapour Deposition (PhCVD).
11. A method as claimed in claim 6, wherein said first layer and/or second layer is deposited by Atmospheric Pressure Chemical Vapour Deposition (APCVD).
12. A method as claimed in claim 6, wherein said first layer is deposited by Bias Sputtering (BS).
13. A method as claimed in claim 6, wherein said first layer and/or second layer is deposited by Spin-on deposition.
14. A method as claimed in claim 6, wherein said first layer and/or second layer is deposited by Electron Cyclotron Resonance (ECR), biased or otherwise.
15. A method as claimed in claim 4, wherein said first layer and/or second layer comprises silicon nitride, stochiometric or not, with or without H, Cl, F.
16. A method as claimed in claim 4, wherein said first layer and/or second layer comprises polyimide or other mechanically deposited organic dielectric.
17. A method as claimed in claim 4, wherein said first layer and/or second layer comprises silicon dioxide, oxynitride, stochiometric or otherwise, with or without H, Cl, F.
18. A method as claimed in claim 4, wherein said first layer and/or second layer comprises materials as claimed in any of claims 15 to 18 doped/alloyed with As, P, B, Pb, or other metallic elements, combinations thereof.
19. In a method of fabricating a semiconductor device wherein a first dielectric layer is applied over an interconnect layer having tracks defining a conductive pattern and made of material having a high coefficient of expansion, the first dielectric layer forming valleys between the tracks of the interconnect layer, spin-on glass is applied over said first layer to planarize it by forming spin-on glass zones in the valleys defined by the first dielectric layer, and a second layer is applied to the planarized first layer, whereby said first and second layers and said spin-on glass zones form a composite multi-layer film, the improvement wherein said first layer is formed under compression to prevent cracking in the composite multi-layer film during subsequent heat treatment.
20. A method as claimed in claim 19, wherein said second layer is a dielectric layer.
21. A method as claimed in claim 19, wherein said second layer is an interconnect layer deposited directly onto said first layer planarized with said SOG interlayer.
22. A method as claimed in claim 19, wherein said SOG
interlayer is formed under a slightly tensile stress of about 5 x 108 dynes/cm2.
23. A method as claimed in claim 22, wherein said second layer is formed under a compressive stress of about 5 x 108 to 3 x 109 dynes/cm2.
24. A method as claimed in claim 23, wherein said first layer comprises SiOxHy (SG).
25. A method as claimed in claim 23, wherein said second layer comprises PSG.
26. A method as claimed in claim 25, wherein said first layer is deposited by LPCVD (Low Pressure Chemical Vapour Deposition).
27. A method as claimed in claim 25, wherein said first layer is deposited by Plasma Enhanced Chemical Vapour Deposition (PECVD).
28. A method as claimed in claim 19, wherein said tracks are made of aluminum or aluminum alloy.
29. A method as claimed in claim 19, wherein said tracks are made of material selected from the group consisting of: W, Mo, Ta, Co, Ti: or a reacted metal such as TixNy, TixWy, TixOvZz, TixWvNz; or a silicide of W, Mo, Ta, Co, Ti, Pt.
30. A composite insulating film comprising first and second layers with intermediate spin-on glass zones acting as a planarization SOG interlayer for said first layer, at least said first layer being a dielectric layer, the improvement wherein the first layer is formed under compression to prevent cracking in the composite structure during subsequent heat treatment.
31. A composite insulating film as claimed in claim 30, wherein said first layer comprises SiOxHy (SC).
32. A composite insulating film as claimed in claim 30, wherein said first layer comprises silicon nitride, stochiometric or otherwise, with or without H, Cl, F.
33. A composite insulating film as claimed in claim 30, wherein said first layer comprises polyimide or other mechanically deposited organic dielectric.
34. A composite insulating film as claimed in claim 30, wherein said first layer comprises silicon dioxide, oxynitride, stochiometric or otherwise, with or without H, Cl, F.
35. A composite insulating film as claimed in claim 30, wherein said first layer comprises materials as claimed in any of claims 31 to 34 doped/alloyed with As, P, B, Pb, or other metallic elements, combinations thereof.
CA 2006174 1989-12-20 1989-12-20 Method of making crack-free insulating films with sog interlayer Abandoned CA2006174A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CA 2006174 CA2006174A1 (en) 1989-12-20 1989-12-20 Method of making crack-free insulating films with sog interlayer
PCT/CA1990/000448 WO1991009422A1 (en) 1989-12-20 1990-12-19 Method of making crack-free insulating films with sog interlayer

Publications (1)

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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2017720C (en) * 1990-05-29 1999-01-19 Luc Ouellet Sog with moisture-resistant protective capping layer
CA2056456C (en) * 1991-08-14 2001-05-08 Luc Ouellet High performance passivation for semiconductor devices
US5371046A (en) * 1993-07-22 1994-12-06 Taiwan Semiconductor Manufacturing Company Method to solve sog non-uniformity in the VLSI process
EP0655776A1 (en) * 1993-11-30 1995-05-31 SGS-THOMSON MICROELECTRONICS S.r.l. Autoplanarizing process for the passivation of an integrated circuit
US5503882A (en) * 1994-04-18 1996-04-02 Advanced Micro Devices, Inc. Method for planarizing an integrated circuit topography
JP3226816B2 (en) * 1996-12-25 2001-11-05 キヤノン販売株式会社 Method of forming an interlayer insulating film, a semiconductor device and a manufacturing method thereof
KR100914443B1 (en) * 2007-09-04 2009-08-28 후지쯔 마이크로일렉트로닉스 가부시키가이샤 Semiconductor device and process for producing the same
JP6323278B2 (en) * 2014-09-19 2018-05-16 株式会社デンソー The semiconductor physical quantity sensor and a manufacturing method thereof

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JPS625230B2 (en) * 1980-08-08 1987-02-03 Fujitsu Ltd
WO1987002828A1 (en) * 1985-11-04 1987-05-07 Motorola, Inc. Glass intermetal dielectric

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WO1991009422A1 (en) 1991-06-27 application

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