EP0154573B1 - Procédé de planarisation pour semi-conducteurs et structures fabriquées selon ce procédé - Google Patents

Procédé de planarisation pour semi-conducteurs et structures fabriquées selon ce procédé Download PDF

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Publication number
EP0154573B1
EP0154573B1 EP85400163A EP85400163A EP0154573B1 EP 0154573 B1 EP0154573 B1 EP 0154573B1 EP 85400163 A EP85400163 A EP 85400163A EP 85400163 A EP85400163 A EP 85400163A EP 0154573 B1 EP0154573 B1 EP 0154573B1
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EP
European Patent Office
Prior art keywords
accordance
planar surface
glass
layer
pattern
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Expired - Lifetime
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EP85400163A
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German (de)
English (en)
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EP0154573A2 (fr
EP0154573A3 (en
Inventor
Greg Burton
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Fairchild Semiconductor Corp
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Fairchild Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG

Definitions

  • the present invention relates generally to a planarization process, and more particularly, to such a process for use in the manufacture of semiconductor structures.
  • the LOCOS technique provides a simple and effective means to dielectrically isolate semiconductor integrated circuits
  • use of this technique typically results in a topographical surface which is non-planar.
  • the resulting non-planar structure on the surface is referred to as a "bird's head".
  • Such a non-planar surface is undesirable for high density applications where the non-planar surface is further processed to include additional structure, e.g., metallization, thereon.
  • additional structure e.g., metallization
  • a general object of the present invention is to provide an improved planarization process.
  • Another object of the present invention is to provide such a process which does not require the use of a dry etch.
  • Another object of the present invention is to provide such a process which can be easily added to a conventional semiconductor fabrication procedure.
  • Another object of the present invention is to provide improved semiconductor structures made by such process.
  • US-A-4 039 359 teaches a planarizing process wherein a liquid, identified by its trade name, is spun onto a field oxidized substrate whereby the spinning results in planarization of the liquid surface. A following heat treatment dries the solution and the dry contents is transformed into silicon dioxide. Thereafter, a wet etching step follows.
  • EP-A-0 060 784 teaches a germanosilicate glass and its application in the production of semiconductor structures so as to cover the surface of a device provided with an aluminum interconnect pattern.
  • the invention in contrast, teaches wet etching of two different materials in one single process step. This allows to select either a planarization process to be implemented or a process by which only a degree of planarization is achieved using a fast and more economical etch process.
  • Figure 1 is a partially sectioned elevational view of a semiconductor structure having a non-planar surface in the form of a bird's head.
  • Figures 2-4 are elevational views, taken as in Figure 1, showing the structure of Figure 1 as it is processed in accordance with one form of the method of the present invention.
  • Figures 5 and 6 are elevational views, taken as in Figure 1, showing other forms of the method of the present invention in which a predetermined degree of planarity is achieved.
  • an exemplary semiconductor structure is generally designated 10.
  • the structure 10 is in the form of a substrate and includes a portion 12 of silicon and an immediately contiguous portion 14 of silicon dioxide.
  • the combined surfaces 12A and 14A presented by the silicon 12 and silicon dioxide 14 are non-planar, with the silicon dioxide 14 in the form of the well known "bird's head".
  • a relatively thin, e.g., 100 nm (1000 ⁇ ), film 16 of thermal oxide is preferably first grown on the exposed silicon surface 12A.
  • a layer 18 of electrically insulating germanosilicate glass is deposited on the film 16 and on the silicon dioxide surface 14A.
  • a preferred germanosilicate glass comprises 54% SiO2, 42% GeO2, and 4% P2O5 (hereinafter PVX-II). Glass composition, as used in this Application, is expressed as a mole percentage.
  • the layer 18 has a thickness in the range of from about 300 nm (3000 ⁇ ) to about 500 nm (5000 ⁇ ). Further information on suitable germanosilicate glasses can be found in U.S. Application Serial No. 362,322, entitled “Smooth Glass Insulating Film Over Interconnects On An Integrated Circuit", filed March 26, 1982, and assigned to the assignee of the present invention.
  • the layer 18 of electrically insulating material is planarized.
  • This planarizing step is conveniently performed through reflow thereof initiated by heat treatment.
  • heat treatment in the range of from about 850 o C to about 1100 o C for a tame period of about 30 minutes provides a satisfactory planar surface 18A.
  • the layer 18 of electrically insulating material and the bird's head portion 14 are wet etched in an etch solution such that the etch rate of the insulating material 18 and the bird's head portion 14 are substantially the same.
  • This wet etching is shown schematically in Figure 3 through the use of horizontal dashed lines. It is to be appreciated that the resulting surface, after etching, reproduces the same degree of planarity as the layer 18, subsequent to its planarization. In one form of the invention this wet etching step is terminated when the silicon surface 12A is again exposed, as shown in Figure 4.
  • a preferable wet etch solution comprises 11.8% hydrofluoric acid (49% solution), 45.4% ammonium fluoride (40% solution), and 42.7% deionized water, with the etchant maintained from about 15 o C to about 30 o C, preferably at about 20 o C.
  • Wet etch composition as used in this Application, is expressed as a volume percentage. This wet etch solution attacks the silicon dioxide 14 and PVX-II at the rate of about 100 nm (1000 ⁇ )/minute.
  • the previously described wet etching step may be terminated prior to reaching the silicon surface 12A.
  • the wet etching step may be terminated when a predetermined thickness of the bird's head 14 has been etched.
  • the remaining PVX-II layer 18 may then be conveniently and selectively removed from the silicon surface 12A by exposing the structure to a weak hydrofluoric acid solution e.g., 10:1 ratio, such that the PVX-II etch rate is substantially faster than the thermal oxide etch rate.
  • the remaining oxide layer 16 can then be removed by conventional wet etch techniques. This form of the invention may be desired in order to reduce the possibility of exposing the silicon sidewall through overetching of the thermal oxide.
  • the relative etch rates of the PVX-II and thermal oxide films can be varied to provide a desired result.
  • variation is conveniently accomplished by changing the composition of the wet etching solution.
  • the hydrofluoric acid concentration is decreased, the PVX-II etch rate becomes significantly faster than the thermal oxide etch rate.
  • the selection of the wet etch composition can be used to provide various degrees of planarization. For example, as shown in Figure 6, one application may require that only two thirds (2/3) of the bird's head 14 is to be removed.
  • the composition of the wet etch solution would be chosen to etch PVX-II at a rate which is three-halves (3/2) greater than that of the thermal oxide.
  • germanosilicate glasses include those having: SiO2 in the range of from about 5% to about 80%; GeO2 in the range of from about 10% to about 100%; and P2O5 in the range of from about 0% to about 10%.
  • hydrofluoric wet etch solution examples include those having: hydrofluoric acid in the range of from about 3% to about 30%; ammonium fluoride in the range of from about 10% to about 95%; and deionized water in the range of from about 0% to about 90%.
  • the method of the present invention can be repeated at some or all of the various levels.
  • the non-planar surface need not be in the form of a bird's head, as in the case of a thermally grown oxide but may, for example, be in the form of a deposited pattern such as that produced by a deposition of silicon dioxide through sputtering or chemical vapor deposition.
  • the method of the present invention requires little additional expense in the fabrication of semiconductors inasmuch as the preferred phosphogermanosilicate glass is formed by low temperature, e.g., 430 o C; deposition at atmospheric pressure while the planarizing heat treatment and the wet etch are routine semiconductor fabrication procedures.
  • the semiconductor structure, e.g., wafer, throughput is high inasmuch as the steps involved in the method can be easily performed simultaneously, i.e., batch processed, on a plurality of wafers.
  • the method does not require a higher degree of operator skill inasmuch as the individual steps involved are essentially classical fabrication procedures.
  • Semiconductor structures made by the method of the present invention present a uniform result across a wafer surface particularly because the planarizing layer e.g., PVX-II, is relatively thin, e.g., 400 nm (4000 ⁇ ) while the wet etch process displays acceptable uniformity, e.g., +2%, across a wafer. Also, referring to Figures 4-6, the integrity of the silicon surface 12A is preserved inasmuch as the wet etch solution is selected to be non-reactive with silicon.
  • the planarizing layer e.g., PVX-II

Claims (16)

  1. Un procédé de fabrication d'une structure semi-conductrice, comprenant les étapes qui consistent :
    (a) à fournir un substrat en silicium (10) ayant au moins une surface à peu près planaire,
    (b) à former une configuration (14,16) en dioxyde de silicium sur ladite surface planaire, ladite configuration comprenant au moins une partie qui s'étend en saillie par rapport à la surface planaire restante,
    (c) à former sur ladite configuration, une couche (18) en un matériau isolant comprenant un verre au germanosilicate,
    (d) à aplanir ladite couche,
    (e) à attaquer par un agent d'attaque humide ladite couche et ladite configuration à des vitesses d'attaque prédéterminées, et
    (f) à achever ladite étape d'attaque humide lorsqu'une épaisseur prédéterminée de ladite couche ait été atteinte, ladite épaisseur prédéterminée étant choisie de telle manière qu'au moins une partie de la configuration (14,16) soit exposée,
    procédé dans lequel la vitesse d'attaque de l'étape (e) est
    - soit à peu près la même pour ladite configuration et ladite couche de manière à maintenir une surface à peu près planaire,
    - soit différente pour ladite configuraiton et ladite couche de manière à obtenir un degré souhaité de planéité.
  2. Un procédé suivant la revendication 1, caractérisé en ce que ladite étape (b) consiste à oxyder ladite surface dudit substrat.
  3. Un procédé selon la revendication 2, caractérisé en ce qu'il consiste à former une couche d'oxyde sur ladite surface planaire restante entre l'exécution des étapes (b) et (c).
  4. Un procédé selon la revendication 3, caractérisé en ce que ledit verre comprend du P₂O₅.
  5. Un procédé selon la revendication 4, caractérisé en ce que ledit verre comprend 54% de SiO₂, 42% de GeO₂ et 4% de P₂O₅.
  6. Un procédé suivant l'une quelconque des revendications 3 à 5, caractérisé en ce que ladite étape (d) consiste à chauffer ledit verre pour provoquer son refusion et pour fournir une surface planaire.
  7. Un procédé selon la revendication 6, caractérisé en ce qu'il consiste à chauffer ledit verre dans la plage allant de 850°C à 1100°C.
  8. Un procédé selon l'une quelconque des revendications 1 à 7, caractérisé en ce que ladite étape (e) consiste à procéder à une attaque humide au moyen d'un agent d'attaque qui ne réagit pas avec le silicium.
  9. Un procédé selon la revendication 8, caractérisé en ce que l'étape d'attaque humide est réalisée à l'aide d'un agent qui comprend l'acide fluorhydrique, le fluorure d'ammonium et de l'eau désionisée.
  10. Un procédé selon la revendication 9, caractérisé en ce que ledit agent d'attaque comprend 11,8% d'acide fluorhydrique, 45,4% de fluorure d'ammonium et 42,7% d'eau désionisée.
  11. Un procédé suivant la revendication 10, caractérisé en ce que ledit agent d'attaque est maintenu à une température allant de 15°C à 30°C.
  12. Un procédé suivant la revendication 1, caractérisé en ce que ledit verre comprend du SiO₂ dans la plage allant de 5% à 80%.
  13. Un procédé selon la revendication 1, caractérisé en ce que ledit verre comprend du GeO₂ dans la plage allant de 10% à 100%.
  14. Un procédé selon la revendication 4, caractérisé en ce que ledit verre comprend du P₂O₅ dans la plage allant jusqu'à 10%.
  15. Un procédé suivant l'une quelconque des revendications 1 à 14, caractérisé en ce que l'étape (f) consiste à arrêter l'étape d'attaque lorsque ladite surface planaire du substrat est atteinte.
  16. Un procédé suivant l'une quelconque des revendications 1 à 14, caractérisé en ce que l'étape (f) consiste à arrêter l'étape d'attaque avant que ladite surface planaire du substrat ne soit atteinte.
EP85400163A 1984-02-03 1985-02-01 Procédé de planarisation pour semi-conducteurs et structures fabriquées selon ce procédé Expired - Lifetime EP0154573B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US576665 1984-02-03
US06/576,665 US4539744A (en) 1984-02-03 1984-02-03 Semiconductor planarization process and structures made thereby

Publications (3)

Publication Number Publication Date
EP0154573A2 EP0154573A2 (fr) 1985-09-11
EP0154573A3 EP0154573A3 (en) 1989-06-21
EP0154573B1 true EP0154573B1 (fr) 1993-04-07

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US (1) US4539744A (fr)
EP (1) EP0154573B1 (fr)
JP (1) JPS6122631A (fr)
CA (1) CA1232368A (fr)
DE (1) DE3587238T2 (fr)

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JPS5246784A (en) * 1975-10-11 1977-04-13 Hitachi Ltd Process for production of semiconductor device
JPS52131471A (en) * 1976-04-28 1977-11-04 Hitachi Ltd Surface treatment of substrate
EP0060205B1 (fr) * 1981-03-16 1986-10-15 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Verres binaires à bas point de fusion pour aplanir les surfaces de circuits intégrés contenant des rainures d'isolation
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EP0060783B1 (fr) * 1981-03-16 1985-09-18 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Procédé de formation d'un mince film de verre sur un substrat semi-conducteur
DE3264723D1 (en) * 1981-03-16 1985-08-22 Fairchild Camera Instr Co Low melting temperature glass for use over aluminium interconnects of an integrated circuit structure
JPS5828838A (ja) * 1981-08-14 1983-02-19 Comput Basic Mach Technol Res Assoc 薄膜磁気ヘッドの製造方法
JPS58197843A (ja) * 1982-05-14 1983-11-17 Toshiba Corp 半導体装置の製造方法
JPS59141231A (ja) * 1983-02-01 1984-08-13 Mitsubishi Electric Corp 半導体装置の製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Handbook of Thin Film Technology, Ed L.I. Maissel + R. Glang, Mcgraw Hill, p. 11-43 to 11-44 and 7-39 *

Also Published As

Publication number Publication date
EP0154573A2 (fr) 1985-09-11
CA1232368A (fr) 1988-02-02
DE3587238D1 (de) 1993-05-13
EP0154573A3 (en) 1989-06-21
DE3587238T2 (de) 1993-08-19
JPS6122631A (ja) 1986-01-31
US4539744A (en) 1985-09-10

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