DE3587238D1 - Planarisierungsverfahren fuer halbleiter und nach diesem verfahren hergestellte strukturen. - Google Patents

Planarisierungsverfahren fuer halbleiter und nach diesem verfahren hergestellte strukturen.

Info

Publication number
DE3587238D1
DE3587238D1 DE8585400163T DE3587238T DE3587238D1 DE 3587238 D1 DE3587238 D1 DE 3587238D1 DE 8585400163 T DE8585400163 T DE 8585400163T DE 3587238 T DE3587238 T DE 3587238T DE 3587238 D1 DE3587238 D1 DE 3587238D1
Authority
DE
Germany
Prior art keywords
semiconductors
structures produced
planarization
planarization method
structures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585400163T
Other languages
English (en)
Other versions
DE3587238T2 (de
Inventor
Greg Burton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Publication of DE3587238D1 publication Critical patent/DE3587238D1/de
Application granted granted Critical
Publication of DE3587238T2 publication Critical patent/DE3587238T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Weting (AREA)
  • Drying Of Semiconductors (AREA)
DE8585400163T 1984-02-03 1985-02-01 Planarisierungsverfahren fuer halbleiter und nach diesem verfahren hergestellte strukturen. Expired - Lifetime DE3587238T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/576,665 US4539744A (en) 1984-02-03 1984-02-03 Semiconductor planarization process and structures made thereby

Publications (2)

Publication Number Publication Date
DE3587238D1 true DE3587238D1 (de) 1993-05-13
DE3587238T2 DE3587238T2 (de) 1993-08-19

Family

ID=24305430

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585400163T Expired - Lifetime DE3587238T2 (de) 1984-02-03 1985-02-01 Planarisierungsverfahren fuer halbleiter und nach diesem verfahren hergestellte strukturen.

Country Status (5)

Country Link
US (1) US4539744A (de)
EP (1) EP0154573B1 (de)
JP (1) JPS6122631A (de)
CA (1) CA1232368A (de)
DE (1) DE3587238T2 (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4612701A (en) * 1984-03-12 1986-09-23 Harris Corporation Method to reduce the height of the bird's head in oxide isolated processes
US4708767A (en) * 1984-10-05 1987-11-24 Signetics Corporation Method for providing a semiconductor device with planarized contacts
EP0490877A3 (en) 1985-01-22 1992-08-26 Fairchild Semiconductor Corporation Interconnection for an integrated circuit
US4649638A (en) * 1985-04-17 1987-03-17 International Business Machines Corp. Construction of short-length electrode in semiconductor device
FR2582445B1 (fr) * 1985-05-21 1988-04-08 Efcis Procede de fabrication de transistors mos a electrodes de siliciure metallique
US4935095A (en) * 1985-06-21 1990-06-19 National Semiconductor Corporation Germanosilicate spin-on glasses
JPS62282446A (ja) * 1986-05-31 1987-12-08 Toshiba Corp 半導体装置の製造方法
US4983537A (en) * 1986-12-29 1991-01-08 General Electric Company Method of making a buried oxide field isolation structure
NL8700541A (nl) * 1987-03-06 1988-10-03 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een plak silicium plaatselijk wordt voorzien van veldoxidegebieden.
US4721548A (en) * 1987-05-13 1988-01-26 Intel Corporation Semiconductor planarization process
US5114867A (en) * 1987-07-15 1992-05-19 Rockwell International Corporation Sub-micron bipolar devices with method for forming sub-micron contacts
US5014107A (en) * 1987-07-29 1991-05-07 Fairchild Semiconductor Corporation Process for fabricating complementary contactless vertical bipolar transistors
US4986878A (en) * 1988-07-19 1991-01-22 Cypress Semiconductor Corp. Process for improved planarization of the passivation layers for semiconductor devices
US5006476A (en) * 1988-09-07 1991-04-09 North American Philips Corp., Signetics Division Transistor manufacturing process using three-step base doping
US4988405A (en) * 1989-12-21 1991-01-29 At&T Bell Laboratories Fabrication of devices utilizing a wet etchback procedure
US5212116A (en) * 1990-06-18 1993-05-18 At&T Bell Laboratories Method for forming planarized films by preferential etching of the center of a wafer
US5252143A (en) * 1990-10-15 1993-10-12 Hewlett-Packard Company Bipolar transistor structure with reduced collector-to-substrate capacitance
US5290396A (en) * 1991-06-06 1994-03-01 Lsi Logic Corporation Trench planarization techniques
US5350492A (en) * 1992-09-18 1994-09-27 Advanced Micro Devices, Inc. Oxide removal method for improvement of subsequently grown oxides
US5350491A (en) * 1992-09-18 1994-09-27 Advanced Micro Devices, Inc. Oxide removal method for improvement of subsequently grown oxides for a twin-tub CMOS process
KR100304761B1 (ko) * 1993-11-24 2001-12-15 이데이 노부유끼 반도체장치의2층게이트구조및그제조방법
US5554560A (en) * 1994-09-30 1996-09-10 United Microelectronics Corporation Method for forming a planar field oxide (fox) on substrates for integrated circuit
US5413953A (en) * 1994-09-30 1995-05-09 United Microelectronics Corporation Method for planarizing an insulator on a semiconductor substrate using ion implantation
US5849625A (en) * 1994-12-07 1998-12-15 United Microelectronics Coporation Planar field oxide isolation process for semiconductor integrated circuit devices using liquid phase deposition
JPH08316223A (ja) * 1995-05-16 1996-11-29 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5882985A (en) * 1995-10-10 1999-03-16 Advanced Micro Devices, Inc. Reduction of field oxide step height during semiconductor fabrication
WO1997017729A1 (en) * 1995-11-10 1997-05-15 Advanced Micro Devices, Inc. Silicon dioxide spacer for locos or recessed locos
US5672538A (en) * 1995-12-04 1997-09-30 Taiwan Semiconductor Manufacturing Company, Ltd Modified locus isolation process in which surface topology of the locos oxide is smoothed
US5837603A (en) * 1996-05-08 1998-11-17 Harris Corporation Planarization method by use of particle dispersion and subsequent thermal flow
US5930647A (en) 1997-02-27 1999-07-27 Micron Technology, Inc. Methods of forming field oxide and active area regions on a semiconductive substrate
US6589875B1 (en) * 2001-08-02 2003-07-08 Advanced Micro Devices, Inc. Method of selectively processing wafer edge regions to increase wafer uniformity, and system for accomplishing same
US10560368B2 (en) 2017-01-25 2020-02-11 Airties Kablosuz Iletisim Sanayi Ve Dis Ticaret A.S. Island topologies and routing in hybrid mesh networks
DE102020209927A1 (de) 2020-08-06 2022-02-10 Robert Bosch Gesellschaft mit beschränkter Haftung Einebnen von Materialerhebungen auf Halbleiterschichten

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5834930B2 (ja) * 1973-05-18 1983-07-29 松下電子工業株式会社 カクサンヨウフジユンブツガンユウサンカブツマク ノ ジヨキヨホウホウ
JPS5214371A (en) * 1975-07-25 1977-02-03 Hitachi Ltd Flattening method of concave-convex surface
JPS5226182A (en) * 1975-08-25 1977-02-26 Hitachi Ltd Manufacturing method of semi-conductor unit
JPS5246784A (en) * 1975-10-11 1977-04-13 Hitachi Ltd Process for production of semiconductor device
JPS52131471A (en) * 1976-04-28 1977-11-04 Hitachi Ltd Surface treatment of substrate
EP0060784B1 (de) * 1981-03-16 1985-07-17 FAIRCHILD CAMERA & INSTRUMENT CORPORATION Niedrigschmelzendes Glas zur Verwendung über Aluminium-Zwischenverbindungen einer integrierten Schaltkreisstruktur
DE3266277D1 (en) * 1981-03-16 1985-10-24 Fairchild Camera Instr Co Process of forming a thin glass film on a semiconductor substrate
US4417914A (en) * 1981-03-16 1983-11-29 Fairchild Camera And Instrument Corporation Method for forming a low temperature binary glass
DE3273863D1 (en) * 1981-03-16 1986-11-20 Fairchild Camera Instr Co Low temperature melting binary glasses for leveling surfaces of integrated circuits containing isolation grooves
JPS5828838A (ja) * 1981-08-14 1983-02-19 Comput Basic Mach Technol Res Assoc 薄膜磁気ヘッドの製造方法
JPS58197843A (ja) * 1982-05-14 1983-11-17 Toshiba Corp 半導体装置の製造方法
JPS59141231A (ja) * 1983-02-01 1984-08-13 Mitsubishi Electric Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0154573B1 (de) 1993-04-07
CA1232368A (en) 1988-02-02
EP0154573A2 (de) 1985-09-11
DE3587238T2 (de) 1993-08-19
JPS6122631A (ja) 1986-01-31
EP0154573A3 (en) 1989-06-21
US4539744A (en) 1985-09-10

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